KR20230115815A - Memory system - Google Patents

Abstract

[Problem] To provide a memory system capable of appropriately accessing a semiconductor memory device.
[Solution Means] A memory system includes a memory controller 10 and a semiconductor memory device 20 . The memory controller 10 transmits the command and address and the first test data to the semiconductor memory device 20, and receives first response information indicating that no error has been detected from the semiconductor memory device 20. , data to be read or written is transmitted or received to and from the semiconductor memory device 20. The semiconductor memory device 20 detects an error in the command and address using the first test data when the command and address and the first test data are received, and when no error is detected, first response information and transmits or receives data to be read or written to and from the memory controller 10 when no error is detected in the command or address.

Description

Memory system {MEMORY SYSTEM}

The present invention relates to a memory system including a memory controller and a semiconductor memory device.

Conventionally, a memory system is known that includes a semiconductor memory device such as DRAM (Dynamic Random Access Memory) and a memory controller that performs control such as reading or writing with respect to the semiconductor memory device (for example, Patent Document 1).

In such a memory system, when a command packet including a command and an address is received from the memory controller, the semiconductor memory device stores a storage area corresponding to the address based on the contents of the command (e.g., a read command and a write command). It is configured to read or write data of (for example, a memory cell).

JP 2002-63791 A

However, in a conventional memory system, if an error (bit error) occurs in a command or address during transfer of a command packet from a memory controller to a semiconductor memory device, the content or address of the command may be changed. This may make it difficult to appropriately access the semiconductor storage device.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a memory system capable of appropriately accessing a semiconductor memory device.

In order to solve the above object, the present invention includes a memory controller and a semiconductor memory device, wherein the memory controller transmits a command and an address and first test data for error detection of the command and the address to the semiconductor memory device. data to be read or written to the address based on the command when first response information indicating that transmission to the device and that no error has been detected with the command and the address is received from the semiconductor memory device; and transmits or receives data from or to a semiconductor memory device, wherein the semiconductor memory device, when receiving the command, the address, and the first test data from the memory controller, performs the first check error detection of the command and the address using data, and sending the first response information to the memory controller when no error is detected in the command and the address; When not detected, there is provided a memory system configured to transmit or receive data to be read or written to the address based on the command to or from the memory controller (Invention 1).

According to this invention (invention 1), the memory controller, when receiving the first response information indicating that no error is detected in the command and address from the semiconductor memory device, transfers data to be read or written to the address to the semiconductor memory device. It becomes possible to transmit or receive between devices. This makes it possible to suppress inappropriate access due to a change in the content or address of a command during transmission of a command packet, so that appropriate access can be made to the semiconductor storage device.

In the above invention (Invention 1), the semiconductor memory device, when an error is detected in either the command or the address, second response information indicating that an error was detected in either the command or the address. to the memory controller, and the memory controller may be configured to, when receiving the second response information from the semiconductor memory device, retransmit the command and the address to the semiconductor memory device (invention 2).

According to this invention (invention 2), when an error is detected in either the command or the address, the memory controller retransmits the command and address to the semiconductor memory device, so that the semiconductor memory device does not initiate an erroneous operation and allows access. You can restart from the beginning.

In the above invention (Inventions 1 to 2), one of the memory controller and the semiconductor memory device transmits the read or written data and the second test data for error detection of the data to the memory controller and the semiconductor memory device. is configured to transmit to the other of the devices, and the other of the memory controller and the semiconductor memory device, when receiving the data and the second test data, uses the second test data to detect an error in the data detection, and when no error is detected in the data, third response information indicating that no error is detected in the data is transmitted to one of the memory controller and the semiconductor memory device (Invention 3) .

According to this invention (invention 3), since it becomes possible to suppress a state in which errors are included in data to be read or written, the integrity of the data can be ensured.

In the above invention (invention 3), the other of the memory controller and the semiconductor memory device, when an error is detected in the data, sends fourth response information indicating that an error is detected in the data to the memory controller and It may be configured to transmit to one of the semiconductor memory devices and to wait for retransmission of the data from one of the memory controller and the semiconductor memory device until a predetermined time elapses (Invention 4).

According to this invention (invention 4), even when an error is detected in the data, the other of the memory controller and the semiconductor memory device waits for the data to be retransmitted, thereby continuing access related to reading or writing of the data. it becomes possible to do This makes it possible to increase access efficiency compared to, for example, a case where access related to reading or writing of this data is resumed from the beginning (when commands and addresses are retransmitted).

In the above invention (invention 4), one of the memory controller and the semiconductor memory device, when receiving the fourth response information, transmits the data and the second test data corresponding to the data to the memory controller. and retransmission to the other of the semiconductor storage devices (Invention 5).

According to this invention (invention 5), when an error is detected in data, either the memory controller or the semiconductor memory device retransmits the data, so that the data can be read or written again.

In the above invention (Inventions 4 to 5), when the other of the memory controller and the semiconductor memory device does not retransmit the data from one of the memory controller and the semiconductor memory device until the predetermined time elapses In this case, it may be configured to cancel waiting for retransmission of the data (Invention 6).

According to this invention (invention 6), the other of the memory controller and the semiconductor memory device can process another read or write access by canceling waiting for retransmission of the corresponding data when the data is not retransmitted. do. In this way, the processing efficiency of access can be improved.

In the above inventions (Inventions 1 to 6), the semiconductor memory device may include a plurality of banks accessed in an interleaved manner (Invention 7).

According to this invention (invention 7), since access to a plurality of banks can be performed simultaneously and in parallel, access to the semiconductor memory can be speeded up.

In the above inventions (Inventions 1 to 7), the semiconductor memory device is configured to internally generate a refresh request signal for performing refresh, from when the refresh request signal is generated until the refresh is executed. When an error is detected in any one of the command, the address, and the data received from the memory controller during It may also be configured to stop the execution of the refresh until n is not detected (Invention 8).

According to this invention (invention 8), it is possible to suppress delay in access due to execution of refresh by stopping execution of refresh until no error is detected in any of the commands, addresses, and data. will do

In the above inventions (Inventions 1 to 7), the semiconductor memory device is configured to internally generate a refresh request signal for performing refresh, from when the refresh request signal is generated until the refresh is executed. transmits fifth response information indicating that the refresh is executed to the memory controller when an error is detected in any of the command, the address, and the data received from the memory controller during It may be configured to execute (Invention 9).

According to this invention (invention 9), refresh is executed when an error is detected in any of the command, address, and data, so that, for example, retransmission of any one of the command, address, and data is repeatedly performed. It becomes possible to suppress the loss of stored information in the semiconductor memory device due to the fact that refresh is not performed during the interim.

In the above inventions (Inventions 1 to 9), the semiconductor memory device may be a pseudo-static random access memory (Invention 10).

According to this invention (invention 10), appropriate access can be made to the pseudo-static random access memory.

In the above inventions (1 to 10), the memory controller, when receiving a write or read request to the semiconductor memory device from the host device, determines a transmission method of an address data signal transmitted and received between the memory controller and the semiconductor memory device. a request control unit that generates a conversion signal for conversion; and a first sequence control unit that converts a transmission method of the address data signal based on the conversion signal, wherein the first sequence control unit, based on the conversion signal, A first serializer/deserializer (SerDes) that serializes or serializes an address data signal, and a first error control unit that generates the first test data using the command and the address, 1 SerDes generates and outputs a write command and address to the first error control unit when the request control unit receives a write request and the conversion signal is input from the request control unit, and the generated write command and when the first test data corresponding to the address is input from the first error control unit, transmitting the generated write command and address and the first test data as the address data signals to the semiconductor memory device; outputting write data received from the host device to the first error controller when first response information indicating that no error has been detected in the command or address is received as the address data signal from the semiconductor memory device; (Invention 11).

According to this invention (invention 11), the memory controller, when receiving from the semiconductor memory device the first response information indicating that no error has been detected in the write command and address, write data received from the host device as a first error message. It becomes possible to output to the detection unit.

In the invention (invention 11), the first error control unit is configured to generate second check data for error detection of the write data using the write data, and the SerDes performs the second check When data is input from the first error control section, the second inspection data and the write data may be transmitted to the semiconductor storage device as the address data signals (Invention 12).

According to this invention (invention 12), it becomes possible for the memory controller to transmit write data and second test data to the semiconductor memory device.

In the above invention (inventions 11 and 12), the first error control section receives second response information indicating that an error has been detected in either the write command or the address as the address data signal from the semiconductor memory device. case, generate a signal for retransmitting the write command and address and the first test data, wherein the first SerDes receives the second response information as the address data signal from the semiconductor memory device. As a case, when a signal for retransmitting the write command and address and the first test data is input from the first error control unit, the write command and address and the first test data are used as the address data signal in the semiconductor device. It may be configured to retransmit to the storage device (Invention 13).

According to this invention (invention 13), when an error is detected in either the command or the address, the memory controller retransmits the command and the address to the semiconductor memory device, so that the semiconductor memory device does not start an erroneous operation and access is restored. You can restart from the beginning.

In the above invention (inventions 11 to 13), the semiconductor memory device includes a second sequence control unit that converts a transmission method of the address data signal transmitted and received with the memory controller, and the second sequence control unit , a second serializer/deserializer (SerDes) for serializing or serializing the address data signal, and error detection of the command and the address using the first check data received from the memory controller. A second error control unit, wherein the second SerDes, when receiving the command, the address, and the first check data as the address data signals from the memory controller, the command, the address, and the first check data Converting data into a serial transmission method and outputting the data to the second error control unit, converting the first response information into a parallel transmission method when the first response information is input from the second error control unit, and 1 outputs response information as the address data signal to a memory controller, outputs a signal representing the content of the command to a command control unit that generates an internal command based on the command, and outputs a signal representing the address to the address output to an address control unit that controls to activate corresponding word lines and bit lines, and converting the second response information into a parallel transmission method when the second response information is input from the second error control unit; It may be configured to transmit second response information as the address data signal to the memory controller (Invention 14).

According to this invention (invention 14), the semiconductor memory device can change the transmission method of the address data signal transmitted and received with the memory controller, and command commands using the first test data received from the memory controller. and address error detection. In addition, the semiconductor memory device becomes capable of processing the command when no error is detected in the command or address (when the first response information is generated), and an error occurs in either the command or the address. is detected (when the second response information is generated), it becomes possible to transmit the second response information to the memory controller.

In the above invention (invention 14), the second error control unit is configured to perform error detection of the write data using second check data for error detection of the write data, and the second SerDes comprises: outputting the write data and the second check data to the second error controller when receiving the write data and second check data for error detection of the write data as address data signals from the memory controller; and transmits the fourth response information as the address data signal to the memory controller when fourth response information indicating that an error has been detected in the write data is input from the second error control unit ( Invention 15).

According to this invention (invention 15), the semiconductor memory device can transmit the fourth response information to the memory controller when an error is detected in write data.

According to the memory system of the present invention, appropriate access can be made to the semiconductor memory device.

1 is a block diagram showing a configuration example of a memory system according to a first embodiment of the present invention.
Fig. 2 is a time chart showing the time transition of signals in the semiconductor memory device when no error is included in the command or address.
Fig. 3 is a time chart showing the time transition of signals in the semiconductor memory device when an error is included in either a command or an address.
Fig. 4 is a time chart showing the time transition of signals in the semiconductor memory device when errors are included in the data.
Fig. 5 is a time chart showing the time transition of signals in the semiconductor memory device when a predetermined time elapses while waiting for data retransmission.
6 is a flowchart showing an example of the operation of the semiconductor memory device.
7(a) and (b) are time charts showing time transitions of signals in the semiconductor memory device in the memory system according to the second embodiment of the present invention.
8(a) and (b) are time charts showing the time transition of signals in the semiconductor memory device.
9 is a time chart showing the time transition of signals in the semiconductor memory device in the memory system according to the third embodiment of the present invention.
Fig. 10 is a time chart showing the time transition of signals in the semiconductor memory device.
Fig. 11 is a diagram showing an example of bit allocation of commands and addresses.
12 is a time chart showing the time transition of the data strobe signal.

Hereinafter, a semiconductor memory device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. However, this embodiment is an illustration, and this invention is not limited to this.

In this specification and the like, expressions such as “first,” “second,” and “third” are used to distinguish certain components from other components, and the number, order, or priority of the components. It is not intended to limit the figure or the like. For example, when there is a description of “first element” and “second element”, it does not mean that only two elements of “first element” and “second element” are employed, and “first element” It does not mean that " must precede the "second element".

(First Embodiment)

1 is a block diagram showing a configuration example of a memory system according to a first embodiment of the present invention. As shown in FIG. 1 , the memory system according to the present embodiment includes a memory controller 10 and a semiconductor memory device 20 .

In this embodiment, a case where the semiconductor memory device 20 is a pseudo-static random access memory (pSRAM) will be described as an example. Here, pSRAM is a semiconductor memory device having an interface compatible with SRAM (Static Random Access Memory). Further, pSRAM uses DRAM (Dynamic Random Access Memory) as a memory cell array to store data, redesigns the DRAM access interface, and makes it compatible with the SRAM access interface.

In this embodiment, the case where the semiconductor memory device 20 is an address data multiplex interface type pSRAM as a clock synchronization type pSRAM that receives signals in synchronization with a clock signal is shown as an example. An address data multiplex interface type pSRAM has an address data terminal configured to input each of an address signal and a data signal. In addition, in the pSRAM of the present embodiment, a case in which a double data rate (DDR) method is employed as a data transfer method is shown as an example, but the pSRAM may employ a single data rate (SDR) method.

In this embodiment, the memory controller 10 includes a command (indicated as Operation in the figure) and an address (indicated as Address in the figure), and first test data for error detection of the command and address (in the figure , indicated as CheckA) to the semiconductor memory device 20, and first response information (indicated as ReplyA(OK) in the figure) indicating that no error has been detected in the command and address is sent to the semiconductor memory device 20. When received from (20), data (indicated as Data in the drawing) to be read or written to an address based on a command is transmitted or received to and from the semiconductor memory device 20. .

On the other hand, when the semiconductor memory device 20 receives a command and an address and first test data from the memory controller 10, the command and address error detection is performed using the first test data, and the command and address are detected. sending first response information (ReplyA(OK)) to the memory controller 10 when no error is detected in , and reading or reading the address based on the command when no error is detected in the command or address It is configured to transmit or receive data to be written to and from the memory controller 10.

Further, in the present embodiment, the semiconductor memory device 20, when an error is detected in either the command or the address, second response information indicating that an error was detected in either the command or the address (shown in the figure). , indicated as ReplyA(NG)) to the memory controller 10. On the other hand, the memory controller 10 is configured to retransmit a command and an address to the semiconductor memory device 20 when second response information (ReplyA(NG)) is received from the semiconductor memory device 20 . In this case, when an error is detected in either the command or the address, the memory controller 10 retransmits the command and address to the semiconductor memory device 20, so that access to the semiconductor memory device 20 can be resumed from the beginning. can

Further, in the present embodiment, the memory controller 10 (one of the memory controller 10 and the semiconductor memory device 20) includes data to be written and second inspection data for error detection of the data (shown in the figure). , indicated as CheckD) to the semiconductor memory device 20 (the other of the memory controller 10 and the semiconductor memory device 20). On the other hand, the semiconductor memory device 20, when receiving the data and the second test data CheckD, performs data error detection using the second test data CheckD, and if no error is detected in the data, In this case, third response information (indicated as ReplyD(OK) in the figure) indicating that no error has been detected in the data is transmitted to the memory controller 10. In this case, since it becomes possible to suppress a state in which errors are included in the data to be read or written, the integrity of the data can be ensured.

Further, in this embodiment, the semiconductor memory device 20 (the other of the memory controller 10 and the semiconductor memory device 20) indicates that an error was detected in the data when an error is detected in the data. Sending fourth response information (indicated as ReplyD(NG) in the figure) to the memory controller 10 (one of the memory controller 10 and the semiconductor memory device 20), and data from the memory controller 10 is configured to wait until a predetermined time elapses before retransmission. In this case, even if an error is detected in the data, it becomes possible for the semiconductor memory device 20 to continuously perform access related to writing the data by waiting for the data to be resent. This makes it possible to increase the access efficiency compared to, for example, the case where access related to writing this data is resumed from the beginning (when the command and address are resent).

Further, in this embodiment, the memory controller 10 (one of the memory controller 10 and the semiconductor memory device 20) receives the fourth response information (ReplyD(NG)), and the corresponding data and , and retransmits the second test data CheckD corresponding to the corresponding data to the semiconductor memory device 20 (the other of the memory controller 10 and the semiconductor memory device 20). As a result, when an error is detected in data, the memory controller 10 retransmits the data, so that the data can be written again.

Further, in this embodiment, the semiconductor memory device 20 (the other of the memory controller 10 and the semiconductor memory device 20) continues to operate until a predetermined time elapses until the memory controller 10 (the memory controller 10 ) and the semiconductor memory device 20) to release waiting for retransmission of data when data is not retransmitted. This makes it possible for the semiconductor memory device 20 to process another read or write access by canceling waiting for retransmission of the data when the data is not retransmitted. Therefore, the processing efficiency of access can be improved.

Referring to Fig. 1, the configuration of the memory controller 10 in this embodiment will be described. The memory controller 10 is connected to an external host device (not shown), and accesses the semiconductor memory device 20, such as reading or writing, in response to commands from the host device. For example, the memory controller 10 sends a write request to write data to the semiconductor memory device 20 or a read request to read data from the semiconductor memory device 20 from the host device. Upon reception, the chip select signal /CE is asserted (low level) and transmitted to the semiconductor memory device 20. In addition, the memory controller 10 transmits the clock signal received from the host device to the semiconductor memory device 20 as an external clock signal CLK.

In this embodiment, the memory controller 10 includes a request control unit 11 and a sequence control unit 12. The request control unit 11 and the sequence control unit 12 may be constituted by dedicated hardware devices or logic circuits.

In addition, the memory controller 10 includes a CPU (Central Processing Unit) (not shown), a storage device (not shown) such as RAM (Random Access Memory), a semiconductor memory device 20, and a host device. You may provide an interface (not shown) for transmitting and receiving signals between them. Here, the CPU of the memory controller 10 may realize the functions of the request control unit 11 and the sequence control unit 12 by, for example, reading and executing programs stored in the storage device.

When a write or read request to the semiconductor memory device 20 is received from the host device, the request control unit 11 transmits an address data signal ADQ transmitted and received between the memory controller 10 and the semiconductor memory device 20. It is configured to generate a conversion signal for converting modes. More specifically, when the request control unit 11 receives a write request for writing data into the semiconductor memory device 20 from the host device, it transmits the request from the memory controller 10 to the semiconductor memory device 20. Outputs the conversion signal deson for converting the address data signal ADQ from the serial transmission method to the parallel transmission method of a predetermined number of bits (eg, 8 bits) (serial-to-parallel conversion) to the sequence controller 12 do.

In addition, when the request control unit 11 receives a read request for reading data from the semiconductor memory device 20 from the host device, it outputs a conversion signal deson to the sequence control unit 12, A conversion signal (seron) for converting (serial conversion) the signal (for example, read data, etc.) transmitted from 20 to the memory controller 10 from the parallel transmission method to the serial transmission method is transmitted to the sequence controller 12. print out

The sequence control unit 12 is configured to convert the transmission method of the address data signal ADQ based on the conversion signal deson. Further, the sequence control unit 12 includes a serializer/deserializer (SerDes) 12a and an error control unit 12b. The SerDes 12a mutually converts a signal transmitted or received between the memory controller 10 and the semiconductor memory device 20 between a serial transmission method and a parallel transmission method. In the present embodiment, a case where the SerDes 12a serializes and parallelizes write data and serializes read data is described as an example, but the SerDes 12a converts write data from 64 bits to 8 bits, for example. It may be configured to perform serial conversion into bits or the like and serial-to-parallel conversion of read data. In the present embodiment, the sequence control unit 12 is an example of the "first sequence control unit" of the present invention, and the SerDes 12a is the "first serializer/serializer (SerDes)" of the present invention. This is an example, and the error control section 12b is an example of the "first error control section" of the present invention.

The SerDes 12a receives a read command or a write command (for example, when the request control unit 11 receives a write request or a read request, and when a conversion signal deson is input from the request control unit 11). Operation) and an address are generated and output to the error controller 12b. Next, the SerDes 12a, when the first check data CheckA for error detection of the command (Operation) and the address (Address) is input from the error controller 12b, the command (Operation), address (Address) and The first check data CheckA is converted into a parallel transmission method. The SerDes 12a transmits the command (Operation), the address (Address), and the first check data (CheckA) to the semiconductor memory device 20 as an address data signal (ADQ).

In addition, the SerDes 12a transmits first response information (ReplyA (OK)) indicating that no error is detected in the write command (Operation) and the address (Address) as the address data signal (ADQ) to the semiconductor memory device 20 When received from the host device, the write data (Data) received from the host device is output to the error control unit 12b. Next, when the second check data CheckD for error detection of the write data Data is input from the error controller 12b, the SerDes 12a converts the second check data CheckD and the write data Data. Convert to parallel transmission method. Then, the SerDes 12a transmits the second check data CheckD and write data Data as the address data signal ADQ to the semiconductor memory device 20 .

In addition, the SerDes 12a transmits the second response information (ReplyA(NG)) indicating that an error is detected in any one of the write command (Operation) and the address (Address) as the address data signal (ADQ) to the semiconductor memory device ( 20), when a signal (retrywr) for retransmitting the write command (Operation), the address (Address), and the first check data (CheckA) is input from the error controller 12b, the write command (Operation ), the address Address and the first check data CheckA are retransmitted to the semiconductor memory device 20 as the address data signal ADQ.

In addition, the SerDes 12a transmits the second response information (ReplyA (NG)) indicating that an error is detected in any of the read command (Operation) and the address (Address) as the address data signal (ADQ) to the semiconductor memory device ( 20), when a signal (retryrd) for retransmitting the read command (Operation), the address (Address), and the first test data (CheckA) is input from the error controller 12b, the read command (Operation ), the address Address and the first check data CheckA are retransmitted to the semiconductor memory device 20 as the address data signal ADQ.

Further, when the SerDes 12a receives the fourth response information (ReplyD(NG)) indicating that an error has been detected in the write data (Data) as the address data signal (ADQ) from the semiconductor memory device 20, The write data Data and the second check data CheckD corresponding to the write data Data are retransmitted to the semiconductor memory device 20 as the address data signal ADQ.

When a command (Operation) and an address (Address) are input from the SerDes (12a), the error controller 12b generates first check data (CheckA) for error detection of the command (Operation) and address (Address), The generated first check data CheckA is output to the SerDes 12a. Here, the first check data CheckA may be composed of, for example, a parity code or a Cyclic Redundancy Checking (CRC) code.

In addition, when the write data Data is input from the SerDes 12a, the error control unit 12b generates second check data CheckD for error detection of the write data Data, and the generated second check data (CheckD) is output to the SerDes (12a). Here, like the first test data CheckA, the second test data CheckD may be configured with, for example, a parity code or a Cyclic Redundancy Checking (CRC) code.

In addition, the error control unit 12b, when second response information (ReplyA (NG)) indicating that an error is detected in either the write command (Operation) or the address (Address) is transmitted from the semiconductor memory device 20 Then, a signal (retrywr) for retransmitting the write command (Operation), the address (Address), and the first check data (CheckA) is output to the SerDes 12a.

In addition, the error control unit 12b, when the second response information (ReplyA (NG)) indicating that an error is detected in either the read command (Operation) or the address (Address) is transmitted from the semiconductor memory device 20 Then, a signal (retryrd) for retransmitting the read command (Operation), the address (Address), and the first check data (CheckA) is output to the SerDes 12a.

Next, the configuration of the semiconductor memory device 20 in this embodiment will be described. The semiconductor memory device 20 includes a sequence control unit 21, a command control unit 22, an address control unit 23, a word line control unit 24, a column control unit 25, a data control unit 26, , a data bus controller 27, a sense amplifier 28, and a memory cell array 29. Each unit 21 to 29 in the semiconductor memory device 20 may be constituted by dedicated hardware devices or logic circuits. In this embodiment, other well-known components such as a power supply circuit, a chip select terminal, a clock terminal, and an address data input/output terminal are not shown in order to simplify the explanation.

The sequence control unit 21 is configured to change the transmission method of the address data signal ADQ transmitted and received with the memory controller 10. Also, the sequence control unit 21 includes a SerDes 21a and an error control unit 21b. Like the SerDes 12a of the memory controller 10, the SerDes 21a transfers signals transmitted or received between the memory controller 10 and the semiconductor memory device 20 to each other between the serial transmission method and the parallel transmission method. convert In the present embodiment, the sequence control unit 21 is configured to transmit the data strobe signal RWDS to the sequence control unit 12 of the memory controller 10. In the present embodiment, the sequence control unit 21 is an example of the "second sequence control unit" of the present invention, and the SerDes 21a is an example of the "second serial converter/serial-to-parallel converter (SerDes)" of the present invention. , and the error control unit 21b is an example of the "second error control unit" of the present invention.

When the SerDes 21a receives the command (Operation), the address (Address), and the first check data (CheckA) as the address data signal (ADQ) from the memory controller 10, the command (Operation), the address (Address) ) and the first check data CheckA are converted into a serial transmission method and output to the error controller 21b.

In addition, the SerDes 21a receives the first response information (ReplyA (OK)) indicating that no error has been detected in the command (Operation) and the address (Address), when input from the error control unit 21b. The information (ReplyA(OK)) is converted in a parallel transmission method, and the first response information (ReplyA(OK)) is transmitted to the memory controller 10 as an address data signal (ADQ). Also, in this case, the SerDes 21a outputs a signal ope indicating the content (read command or write command) of the received command (Operation) to the command control unit 22, and returns the received address (Address). The indicating signal adr is output to the address control unit 23.

In addition, the SerDes 21a receives second response information (ReplyA (NG)) indicating that an error has been detected in any of the command (Operation) and the address (Address) from the error control unit 21b, The second response information (ReplyA(NG)) is converted in a parallel transmission method, and the second response information (ReplyA(NG)) is transmitted to the memory controller 10 as an address data signal (ADQ).

In addition, when the SerDes 21a receives the second check data CheckD and the write data Data as the address data signal ADQ from the memory controller 10, the second check data CheckD and the write data (Data) is converted into a serial transmission method and output to the error control section 21b.

In addition, the SerDes 21a receives the third response information (ReplyD(OK)) indicating that no error is detected in the write data (Data) from the error control unit 21b, the third response information (ReplyD( OK) is converted into a parallel transmission method, and the third response information (ReplyD(OK)) is transmitted to the memory controller 10 as an address data signal ADQ. Also, in this case, the SerDes 21a outputs a signal di indicating the received write data Data to the data control unit 26 .

In addition, the SerDes 21a receives fourth response information (ReplyD(NG)) indicating that an error has been detected in the write data (Data) from the error controller 21b, the fourth response information (ReplyD(NG)). )) is converted into a parallel transmission method, and the fourth response information (ReplyD(NG)) is transmitted to the memory controller 10 as an address data signal (ADQ).

Further, the SerDes 21a outputs the read data Data to the error control unit 21b when a signal do indicating read data is input from the data control unit 26. Then, the SerDes 21a, when the second check data CheckD for error detection of the read data Data is input from the error controller 21b, read data Data and the second check data CheckD. is converted into a parallel transmission method, and the read data Data and the second check data CheckD are transmitted to the memory controller 10 as the address data signal ADQ.

When the command (Operation), the address (Address), and the first check data (CheckA) are input from the SerDes (21a), the error control unit 21b uses the first check data (CheckA) to generate the command (Operation) and address ( Address) error detection. Further, the error control unit 21b, when no error is detected in the command (Operation) or address (Address), first response information (ReplyA) indicating that no error is detected in the command (Operation) or address (Address). (OK)) is output to the SerDes 21a. On the other hand, when an error is detected in either of the command (Operation) and the address (Address), the error control unit 21b indicates that an error has been detected in either the command (Operation) or the address (Address). Response information (ReplyA(NG)) is output to the SerDes 21a.

Also, when the second check data CheckD and the write data Data are input from the SerDes 21a, the error control unit 21b detects an error in the write data Data using the second check data CheckD. do Further, the error controller 21b, when no error is detected in the write data Data, sends third response information (ReplyD(OK)) indicating that no error is detected in the write data Data to the SerDes 21a ) is output to On the other hand, when an error is detected in the write data (Data), the error control unit 21b transmits fourth response information (ReplyD(NG)) indicating that an error is detected in the write data (Data) to the SerDes (21a). print out

In addition, when the read data Data is input from the SerDes 21a, the error control unit 21b generates second test data CheckD for error detection of the read data Data, and the generated second test data (CheckD) is output to the SerDes (21a). Here, the second check data CheckD may be composed of a parity code or a Cyclic Redundancy Checking (CRC) code or the like, as described above.

In addition, the error control unit 21b, when the chip select signal /CE changes from negate (high level) to assert (low level), sends a signal (busy) indicating that read or write access is being processed. It is asserted (high level) and output to the command control unit 22.

The command control unit 22 is configured to generate internal commands based on commands input from the memory controller 10 . Specifically, the command control unit 22, when an asserted (high level) signal (busy) is input from the sequence control unit 21, according to the signal ope input from the sequence control unit 21 Generate internal commands. Here, the generated internal command includes, for example, a read signal, a write signal, a refresh signal, and the like. The command control unit 22 asserts and outputs the signal wlon for activating the word line to the word line control unit 24 according to the generated internal command, and asserts the signal clone for activating the bit line. Assert the signal saon for activating the sense amplifier 28 and output it to the sense amplifier 28. Also, the command control section 22 asserts a signal wloff for inactivating the word line and outputs it to the word line control section 24.

The address controller 23, based on the address input from the memory controller 10, controls to activate the word line and bit line corresponding to the address. Specifically, when the signal adr is input from the sequence control unit 21, the address control unit 23 includes a row address signal ra indicating an activated word line and a column address signal indicating an activated bit line ( ca) to generate Then, the address control section 23 outputs the generated row address signal ra to the word line control section 24 and outputs the generated column address signal ca to the column control section 25.

The word line control section 24, when input from the command control section 22 with the signal wlon asserted, outputs the word line indicated by the row address signal ra input from the address control section 23. The activation signal wl is output to the memory cell array 29 to activate (drive) the corresponding word line. In addition, when the signal wloff is input from the command control unit 22 in an asserted state, the word line controller 24 transmits a signal wl for inactivating the activated word line to the memory cell array 29 ) to disable the corresponding word line.

The column control section 25, when input from the command control section 22 in the asserted state of the signal clon, outputs input from the address control section 23 among a plurality of bit lines in the memory cell array 29. A signal cl for activating the bit line indicated by the column address signal ca is output to the sense amplifier 28.

The data control unit 26 outputs a signal wdb indicating the write data to the data bus control unit 27 when a signal di representing write data is input from the sequence control unit 21 . Further, the data control unit 26 outputs a signal do indicating read data to the sequence control unit 21 when a signal rdb indicating read data is inputted from the data bus control unit 27 .

The data bus controller 27 outputs a signal cdb representing the write data to the sense amplifier 28 when the signal wdb representing the write data is input from the data controller 26 . Also, when the signal cdb indicating read data is inputted from the sense amplifier 28, the data bus control section 27 outputs a signal indicating read data (rdb) to the data control section 26.

The sense amplifier 28 is configured to activate the bit line indicated by the signal cl input from the column control unit 25 when the signal saon is input from the command control unit 22 in an asserted state. A signal bl is outputted to the memory cell array 29 to activate (drive) the corresponding bit line. Then, the sense amplifier 28 reads and writes data to and from the memory cells via the activated bit line. For example, the sense amplifier 28 writes a signal cdb representing write data input from the data bus control unit 27 into the memory cell via an activated bit line. In addition, the sense amplifier 28 outputs data read from the memory cell to the data bus controller 27 via the activated bit line.

The memory cell array 29 includes a plurality of memory cells (not shown) arranged in a matrix (array) form. Data input from the memory controller 10 is stored in each memory cell. Each memory cell may be a well-known 1T1C (one transistor, one capacitor) type memory cell. In addition, each memory cell is connected to one word line of a plurality of word lines and to one one of a plurality of bit lines.

Incidentally, since the details of data read/write control for each memory cell in the memory cell array 29 are the same as well-known techniques, detailed explanations are omitted in this embodiment.

Next, with reference to FIG. 2, an example of the operation of the semiconductor memory device 20 in this embodiment will be described. Fig. 2 is a time chart showing the time transition of signals in the semiconductor memory device 20 when no errors are included in the commands and addresses. Incidentally, here, a case where a write command (Operation) is input from the memory controller 10 will be described as an example.

First, when the semiconductor memory device 20 receives a command (Operation), an address (Address), and first test data (CheckA) from the memory controller 10, the command (Operation ) and address error detection. And, when an error is not detected, the semiconductor memory device 20 transmits first response information (ReplyA(OK)) indicating that no error is detected in the command (Operation) and the address (Address) to the memory controller 10 ) is sent to Also, the first response information (ReplyA(OK)) may be transmitted during a latency period from when a command and an address are input to when data is input or output.

In addition, the semiconductor memory device 20 asserts (high level) the signal wlon when errors are not detected in the command (Operation) and the address (Address). In this case, the signal wl for activating the word line corresponding to the address Address is asserted (high level).

Meanwhile, upon receiving the first response information (ReplyA(OK)), the memory controller 10 transmits the second check data CheckD and the write data Data to the semiconductor memory device 20 . Also, the second check data CheckD may be transmitted during latency.

When the semiconductor memory device 20 receives the second test data CheckD and the write data Data from the memory controller 10, the error detection of the write data Data is performed using the second test data CheckD. do In addition, the semiconductor memory device 20 asserts (high level) the signal cl for activating the bit line corresponding to the address Address. At this time, the sense amplifier 28 of the semiconductor memory device 20 activates the bit line corresponding to the address Address, so that the write data Data is written into the memory cell in the memory cell array 29 .

In addition, when the chip select signal /CE is negative (high level) after receiving the write data Data, the semiconductor memory device 20 provides response information indicating whether or not an error has been detected in the write data (second 3 response information (ReplyD(OK)) or fourth response information (ReplyD(NG)) is transmitted to the memory controller 10.

In addition, the semiconductor memory device 20 asserts (high level) the signal wloff when the write data Data is correctly written to the memory cell in the memory cell array 29 . By this, the signal wl is negative (low level).

In this way, when the memory controller 10 receives first response information (ReplyA(OK)) indicating that no errors are detected in the command (Operation) and the address (Address) from the semiconductor memory device 20, , it becomes possible to transmit the data (Data) written to the corresponding address (Address) to and from the semiconductor memory device (20).

Referring to Fig. 3, another example of the operation of the semiconductor memory device 20 in this embodiment will be described. Fig. 3 is a time chart showing the time transition of signals in the semiconductor memory device 20 when an error is included in either a command or an address. Meanwhile, as in FIG. 2 , a case in which a write command (Operation) is input from the memory controller 10 will be described as an example.

First, when the semiconductor memory device 20 receives a command (Operation), an address (Address), and first test data (CheckA) from the memory controller 10, the command (Operation ) and address error detection. And, when an error is detected, the semiconductor memory device 20 transmits second response information (ReplyA (NG)) indicating that an error is detected in any one of the command (Operation) and the address (Address) to the memory controller ( 10) is sent. Also, in this case, the semiconductor memory device 20 does not activate the word line and bit line corresponding to the address.

Meanwhile, upon receiving the second response information (ReplyA(NG)), the memory controller 10 retransmits the command (Operation), the address (Address), and the first check data (CheckA) to the semiconductor memory device 20. .

When the semiconductor memory device 20 receives the retransmitted command (Operation), the address (Address), and the first inspection data (CheckA) from the memory controller 10, the command (Operation) is performed using the first inspection data (CheckA). ) and address error detection. And, when an error is not detected, the semiconductor memory device 20 transmits first response information (ReplyA(OK)) indicating that no error is detected in the command (Operation) and the address (Address) to the memory controller 10 ) is sent to Incidentally, the operation of the semiconductor memory device 20 after this is the same as that of the example shown in FIG.

In this way, when an error is detected in the command (Operation) and the address (Address), the memory controller 10 retransmits the command (Operation) and the address (Address) to the semiconductor memory device 20, so that the semiconductor memory device 20 ) makes it possible to resume access from the beginning without starting an erroneous operation.

Referring to Fig. 4, another example of the operation of the semiconductor memory device 20 in this embodiment will be described. Fig. 4 is a time chart showing the time transition of signals in the semiconductor memory device when errors are included in the data. Incidentally, a case in which a write command (Operation) is input from the memory controller 10 will be described as an example, similarly to FIGS. 2 and 3 .

First, when the semiconductor memory device 20 receives a command (Operation), an address (Address), and first test data (CheckA) from the memory controller 10, the command (Operation ) and address error detection. In addition, the semiconductor memory device 20 asserts (high level) the signal (busy) when the chip select signal /CE changes from negative (high level) to assert (low level).

In addition, when the semiconductor memory device 20 receives the second check data CheckD and the write data Data after transmitting the first response information ReplyA(OK) to the memory controller 10, the second check Error detection of write data Data is performed using the data CheckD. In addition, the semiconductor memory device 20 writes the write data Data as described above.

Here, when an error is detected in the write data (Data), the semiconductor memory device 20, when the chip select signal /CE is negative (high level), fourth response information indicating that an error is detected in the write data ( ReplyD(NG)) is transmitted to the memory controller 10. Also, in this case, the semiconductor memory device 20 holds each of the signal wl and the signal busy in an asserted state.

Meanwhile, upon receiving the fourth response information (ReplyD(NG)), the memory controller 10 retransmits the second check data CheckD and the write data Data to the semiconductor memory device 20 .

When the semiconductor memory device 20 receives the second test data CheckD and the write data Data retransmitted from the memory controller 10, the error of the write data Data is generated by using the second check data CheckD. do the detection Also, the semiconductor memory device 20 writes the write data Data again. And, when an error is not detected in the write data Data, the semiconductor memory device 20 transmits third response information (ReplyD(OK)) indicating that no error is detected in the write data Data, to the memory controller 10 ) is sent to In addition, the semiconductor memory device 20 negates (low level) each of the signals wl and busy.

In this way, according to the memory system according to the present embodiment, it is possible to suppress a state in which an error is included in data to be read or written from being maintained.

Further, according to the memory system according to the present embodiment, even when an error is detected in the data Data, the semiconductor memory device 20 waits for the data Data to be retransmitted, thereby It becomes possible to continuously perform write-related access. In addition, the semiconductor memory device 20 maintains the signal wl in an asserted state while waiting for the retransmission of the data Data, thereby activating the sense amplifier when the command and address are retransmitted, for example. Since the waiting time (latency) is unnecessary, the operation time can be shortened.

Further, in the present embodiment, the case where only the data Data is retransmitted when an error is detected in the data Data has been described as an example, but the present invention is not limited to this case. For example, the command (Operation) may be retransmitted, the address (Address) corresponding to the row address signal (ra) and/or column address signal (ca) may be retransmitted, or the command (Operation) and the address (Address) may be retransmitted. It may be resent.

Also, according to the memory system according to the present embodiment, when an error is detected in the data Data, the memory controller 10 retransmits the data Data, so that the corresponding data Data can be written again. .

Referring to Fig. 5, another example of the operation of the semiconductor memory device 20 in this embodiment will be described. Fig. 5 is a time chart showing the time transition of signals in the semiconductor memory device when a predetermined time elapses while waiting for data retransmission. Incidentally, a case in which a write command (Operation) is input from the memory controller 10 will be described as an example similarly to FIGS. 2 to 4 .

First, when an error is detected in the write data (Data), the semiconductor memory device 20, if the chip select signal /CE is negative (high level), fourth response information indicating that an error is detected in the write data. (ReplyD(NG)) is sent to the memory controller 10. Incidentally, the operation of the semiconductor memory device 20 until an error is detected in the write data Data is the same as the example described with reference to FIG. 4 .

Here, the semiconductor memory device 20 transmits the second test data CheckD and writes until a predetermined time elapses after the fourth response information ReplyD(NG) is transmitted to the memory controller 10. When the data Data is not received from the memory controller 10, each of the signal wl and the signal busy may be negative (low level). As a result, the waiting state for retransmission of write data (Data) is canceled. In addition, the semiconductor memory device 20 may measure the elapsed time using a built-in timer circuit (not shown) or the like.

In this way, according to the memory system according to the present embodiment, the semiconductor memory device 20 cancels waiting for retransmission of the corresponding data Data when the data Data is not retransmitted, so that another read or It becomes possible to handle write access.

Next, with reference to FIG. 6, an example of the operation flow of the semiconductor memory device 20 will be described. In the semiconductor memory device 20, in the standby state (standby), when the chip select signal /CE is asserted (low level) and a command (Operation), address (Address), and first test data (CheckA) are input, , an error check of a command (Operation) and an address (Address) is performed using the first check data (CheckA) (step S100). Then, the semiconductor memory device 20 outputs the second response information (ReplyA(NG)) to the memory controller 10 when an error is detected (step S101: YES), and transits to a standby state. In addition, the semiconductor memory device 20 outputs the first response information (ReplyA (OK)) to the memory controller 10 when no error is detected (step S101: No), and enters an active state (active). fulfill

When the semiconductor memory device 20 transitions to an active state (active), the memory cell array 29 is activated (word lines and bit lines are activated) (step S102).

Next, the semiconductor memory device 20 performs read or write access based on the command (Operation) and the address (Address) (step S103). Here, in the case of write access, the semiconductor memory device 20 performs write access after receiving the second test data CheckD and write data Data.

In addition, the semiconductor memory device 20 performs an error check of the data Data using the second test data CheckD (step S104).

Here, when an error is detected in the data (Data) (step S105: Yes), the semiconductor memory device 20 outputs the fourth response information (ReplyD(NG)) to the memory controller 10, and the data (Data ) to wait for retransmission. Then, when the chip select signal /CE is asserted (low level), the semiconductor memory device 20 proceeds to the process of step S103. In addition, when the predetermined time has elapsed in the state of waiting for retransmission of the data (Data), the semiconductor memory device 20 proceeds to the processing of step S106 described later.

When an error is not detected in the data (Data) (step S105: No), the semiconductor memory device 20 outputs the third response information (ReplyD(OK)) to the memory controller 10, and the memory cell array ( 29) is deactivated (deactivation of word lines and bit lines) (step S106), and transitions to a standby state.

As described above, according to the memory system of this embodiment, the memory controller 10 transmits the first response information (ReplyA(OK)) indicating that no errors are detected in the command (Operation) and the address (Address) to the semiconductor When received from the memory device 20, it is possible to transmit or receive data (Data) to be read or written to the corresponding address with the semiconductor memory device 20. This makes it possible to suppress inappropriate access due to a change in the content or address of a command (Operation) during transmission of a command packet, so that appropriate access to the semiconductor memory device 20 is possible. can

Further, according to the memory system of this embodiment, appropriate access can be made to the pseudo-static random access memory.

(Second Embodiment)

Hereinafter, a second embodiment of the present invention will be described. The memory system of this embodiment differs from the first embodiment in that the semiconductor memory device 20 includes a plurality of banks accessed in an interleaved manner. Hereinafter, a configuration different from that of the first embodiment will be described.

An example of the operation of the semiconductor memory device 20 in this embodiment will be described with reference to FIGS. 7 and 8 . 7 and 8 are time charts showing the time transition of signals in the semiconductor memory device 20. In addition, the time charts shown in Fig. 7 (a) and Fig. 7 (b) show a continuous time transition from Fig. 7 (a) to Fig. 7 (b), and Figs. ) as well. In the example shown in the figure, a case in which the semiconductor memory device 20 includes two banks BNK0 and BNK1 will be described as an example.

As shown in Fig. 7, in the semiconductor memory device 20 in this embodiment, the command (Operation (BNK0)), address (Address (BNK0)) and first check data (CheckA) for one bank (BNK0) During the latency from when (BNK0) is input until data (Data (BNK0)) is input or output, access to the other bank (BNK1) is performed.

Similar to the first embodiment described above, when errors are not detected in the command (Operation (BNK0)) and the address (Address (BNK0)) for one bank (BNK0), the semiconductor memory device 20 outputs the address (Address Assert (high level) the word line (wl) (BNK0) corresponding to (BNK 0, row = Rm (Rm represents a row address, m is an integer))).

In addition, the semiconductor memory device 20 accesses the other bank BNK1 during the latency of access to one bank BNK0 (latency BNK0). Here, in the access to the other bank BNK1, the semiconductor memory device 20 receives the address received before the latency of the access to the other bank BNK1 (Address(BNK 1, row = Ri (Ri is the row Indicates an address, i is an integer))) and reads or writes data (Data(BNK1)) corresponding to it. Then, the semiconductor memory device 20, when no error is detected in the data (Data(BNK1)) (when ReplyD(BNK1) is “OK”), issues a command for the next access to the other bank (BNK1). (Operation (BNK1)) and an address (Address(BNK 1, row=Rj (Rj represents a row address, j is an integer)))) are received. At this time, the semiconductor memory device 20 asserts (high level) the word line wl (BNK1) corresponding to the address (Address(BNK1, row=Rj)).

Next, the semiconductor memory device 20 performs access to one bank BNK0 during the latency of access to the other bank BNK1 (latency BNK1). Here, in the access to one bank BNK0, the semiconductor memory device 20 stores data corresponding to the address (Address(BNK0, row=Rm)) received before latency of access to one bank BNK0 ( Data (BNK0)) is read or written. Then, the semiconductor memory device 20, when no error is detected in the data (Data(BNK0)) (when ReplyD(BNK0) is "OK"), issues a next access command for one bank (BNK0) ( Operation (BNK0)) and an address (Address(BNK 0, row=Rn (Rn represents a row address, n is an integer))) are received. At this time, the semiconductor memory device 20 asserts (high level) the word line wl (BNK0) corresponding to the address (Address(BNK0, row=Rn)).

8, when an error is detected in data (Data(BNK0)) in access to one bank (BNK0) (when ReplyD(BANK0) is “NG”), the semiconductor memory device ( 20), after receiving the data (Data(BNK0)) for which no error has been detected, until the next access command (Operation (BNK0)) and address (Address (BNK0, row=Rn)) are received, other The latency of access to the side bank BNK1 (latency BNK1) may be extended.

As described above, according to the memory system of this embodiment, access to a plurality of banks can be performed in parallel at the same time, so access to the semiconductor memory device 20 can be speeded up.

(Third Embodiment)

Hereinafter, a third embodiment of the present invention will be described. The memory system of this embodiment differs from the above embodiments in that the semiconductor memory device 20 is configured to internally generate a refresh request for executing memory cell refresh. Hereinafter, configurations different from those of each of the above embodiments will be described.

In this embodiment, the semiconductor memory device 20 receives commands, addresses, and data from the memory controller 10 between when the refresh request signal is generated and when the refresh is executed. ), any one of the command (Operation), address (Address) and data (Data) is retransmitted from the memory controller 10 so that the refresh process is performed until the error is not detected. It is configured to stop execution.

Referring to Fig. 9, an example of the operation of the semiconductor memory device 20 in this embodiment will be described. 9 is a time chart showing the time transition of signals in the semiconductor memory device 20. Incidentally, here, a case where a write command (Operation) is input from the memory controller 10 will be described as an example.

First, the semiconductor memory device 20 asserts (high level) the signal (busy) when the chip select signal /CE changes from negative (high level) to assert (low level). Here, when the semiconductor memory device 20 internally generates (asserts) the refresh request signal refreq while receiving the command (Operation), the address (Address), and the first test data (CheckA), , asserts (high level) the signal (refwait) for waiting for execution of refresh. Also, the refresh request signal refreq and the signal refwait may be generated by the command control unit 22 of the semiconductor memory device 20, for example.

And, when an error is detected in the command (Operation) and the address (Address), the semiconductor memory device 20 sends second response information (ReplyA(NG)) indicating that an error has been detected to the memory controller 10. transmit

Next, the semiconductor memory device 20 receives the write data Data from the memory controller 10 when errors are not detected in the command Operation and Address retransmitted from the memory controller 10. and writing of the received write data (Data) is performed.

Then, the semiconductor memory device 20 sends a signal refwait when an error is not detected in the write data Data (when the third response information ReplyD(OK) is transmitted to the memory controller 10). Negates (levels to low). In addition, the semiconductor memory device 20 executes refresh when the signal refwait is negative (low level). Specifically, the semiconductor memory device 20 asserts (high level) the signal wlon and simultaneously asserts (high level) the signal wlon in order to activate the word line to be refreshed. . In addition, the semiconductor memory device 20 asserts (high level) the signal bl for activating the bit line in order to perform refresh. Then, the semiconductor memory device 20 performs refresh. Also, when the refresh is complete, the semiconductor memory device 20 asserts the signal wloff (high level) and negates the signal wl (low level).

Incidentally, although description is omitted in the drawings, the semiconductor memory device 20, when an error is detected in the data Data, continues until the error is no longer detected in the data Data transmitted from the memory controller 10. Execution of refresh may be waited (signal (refwait) asserted (high level)).

In this way, according to the present embodiment, the execution of refresh is stopped until an error is not detected in any of the command (Operation), address (Address), and data (Data), which is due to the fact that the refresh is executed. It becomes possible to suppress the delay of access.

Further, as a modification of the third embodiment, the semiconductor memory device 20 receives a command (Operation) received from the memory controller 10 between the generation of the refresh request signal (refreq) and the execution of refresh, It may be configured so that when an error is detected in either of the address (Address) and the data (Data), the fifth response information indicating that the refresh is executed is transmitted to the memory controller 10, and the refresh is executed.

Referring to Fig. 10, an example of the operation of the semiconductor memory device 20 in a modified example will be described. 10 is a time chart showing the time transition of signals in the semiconductor memory device 20. Incidentally, here, a case where a write command (Operation) is input from the memory controller 10 will be described as an example.

First, the semiconductor memory device 20 asserts (high level) the signal (busy) when the chip select signal /CE changes from negative (high level) to assert (low level). Here, when the semiconductor memory device 20 internally generates (asserts) the refresh request signal refreq while receiving the command (Operation), the address (Address), and the first test data (CheckA), Assert (high level) the signal (refwait) for waiting for execution of refresh.

And, when an error is detected in the command (Operation) and the address (Address), the semiconductor memory device 20 sends second response information (ReplyA(NG)) indicating that an error has been detected to the memory controller 10. transmit Here, the second response information (ReplyA(NG)) may include fifth response information (indicated as "Ref next" in the figure) indicating that refresh is executed.

On the other hand, when the memory controller 10 receives the second response information (ReplyA(NG)) including the fifth response information ("Ref next"), refresh is executed in the semiconductor memory device 20, In view of this, transmission of the command (Operation), address (Address), and first check data (CheckA) in the next access may be waited until a predetermined time elapses.

Next, the semiconductor memory device 20 negates (low level) the signal (busy) once, and then asserts (high level) thereafter. In addition, the semiconductor memory device 20 starts execution of refresh according to the signal busy becoming negative (low level), and negating the signal refwait (low level).

Then, the semiconductor memory device 20 performs processing in the next access after the execution of refresh is finished.

In this way, according to this modified example, refresh is executed when an error is detected in any one of the command (Operation), address (Address), and data (Data), for example, the command (Operation), address It is possible to suppress information stored in the semiconductor memory device 20 from being lost due to the fact that refresh is not executed while retransmission of any of (Address) and data (Data) is repeatedly performed.

Each embodiment described above is described for facilitating understanding of the present invention, and is not described for limiting the present invention. Therefore, each element disclosed in each of the above embodiments is intended to include all design changes and equivalents belonging to the technical scope of the present invention.

For example, in the above embodiment, the case where the semiconductor memory device 20 is a pSRAM has been described as an example, but the present invention is not limited to this case. For example, the semiconductor memory device 20 may be a DRAM, a flash memory, or another semiconductor memory device.

In the above embodiment, the case where the memory controller 10 transmits the write command (Operation (Write)) to the semiconductor memory device 20 has been described as an example, but the memory controller 10 transmits the read command (Operation) Also in the case of transmitting to the semiconductor memory device 20, the same effect as in the above-described embodiment is obtained.

For example, the semiconductor memory device 20 (one of the memory controller 10 and the semiconductor memory device 20) transmits read data and second check data CheckD for error detection of the read data to the memory controller ( 10) (the other of the memory controller 10 and the semiconductor memory device 20). Further, when the read data and the second check data CheckD are received, the memory controller 10 performs error detection of the read data using the second check data CheckD, and an error is detected in the read data. If not, third response information (ReplyD(OK)) indicating that no error is detected in the read data may be transmitted to the semiconductor memory device 20. In this case, the semiconductor memory device 20 can confirm that the data to be written has properly reached the memory controller 10 by receiving the third response information (ReplyD(OK)).

Further, in the above case, the memory controller 10 (the other of the memory controller 10 and the semiconductor memory device 20), when an error is detected in the data, gives an indication that an error is detected in the data. 4 Response information (ReplyD(NG)) is transmitted to the semiconductor memory device 20 (either the memory controller 10 or the semiconductor memory device 20), and data is retransmitted from the semiconductor memory device 20 for a predetermined time. You may wait until this elapses. In this case, even if an error is detected in the data, it becomes possible for the memory controller 10 to continuously access the data read by waiting for the data to be resent. This makes it possible to increase the access efficiency compared to, for example, the case where access related to reading this data is restarted from the beginning (when the command and address are retransmitted).

Further, in the above case, the semiconductor memory device 20 (one of the memory controller 10 and the semiconductor memory device 20) receives the fourth response information (ReplyD(NG)), and the data and , data may be retransmitted to the memory controller 10 (the other of the memory controller 10 and the semiconductor memory device 20). In this way, when an error is detected in the data, the semiconductor memory device 20 retransmits the data, so that the data can be read again.

Further, in the above case, the memory controller 10 (the other of the memory controller 10 and the semiconductor memory device 20) continues to operate until a predetermined time elapses until the semiconductor memory device 20 (the memory controller 10 ) and the semiconductor memory device 20), waiting for data retransmission may be canceled when data is not retransmitted. In this case, the memory controller 10 cancels waiting for retransmission of the data when the data is not retransmitted, so that it becomes possible to process another read or write access. In this way, the processing efficiency of access can be improved.

In the above embodiment, the case where the first check data CheckA is transmitted in a state divided into a command (Operation) and an address (Address) has been described as an example, but the present invention is not limited to this case. Fig. 11 shows an example of bit allocation of commands (Operation) and addresses (Address). In addition, here, the case where the semiconductor memory device 20 is a pSRAM is assumed.

In the example shown in Fig. 11, 8-bit address data signals ADQ[7] to ADQ[0] are input at every rising edge and falling edge of the external clock signal CLK. Here, a command (Operation) is configured in the address data signals (ADQ[7] to ADQ[5]) input at the rising edge of the first external clock signal (CLK), and the first external clock signal (CLK ), addresses (Address[31] to Address[0]) are configured in the address data signal ADQ input in the third external clock signal CLK. Further, the address data signals ADQ[7] to ADQ[0] input at the third rising edge of the external clock signal CLK and the input at the third falling edge of the external clock signal CLK Although the address data signals ADQ[7] to ADQ[3] are reserved areas, they are unused areas. Therefore, the first inspection data CheckA may be configured using at least a part of this reserved area. This makes it possible for the semiconductor memory device 20 to receive the first test data CheckA simultaneously with the address. Also, the first check data CheckA may be configured in the address data signal ADQ input at the rising edge or falling edge of the fourth or subsequent external clock signal CLK.

In the example shown in Fig. 11, the data strobe signal RWDS may be configured to display fifth response information indicating that refresh is being executed. For example, when the data strobe signal RWDS is at a high level (H), fifth response information ("Ref next") indicating that refresh is being executed may be displayed. On the other hand, when the data strobe signal RWDS has a low level (L), a signal indicating that the address data signal ADQ can be immediately transmitted and received ("Immediate") may be displayed.

As shown in Fig. 12, the data strobe signal RWDS may be configured to display either the first response information (ReplyA(OK)) or the second response information (ReplyA(NG)). For example, when the logic level (high level or low level) of the data strobe signal RWDS is maintained ("kept") at the fourth rising edge of the external clock signal CLK, the data strobe signal RWDS ) may indicate the first response information (ReplyA(OK)). On the other hand, when the logic level (high level or low level) of the data strobe signal RWDS is inverted (“inverted”) at the fourth rising edge of the external clock signal CLK, the data strobe signal RWDS is The second response information (ReplyA(NG)) may be displayed. Further, for example, according to the state of the data strobe signal RWDS at the rising edge or falling edge of the external clock signal CLK after the fifth, the first response information (ReplyA(OK)) or the second response Information (ReplyA(NG)) may be displayed.

Note that the configurations of the memory controller 10 and the semiconductor memory device 20 shown in Fig. 1 are examples, and may be appropriately changed or various other configurations may be employed.

10: memory controller 11: request controller
12: sequence control
12a: Serializer/Deserializer (SerDes)
12b: error control unit 20: semiconductor memory device
21: sequence control
21a: Serializer/Deserializer (SerDes)
2lb: error control unit 22: command control unit
23: address control unit 24: word line control unit
25: column control unit 26: data control unit
27: data bus controller 28: sense amplifier
29: memory cell array

Claims (15)

As a memory system,
memory controller; and
semiconductor memory
Including, the memory controller,
sending a command and an address and first test data for error detection of the command and the address to the semiconductor memory device;
When first response information indicating that no errors are detected in the command and the address is received from the semiconductor memory device, data read from or written to the address based on the command is transferred between the semiconductor memory device and the semiconductor memory device. to send or receive from
is configured to do
The semiconductor memory device,
When the command, the address, and the first check data are received from the memory controller, errors are detected in the command and the address using the first check data, and errors are detected in the command and the address. sending the first response information to the memory controller if not;
Transmitting or receiving data to be read from or written to the address based on the command to or from the memory controller when errors are not detected in the command or the address.
A memory system configured to perform According to claim 1,
The semiconductor memory device,
When an error is detected in either of the command and the address, send second response information indicating that an error is detected in one of the command and the address to the memory controller;
The memory controller,
and retransmit the command and the address to the semiconductor memory device when the second response information is received from the semiconductor memory device. According to claim 1,
One of the memory controller and the semiconductor memory device,
configured to transmit the data to be read or written and second test data for error detection of the data to the other of the memory controller and the semiconductor memory device;
The other of the memory controller and the semiconductor memory device,
When the data and the second inspection data are received, error detection of the data is performed using the second inspection data, and when no error is detected in the data, an error is not detected in the data. and transmit third response information indicating that the memory system is configured to transmit to one of the memory controller and the semiconductor memory device. According to claim 3,
The other of the memory controller and the semiconductor memory device,
When an error is detected in the data, sending fourth response information indicating that an error is detected in the data to one of the memory controller and the semiconductor memory device;
Waiting for the data to be retransmitted from one of the memory controller and the semiconductor memory device until a predetermined time elapses
A memory system configured to perform According to claim 4,
One of the memory controller and the semiconductor memory device,
and resends the data and the second test data corresponding to the data to the other of the memory controller and the semiconductor memory device when receiving the fourth response information. According to claim 4,
The other of the memory controller and the semiconductor memory device,
and cancel waiting for retransmission of the data when the data is not retransmitted from one of the memory controller and the semiconductor memory device until the predetermined time elapses. According to any one of claims 1 to 6,
The memory system according to claim 1 , wherein the semiconductor memory device has a plurality of banks accessed in an interleaved manner. According to any one of claims 1 to 6,
When the semiconductor memory device is configured to internally generate a refresh request signal for executing refresh, the command received from the memory controller between when the refresh request signal is generated and when the refresh is executed , when an error is detected in any of the address and the data, the execution of the refresh until the error is not detected by retransmitting any of the command, the address, and the data from the memory controller A memory system configured to stop the According to any one of claims 1 to 6,
When the semiconductor memory device is configured to internally generate a refresh request signal for executing refresh, the command received from the memory controller between when the refresh request signal is generated and when the refresh is executed , when an error is detected in any of the address and the data, send fifth response information indicating that the refresh is executed to the memory controller, and execute the refresh. The memory system according to any one of claims 1 to 6, wherein the semiconductor memory device is a pseudo-static random access memory. According to any one of claims 1 to 6,
The memory controller,
a request control unit configured to generate a conversion signal for converting a transmission method of an address data signal transmitted and received between the memory controller and the semiconductor memory device when a write or read request for the semiconductor memory device is received from a host device;
a first sequence controller for converting the transmission method of the address data signal based on the conversion signal;
And the first sequence control unit,
a first serializer/serializer (SerDes) for serializing or serializing the address data signal based on the conversion signal;
A first error controller generating the first inspection data using the command and the address
And the first SerDes,
generating and outputting a write command and an address to the first error control unit when the request control unit receives a write request and the conversion signal is input from the request control unit;
when the first test data corresponding to the generated write command and address is input from the first error control unit, transmitting the generated write command and address and the first test data as the address data signals to the semiconductor memory device; ,
When first response information indicating that no error has been detected in the generated write command and address is received as the address data signal from the semiconductor memory device, the write data received from the host device is output to the first error control unit. to do
A memory system configured to perform According to claim 11,
The first error control unit is configured to generate second inspection data for error detection of the write data using the write data;
wherein the SerDes is configured to transmit the second test data and the write data as the address data signals to the semiconductor memory device when the second test data is input from the first error control unit. According to claim 11,
The first error control section, when receiving second response information indicating that an error has been detected in either of the write command and address as the address data signal from the semiconductor memory device, receives the write command and address and the second response information. 1 configured to generate a signal for retransmitting test data;
When the first SerDes receives the second response information as the address data signal from the semiconductor memory device, the write command and a signal for retransmitting the address and the first test data are sent from the first error control unit. and resends the write command and address and the first test data as the address data signals to the semiconductor memory device when inputted. According to claim 11,
The semiconductor memory device includes a second sequence controller that converts a transmission method of the address data signal transmitted and received with the memory controller;
The second sequence control unit,
A second serializer/serializer (SerDes) for serializing or serializing the address data signal;
A second error controller configured to detect errors in the command and the address using the first test data received from the memory controller
And the second SerDes,
When the command, the address, and the first check data are received as the address data signals from the memory controller, the command, the address, and the first check data are serially transmitted and converted to the second error control unit. output and
When the first response information is input from the second error control unit, the first response information is converted into a parallel transmission method, and the first response information is output as the address data signal to a memory controller, and the command outputting a signal representing the content to a command control unit that generates an internal command based on the command, and outputting a signal representing the address to an address control unit that controls to activate a word line and a bit line corresponding to the address; ,
When the second response information is input from the second error control unit, converting the second response information in a parallel transmission method and transmitting the second response information as the address data signal to the memory controller.
A memory system configured to perform According to claim 14,
the second error control unit is configured to perform error detection of the write data using second check data for error detection of the write data;
The second SerDes,
outputting the write data and the second check data to the second error controller when receiving the write data and second check data for error detection of the write data as address data signals from the memory controller;
When fourth response information indicating that an error is detected in the write data is input from the second error control unit, transmitting the fourth response information as the address data signal to the memory controller.
A memory system configured to perform