TWI806532B - Circuit board structure - Google Patents

Circuit board structure Download PDF

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TWI806532B
TWI806532B TW111112687A TW111112687A TWI806532B TW I806532 B TWI806532 B TW I806532B TW 111112687 A TW111112687 A TW 111112687A TW 111112687 A TW111112687 A TW 111112687A TW I806532 B TWI806532 B TW I806532B
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metal
metal base
circuit board
hole
board structure
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TW202341828A (en
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林鈺銘
劉弘晟
李承宇
謝清順
藍國興
林品仲
何政恩
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景碩科技股份有限公司
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Abstract

A circuit board structure includes a dielectric board body and a metal via-filling structure. The dielectric board body is provided with a via, and a metal base is at the bottom of the via. The metal via-hole filling structure is on the metal base and fills the via, wherein an average misorientation angle between the surface of the metal base and the bottom of the metal via-filling structure is less than seven degrees. By controlling the average misorientation angle between the surface of the metal base and the bottom of the metal via-filling structure to be less than seven degrees, the crystal coherency between crystals can be increased, and the overall mechanical properties and electrical properties can be improved.

Description

電路板結構circuit board structure

本發明涉及電鍍領域,尤其是一種電路板結構。 The invention relates to the field of electroplating, in particular to a circuit board structure.

隨著微電子元件細微化需要依賴高密度互聯(high density interconnection,HDI)技術,使用細線路(fine line)和大量堆疊盲孔(stacked-via)結構互連在不同封裝級別的印刷電路板(printed circuit boards,PCBs)上。 With the miniaturization of microelectronic components, it is necessary to rely on high density interconnection (HDI) technology, using fine lines and a large number of stacked-via structures to interconnect printed circuit boards at different packaging levels ( printed circuit boards, PCBs).

PCB在盲孔中的電鍍填料,常因不同溫度的變化,如基板材料的熱脹冷縮、佈線金屬和介電材料之間熱膨脹係數(coefficient of thermal expansion,CTE)差異過大而產生明顯的材料熱應力,終致基板產生翹曲(warpage),甚而使盲孔發生斷裂。 The electroplating filler of PCB in the blind hole is often due to the change of different temperatures, such as the thermal expansion and contraction of the substrate material, the excessive difference in the coefficient of thermal expansion (CTE) between the wiring metal and the dielectric material, resulting in obvious material The thermal stress eventually causes warpage of the substrate, and even breaks the blind via.

經過檢驗,能理解的是,當填孔材料與底部的佈線金屬之間的晶格缺陷增加,也就是晶格不匹配程度明顯增加時,可以觀察到機械可靠度下降、同時電阻大幅提升的問題。 After inspection, it can be understood that when the lattice defects between the hole-filling material and the wiring metal at the bottom increase, that is, when the degree of lattice mismatch increases significantly, the problem of a decrease in mechanical reliability and a significant increase in resistance can be observed .

為了解決先前技術所面臨的問題,在此提供一種電路板結構。電路板結構包含介電板件本體及金屬填孔結構。介電板件本體開設有盲孔,盲孔的底部包含金屬底座。金屬填孔結構位於金屬底座之上,且填滿盲孔,其中金屬底座的表面與金屬填孔結構的底部之間的平均晶 粒取向差角(misorientation angle)小於七度。 In order to solve the problems faced by the prior art, a circuit board structure is provided here. The circuit board structure includes a dielectric board body and a metal filling hole structure. The body of the dielectric board is provided with a blind hole, and the bottom of the blind hole contains a metal base. The metal-filled hole structure is located on the metal base and fills the blind hole, wherein the average grain size between the surface of the metal base and the bottom of the metal-filled hole structure The grain misorientation angle is less than seven degrees.

在一些實施例中,金屬底座及金屬填孔結構的材質係選自由銅、錫、銀、金、鋅、鐵、鈷、以及鎳所構成之群組。 In some embodiments, the material of the metal base and the metal filling structure is selected from the group consisting of copper, tin, silver, gold, zinc, iron, cobalt, and nickel.

更詳細地,在一些實施例中,金屬底座為壓合銅層或電鍍銅層,金屬填孔結構為電鍍銅層。 In more detail, in some embodiments, the metal base is a laminated copper layer or an electroplated copper layer, and the metal hole filling structure is an electroplated copper layer.

進一步地,在一些實施例中,在盲孔的孔壁與金屬填孔結構之間,以及金屬底座與金屬填孔結構之間,更包含化學銅層,其中化學銅層的厚度小於1μm。 Further, in some embodiments, an electroless copper layer is further included between the wall of the blind hole and the metal-filled via structure, and between the metal base and the metal-filled via structure, wherein the thickness of the electroless copper layer is less than 1 μm.

更詳細地,在一些實施例中,金屬底座的厚度為5至20μm,金屬填孔結構的厚度為20至35μm。 In more detail, in some embodiments, the metal base has a thickness of 5 to 20 μm, and the metal hole-filling structure has a thickness of 20 to 35 μm.

在一些實施例中,金屬底座的表面與金屬填孔結構的底部之間的平均晶粒取向差角的範圍是1至5.5度。更詳細地,在一些實施例中,金屬底座表面與金屬填孔結構底部之間的平均晶粒取向差角的範圍是2至5度。 In some embodiments, the average grain misorientation angle between the surface of the metal pedestal and the bottom of the metal-filled via structure ranges from 1 to 5.5 degrees. In more detail, in some embodiments, the average grain misorientation angle between the surface of the metal base and the bottom of the metal-filled via structure ranges from 2 to 5 degrees.

在一些實施例中,金屬填孔結構進行電鍍的沉積速率約小於0.22μm/min。更詳細地,在一些實施例中,金屬填孔結構進行電鍍的沉積速率約為0.044μm/min至0.176μm/min。 In some embodiments, the metal-filled via structure is electroplated at a deposition rate of less than about 0.22 μm/min. In more detail, in some embodiments, the metal-filled hole structure is plated at a deposition rate of about 0.044 μm/min to 0.176 μm/min.

如同前述實施例所述,透過控制金屬底座的表面與金屬填孔結構的底部之間的平均晶粒取向差角小於七度,能使得晶體間的晶體延續性增加,可增進整體的機械特性及電性,同時維持製程的速率,以及量產的規模。 As described in the foregoing embodiments, by controlling the average grain misorientation angle between the surface of the metal base and the bottom of the metal-filled hole structure to be less than seven degrees, the continuity of crystals between crystals can be increased, and the overall mechanical properties and Electrical properties, while maintaining the speed of the process and the scale of mass production.

1:電路板結構 1: Circuit board structure

10:介電板件本體 10: Dielectric plate body

20:盲孔 20: blind hole

30:金屬底座 30: metal base

40:金屬填孔結構 40: Metal hole filling structure

45:化學銅層 45: chemical copper layer

圖1係電路板結構的剖面示意圖。 Figure 1 is a schematic cross-sectional view of a circuit board structure.

圖2係圖1中盲孔位置的A部分局部放大圖。 Fig. 2 is a partially enlarged view of part A of the position of the blind hole in Fig. 1 .

圖3係圖2中盲孔位置的B部分細部放大圖。 Fig. 3 is a detailed enlarged view of part B of the position of the blind hole in Fig. 2 .

圖4為聚焦離子束(focus ion beam,FIB)之橫截面影像與金屬填孔結構40及金屬底座30之電子背向散射繞射系統(electron backscatter diffraction,EBSD)晶體取向圖之疊圖。 4 is a superimposed view of a cross-sectional image of a focused ion beam (FIB) and an electron backscatter diffraction (EBSD) crystal orientation map of the metal hole-filling structure 40 and the metal base 30 .

圖5為對應於圖4之EBSD之影像清晰度分析(image quality,IQ)影像與電鍍銅和底材銅之間的晶界分析疊圖。 FIG. 5 is an image quality (IQ) image of EBSD corresponding to FIG. 4 and an overlay of grain boundary analysis between electroplated copper and substrate copper.

圖6為盲孔結構在快速盲孔拉力(quick via pulling test,QVP test)測試後的拉力曲線。 FIG. 6 is a pulling force curve of the blind hole structure after a quick via pulling test (quick via pulling test, QVP test).

圖1係電路板結構的剖面示意圖。圖2係圖1中A部分盲孔位置的局部放大圖。如圖1及圖2所示,電路板結構1可以為多層堆疊的結構,其中可以包含多個介電板件本體10,介電板件本體10上可以開設有一個或多個盲孔20,各盲孔20的底部包含金屬底座30。另外,電路板結構1還具有金屬填孔結構40。金屬填孔結構40位於金屬底座30之上,且填滿盲孔20。在此,金屬填孔結構40及金屬底座30,可以是銅、錫、銀、金、鋅、鐵、鈷、以及鎳等高導電率的金屬,較常用為銅。 Figure 1 is a schematic cross-sectional view of a circuit board structure. Fig. 2 is a partial enlarged view of the position of the blind hole in part A in Fig. 1 . As shown in Figures 1 and 2, the circuit board structure 1 may be a multi-layer stacked structure, which may include a plurality of dielectric board bodies 10, and one or more blind holes 20 may be opened on the dielectric board body 10, The bottom of each blind hole 20 includes a metal base 30 . In addition, the circuit board structure 1 also has a metal filling hole structure 40 . The metal filling structure 40 is located on the metal base 30 and fills the blind hole 20 . Here, the metal filling structure 40 and the metal base 30 can be copper, tin, silver, gold, zinc, iron, cobalt, and nickel and other high-conductivity metals, and copper is more commonly used.

在此,金屬底座30可以是電鍍銅層,或是壓合銅層,也就是,介電板件本體10可以設置在完成電鍍的介電板件本體10上,透過鑽孔方式,於前次預留的電鍍銅層位置上形成盲孔20,或者透過壓合的方 式壓合在銅箔上,進行鑽孔而形成盲孔20。 Here, the metal base 30 can be an electroplated copper layer, or a laminated copper layer, that is, the dielectric plate body 10 can be arranged on the electroplated dielectric plate body 10, through drilling, in the previous A blind hole 20 is formed on the reserved position of the electroplated copper layer, or through a pressing method The blind hole 20 is formed by pressing and bonding on the copper foil.

圖3係圖2中B部分盲孔位置的細部放大圖。其中,圖中虛線表示金屬填孔結構40和金屬底座30之間的交界在實驗中,先採用電子背向散射繞射系統(electron backscatter diffraction,EBSD)解析銅晶體微結構,如圖3所示,可以看出金屬底座30與金屬填孔結構40上分別具有複數個晶粒。再透過TSL-OIM軟體選擇晶格邊界的上方、下方之晶粒,量測其取向差角(misorientation angle,θ)。量測時是採取50μm的局部範圍,沿著盲孔20的底部,也就是金屬底座30與金屬填孔結構40間的晶格邊界以5μm的間距依序平移量測邊界上下晶粒之取向差角。再以10組的數據平均,而獲得平均晶粒取向差角。 Fig. 3 is a detailed enlarged view of the position of the blind hole in part B in Fig. 2 . Among them, the dotted line in the figure indicates the junction between the metal hole-filling structure 40 and the metal base 30. In the experiment, the electron backscatter diffraction system (electron backscatter diffraction, EBSD) was first used to analyze the copper crystal microstructure, as shown in FIG. 3 , it can be seen that the metal base 30 and the metal filling structure 40 respectively have a plurality of crystal grains. Then use the TSL-OIM software to select the crystal grains above and below the lattice boundary, and measure the misorientation angle (θ). During the measurement, a local range of 50 μm is taken, along the bottom of the blind hole 20, that is, the lattice boundary between the metal base 30 and the metal-filled hole structure 40, and the orientation difference of the crystal grains above and below the boundary is measured sequentially at a distance of 5 μm. horn. Then average the data of 10 groups to obtain the average grain misorientation angle.

依據晶粒取向差角效應(misorientation angle effect),可以理解晶粒取向差角與電阻率成正比,同時,電阻率可以依據下方的方程式(1),即(Mayadas-Shatzkes model)進行計算。在本案所欲控制的結構中,考量機械性質、電性及製程速度,平均晶粒取向差角小於七度。較佳地,平均晶粒取向差角的範圍是1至5.5度,進一步地,平均晶粒取向差角的範圍是2至5度。 According to the misorientation angle effect, it can be understood that the grain misorientation angle is proportional to the resistivity, and the resistivity can be calculated according to the following equation (1), ie (Mayadas-Shatzkes model). In the structure to be controlled in this case, considering mechanical properties, electrical properties and process speed, the average grain misorientation angle is less than seven degrees. Preferably, the average grain misorientation angle ranges from 1 to 5.5 degrees, further, the average grain misorientation angle ranges from 2 to 5 degrees.

Figure 111112687-A0305-02-0006-1
Figure 111112687-A0305-02-0006-1

其中ρgb為晶界電阻率(grain boundary resistivity)(μΩ cm),ρb為塊體的電阻率(bulk resistivity)(μΩ cm),r是晶界反射系數(grain boundary reflection coefficient),λ是電子平均自由徑(mean free path)(nm),D是晶粒尺寸(grain size)(μm)。 where ρ gb is the grain boundary resistivity (μΩ cm), ρ b is the bulk resistivity (μΩ cm), r is the grain boundary reflection coefficient (grain boundary reflection coefficient), λ is Electron mean free path (nm), D is the grain size (grain size) (μm).

再次參照圖2,在此盲孔20為一梯形,其底部寬度為50μm,上部寬度為60μm,深度為27μm。然而,這僅為示例,而非限於此,若是盲孔20底部寬度較寬,在進行晶粒取向差角的量測時,可以增加取樣的點數,來增加平均值的可信度。 Referring again to FIG. 2 , the blind hole 20 is trapezoidal, with a bottom width of 50 μm, an upper width of 60 μm, and a depth of 27 μm. However, this is only an example and not limited thereto. If the width of the bottom of the blind hole 20 is wider, the number of sampling points can be increased to increase the reliability of the average value when measuring the grain misorientation angle.

為了在電鍍前增加附著性,可以在電鍍形成金屬填孔結構40之前,先以浸潤、無電鍍的方式形成化學銅層45,換言之,在完成電鍍後,化學銅層45位於盲孔20的孔壁與金屬填孔結構40之間,以及金屬底座30與金屬填孔結構40之間,且化學銅層45的厚度小於1μm,較佳地,厚度在0.5μm至0.8μm的範圍,例如0.7μm。另外,金屬底座30的厚度為5至20μm,金屬填孔結構40的厚度為20至35μm,例如,26μm。 In order to increase the adhesion before electroplating, the electroless copper layer 45 can be formed by wetting and electroless plating before electroplating to form the metal filling hole structure 40. In other words, after the electroplating is completed, the electroless copper layer 45 is located in the hole of the blind hole 20 Between the wall and the metal filling structure 40, and between the metal base 30 and the metal filling structure 40, the thickness of the chemical copper layer 45 is less than 1 μm, preferably, the thickness is in the range of 0.5 μm to 0.8 μm, such as 0.7 μm . In addition, the metal base 30 has a thickness of 5 to 20 μm, and the metal filling structure 40 has a thickness of 20 to 35 μm, for example, 26 μm.

更詳細地,由於化學銅層45的厚度較薄,在電鍍前之酸洗時,化學銅層45部分會被蝕刻而部分去除,因此量測時化學銅層45的厚度可以忽視,平均晶粒取向差角的量測可以看作金屬底座30及金屬填孔結構40之間的平均晶粒取向差角。 In more detail, because the thickness of the chemical copper layer 45 is relatively thin, during the pickling before electroplating, the chemical copper layer 45 part will be etched and partially removed, so the thickness of the chemical copper layer 45 can be ignored during measurement, and the average crystal grain The measurement of the misorientation angle can be regarded as the average grain misorientation angle between the metal base 30 and the metal-filled via structure 40 .

晶粒取向差角(misorientation angle)經實驗發現可以透過控制電鍍的沉積速率,來進行控制,經發現沉積速率下降時,可以獲得較低的平均晶粒取向差角,而達到較佳的電性及機械性質。然而,會有降低產量及製程速度的副作用。考量兩者,選擇沉積速率小於0.22μm/min,較佳地,通常控制沉積速率0.044至0.176μm/min。作為參考值,一般業界採用的沉積速率為0.22至0.44μm/min。 The misorientation angle can be controlled by controlling the deposition rate of electroplating through experiments. It is found that when the deposition rate decreases, a lower average misorientation angle can be obtained to achieve better electrical properties. and mechanical properties. However, there is a side effect of reducing yield and process speed. Considering both, the deposition rate is selected to be less than 0.22 μm/min, preferably, the deposition rate is generally controlled to be 0.044 to 0.176 μm/min. As a reference value, the deposition rate generally used in the industry is 0.22 to 0.44 μm/min.

以下將詳述實驗的方法,以下採用雙層介電板件本體10,對上層盲孔20中的金屬底座30及金屬填孔結構40進行各項的量測,在 此,金屬底座30為壓合銅,盲孔20底部寬度為50μm,上部寬度為60μm,深度為27μm。金屬底座30的厚度約為20μm,金屬填孔結構40的厚度約為26μm。依據前述的進行平均晶粒取向差角的量測、電阻的量測,以及拉力測試。 The method of the experiment will be described in detail below. The following uses the double-layer dielectric board body 10 to carry out various measurements on the metal base 30 and the metal filling structure 40 in the upper blind hole 20. Here, the metal base 30 is pressed copper, the width of the bottom of the blind hole 20 is 50 μm, the width of the upper part is 60 μm, and the depth is 27 μm. The thickness of the metal base 30 is about 20 μm, and the thickness of the metal filling structure 40 is about 26 μm. The measurement of the average grain misorientation angle, the measurement of the electrical resistance, and the tensile test were carried out according to the foregoing.

以下透過不同的實施例,其中比較例是以沉積速率0.44μm/min進行電鍍金屬填孔結構40,而實驗示例1是以沉積速率0.22μm/min進行電鍍金屬填孔結構40、實驗示例2是以沉積速率0.11μm/min進行電鍍金屬填孔結構40、實驗示例3是以沉積速率0.066μm/min進行電鍍金屬填孔結構40。所獲得的實驗結果如表1所示。 The following is through different examples, wherein the comparative example is to electroplate the metal filling structure 40 at a deposition rate of 0.44 μm/min, and the experimental example 1 is to electroplate the metal filling structure 40 at a deposition rate of 0.22 μm/min, and the experimental example 2 is The metal-filled hole structure 40 was electroplated at a deposition rate of 0.11 μm/min. In Experimental Example 3, the metal-filled hole structure 40 was electroplated at a deposition rate of 0.066 μm/min. The experimental results obtained are shown in Table 1.

Figure 111112687-A0305-02-0008-2
Figure 111112687-A0305-02-0008-2

其中,實際實驗上,以聚焦離子束(focus ion beam,FIB)之橫截面影像與金屬填孔結構40及金屬底座30之EBSD晶體取向圖之疊圖、EBSD之影像清晰度分析IQ影像與電鍍銅和底材銅之間的晶界分析疊圖、以及盲孔結構在快速盲孔拉力(quick via pulling test,QVP test)測試後的拉力曲線,請參見圖4至圖6。其中圖4中的虛線表示金屬 填孔結構40及金屬底座30之間的交界,圖5乃對應於圖4。圖6為(25×24BHs)。 Among them, in the actual experiment, the cross-sectional image of the focused ion beam (FIB) and the EBSD crystal orientation map of the metal filling structure 40 and the metal base 30 are superimposed, and the image definition of the EBSD is used to analyze the IQ image and the electroplating Please refer to Figure 4 to Figure 6 for the grain boundary analysis stack between copper and substrate copper, and the pulling force curve of the blind via structure after the quick via pulling test (QVP test). where the dotted line in Figure 4 represents the metal The interface between the filling structure 40 and the metal base 30 , FIG. 5 corresponds to FIG. 4 . Figure 6 is (25×24BHs).

由上述實驗的結果比較,綜觀平均晶粒取向差角的量測、電阻的量測的結果,以及拉力測試的結果、製程的產量、製程速率,選擇較低的沉積速率、以控制金屬底座的表面與金屬填孔結構的底部之間的平均晶粒取向差角小於七度。 By comparing the results of the above experiments, taking a comprehensive look at the results of the measurement of the average grain misorientation angle, the measurement of the resistance, and the results of the tensile test, the output of the process, and the process rate, a lower deposition rate is selected to control the metal base. The average grain misorientation angle between the surface and the bottom of the metal-filled via structure is less than seven degrees.

綜上所述,如同前述實施例所述,透過金屬底座30表面與金屬填孔結構40底部之間的平均晶粒取向差角小於七度,能使得晶體間的晶體延續性增加,可增進整體的機械特性及電性,同時維持製程的速率,以及量產的規模。 In summary, as described in the foregoing embodiments, the average grain misorientation angle between the surface of the metal base 30 and the bottom of the metal filling structure 40 is less than seven degrees, which can increase the continuity of crystals between crystals and improve the overall Excellent mechanical characteristics and electrical properties, while maintaining the speed of the process and the scale of mass production.

雖然本發明的技術內容已經以較佳實施例揭露如上,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神所作些許之更動與潤飾,皆應涵蓋於本發明的範疇內,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 Although the technical content of the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any modification and modification made by those skilled in the art without departing from the spirit of the present invention should be covered by the present invention. Therefore, the scope of protection of the present invention should be defined by the scope of the appended patent application.

20:盲孔 20: blind hole

30:金屬底座 30: metal base

40:金屬填孔結構 40: Metal hole filling structure

45:化學銅層 45: chemical copper layer

Claims (9)

一種電路板結構,包含: 一介電板件本體,開設有一盲孔,該盲孔的底部包含一金屬底座;以及一金屬填孔結構,位於該金屬底座之上,且填滿該盲孔,其中該金屬底座的表面與該金屬填孔結構的底部之間的一平均晶粒取向差角(misorientation angle)小於七度。 A circuit board structure comprising: A dielectric plate body is provided with a blind hole, and the bottom of the blind hole includes a metal base; and a metal hole-filling structure is located on the metal base and fills the blind hole, wherein the surface of the metal base and the An average grain misorientation angle between the bottoms of the metal via structure is less than seven degrees. 如請求項1所述之電路板結構,其中該金屬底座及該金屬填孔結構的材質係選自由銅、錫、銀、金、鋅、鐵、鈷、以及鎳所構成之群組。The circuit board structure according to claim 1, wherein the material of the metal base and the metal filling structure is selected from the group consisting of copper, tin, silver, gold, zinc, iron, cobalt, and nickel. 如請求項2所述之電路板結構,其中該金屬底座為一壓合銅層或一電鍍銅層,該金屬填孔結構為一電鍍銅層。The circuit board structure according to claim 2, wherein the metal base is a laminated copper layer or an electroplated copper layer, and the metal hole filling structure is an electroplated copper layer. 如請求項3所述之電路板結構,其中在該盲孔的孔壁與該金屬填孔結構之間,以及該金屬底座與該金屬填孔結構之間,更包含一化學銅層,其中該化學銅層的厚度小於1μm。The circuit board structure as described in claim 3, wherein between the hole wall of the blind hole and the metal filling structure, and between the metal base and the metal filling structure, an chemical copper layer is further included, wherein the The thickness of the chemical copper layer is less than 1 μm. 如請求項4所述之電路板結構,其中該金屬底座的厚度為5至20μm,該金屬填孔結構的厚度為20至35μm。The circuit board structure according to claim 4, wherein the metal base has a thickness of 5 to 20 μm, and the metal hole filling structure has a thickness of 20 to 35 μm. 如請求項1所述之電路板結構,其中該金屬底座的表面與該金屬填孔結構的底部之間的該平均晶粒取向差角的範圍是1至5.5度。The circuit board structure as claimed in claim 1, wherein the average grain misorientation angle between the surface of the metal base and the bottom of the metal via structure is in a range of 1 to 5.5 degrees. 如請求項6所述之電路板結構,其中該金屬底座的表面與該金屬填孔結構的底部之間的該平均晶粒取向差角的範圍是2至5度。The circuit board structure as claimed in claim 6, wherein the average grain misorientation angle between the surface of the metal base and the bottom of the metal via structure is in a range of 2 to 5 degrees. 如請求項1所述之電路板結構,其中該金屬填孔結構進行電鍍的一沉積速率小於0.22μm/min。The circuit board structure as claimed in claim 1, wherein a deposition rate of the metal-filled hole structure for electroplating is less than 0.22 μm/min. 如請求項8所述之電路板結構,其中該金屬填孔結構進行電鍍的該沉積速率為0.044至0.176μm/min。The circuit board structure as claimed in claim 8, wherein the deposition rate of the metal filling via electroplating is 0.044 to 0.176 μm/min.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101174577A (en) * 2001-10-26 2008-05-07 应用材料公司 Integration of ald tantalum nitride and alpha-phase tantalum for copper metallization application
TW201840255A (en) * 2017-04-21 2018-11-01 南亞電路板股份有限公司 Circuit board structure and method for forming the same
TW201918590A (en) * 2017-11-08 2019-05-16 美商羅門哈斯電子材料有限公司 Electroplated copper
CN113811641A (en) * 2019-05-15 2021-12-17 住友电气工业株式会社 Printed wiring board

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101174577A (en) * 2001-10-26 2008-05-07 应用材料公司 Integration of ald tantalum nitride and alpha-phase tantalum for copper metallization application
TW201840255A (en) * 2017-04-21 2018-11-01 南亞電路板股份有限公司 Circuit board structure and method for forming the same
TW201918590A (en) * 2017-11-08 2019-05-16 美商羅門哈斯電子材料有限公司 Electroplated copper
CN113811641A (en) * 2019-05-15 2021-12-17 住友电气工业株式会社 Printed wiring board

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