TWI802524B - Package structure with FOWBCSP chip type and manufacturing method thereof - Google Patents

Abstract

A packaging structure with a FOWBCSP chip type and a manufacturing method thereof, the packaging structure includes a chip, the top of which includes contacts; a first packaging structure is located below and on the side of the chip; a substrate is placed above the chip, Wherein the position of the substrate corresponding to the contact point of the chip forms a penetrating plate hole, and a contact point is formed above the substrate; the lead wire passes through the plate hole of the substrate to connect the contact point of the substrate and the contact point of the chip; wherein the Each of the board holes of the substrate respectively forms a second packaging structure, which is formed by sealing the board holes with adhesive material, and the contacts above the substrate have conductive balls.

Description

Package structure with FOWBCSP chip type and manufacturing method thereof

The present invention relates to a semiconductor package structure, especially a package structure with a FOWBCSP chip type and a manufacturing method thereof.

In the prior art semiconductor chip packaging structure, the contacts of the chip are placed on the top, and the contacts of the substrate are also placed on the top, and then the contacts of the chip are used to connect the contacts of the substrate with exposed wires. In addition, a through hole is formed on the substrate to fill the conductive material, so that the contact crystal of the substrate is guided to the bottom of the substrate through the through hole filled with the conductive material. Then the circuit board is positioned under the substrate, so that the contacts on the circuit board are connected to the contacts on the substrate, and the purpose of electrical connection is achieved as a whole.

When packaging, the chip and the substrate must be completely covered and connected, so a larger area must be packaged to avoid the exposed wires, so the cost of packaging is higher and the time is longer.

In addition, a plurality of through-holes must be formed on the substrate to be poured with conductive materials, and these through-holes must be formed separately and cannot communicate with each other to avoid short circuits. Therefore, the manufacturing is time-consuming and labor-intensive, and increases the overall manufacturing cost.

Therefore, this case hopes to propose a brand-new packaging structure with FOWBCSP chip type and its manufacturing method to solve the above-mentioned defects in the prior art.

Therefore, the purpose of the present invention is to solve the problems in the above-mentioned prior art. In the present invention, a packaging structure with a FOWBCSP chip type and its manufacturing method are proposed. The advantage is that only a small number of plate holes need to be formed on the substrate, and Multiple wires pass through one plate hole at the same time, instead of forming multiple plate holes in the traditional structure, so the manufacturing period is shortened and the cost is also reduced. In addition, in this case, only a small number of areas that may be exposed to wires need to be packaged during packaging, instead of the traditional structure and the packaged area is not above the entire chip and substrate, so the packaging method of this case can save costs and man-hours. Furthermore, because the length of the wire is short and most of it is hidden inside the plate hole, it will not cause the wire to be exposed and cause other hazards.

In order to achieve the above object, the present invention proposes a packaging structure with a FOWBCSP chip type, comprising: a chip, the top of the chip includes contacts; a first packaging structure is positioned at the bottom and side of the chip; a substrate is placed on the chip. On the top of the chip, the position of the substrate corresponding to the contact of the chip forms a penetrating plate hole, and the top of the substrate forms a contact; the contact of the substrate and the contact of the chip are connected by a wire passing through the plate hole of the substrate and wherein each of the board holes of the substrate respectively forms a second packaging structure, which is formed by sealing the board holes with adhesive material, and the contacts above the substrate have conductive balls.

This case still proposes a kind of manufacturing method that has the package structure of FOWBCSP chip form, comprises the following steps: Step A: Take a chip, the bottom of this chip contains contacts; Place a non-adhesive film on the bottom of this chip, and then The carrier is placed under the non-adhesive film; and a first packaging structure is formed on the top and side of the chip; then the overall structure is transported to a predetermined position; step B: unloading the carrier and the non-adhesive film, and turning the wafer over so that the contacts of the wafer are above the wafer; and the first packaging structure is reversed to the bottom; step C: placing a substrate above the wafer, wherein the substrate is The position of the contact point of the chip should be formed through the plate hole, and on the substrate Form the contacts; use wires to connect the contacts of the substrate and the contacts of the chip through the holes of the substrate; step D: apply glue to seal the holes of the substrate to form a second package structure, and connect the contacts above the substrate The dots form conductive balls to form an integrated structure.

The features and advantages of the present invention can be further understood from the following description, please refer to the accompanying drawings when reading.

1: The first package structure

2: The second package structure

10: Wafer

11: Contact

12: Light sensing area

20: Substrate

21: Contact

22: plate hole

23: hollow area

30: Guide and catch the ball

40: circuit board

41: contact

42: perforation

50: inner chip

51: contact

60: wire

61: wire

70: CMOS chip

80: isolation film

81: Block lift

90: glass

100: non-adhesive film

110: carrier board

200: Glue

231: Inner contact

232: Encapsulation material

300: package structure

FIG. 1 shows an exploded view of the chip, substrate and circuit board of the first embodiment of the present invention.

FIG. 2A shows a schematic cross-sectional view of the device configuration in step A of the first embodiment of the present invention.

FIG. 2B shows a schematic cross-sectional view of the device configuration in step B of the first embodiment of the present invention.

FIG. 2C shows another schematic cross-sectional view of the device configuration in step B of the first embodiment of the present invention.

FIG. 2D shows a schematic cross-sectional view of the device configuration in step C of the first embodiment of the present invention.

FIG. 2E shows a schematic cross-sectional view of the device configuration in step D of the first embodiment of the present invention.

FIG. 2F shows a schematic diagram of the application of the first embodiment of the present invention.

FIG. 3A shows a schematic cross-sectional view of the component combination of the first embodiment of the present invention.

FIG. 3B shows a schematic cross-sectional view of an application example of the combination of components in FIG. 3A .

FIG. 4A shows a schematic cross-sectional view of the device configuration in step A of the second embodiment of the present invention.

FIG. 4B shows a schematic cross-sectional view of the device configuration in step B of the second embodiment of the present invention.

FIG. 4C shows another schematic cross-sectional view of the device configuration in step B of the second embodiment of the present invention.

FIG. 4D shows a schematic cross-sectional view of the device configuration in step C of the second embodiment of the present invention.

FIG. 4E shows a schematic cross-sectional view of the device arrangement in step D of the second embodiment of the present invention.

FIG. 5 shows a schematic cross-sectional view of the component assembly of the second embodiment of the present invention.

FIG. 6 shows an exploded schematic diagram of a plurality of chips, substrates and circuit boards of the third embodiment of the present invention.

FIG. 7A shows a schematic cross-sectional view of the device arrangement in step A1 of the third embodiment of the present invention.

FIG. 7B shows a schematic cross-sectional view of the device arrangement in step B1 of the third embodiment of the present invention.

FIG. 7C shows another schematic cross-sectional view of the device arrangement in step B1 of the third embodiment of the present invention.

FIG. 7D shows a schematic cross-sectional view of the device arrangement in step C1 of the third embodiment of the present invention.

FIG. 7E shows a schematic cross-sectional view of the device arrangement in step D1 of the third embodiment of the present invention.

FIG. 7F shows a schematic diagram of the application of the third embodiment of the present invention.

FIG. 8 shows an exploded view of the chip, substrate and circuit board of the fourth embodiment of the present case.

FIG. 9A shows a schematic cross-sectional view of the device arrangement in step A2 of the fourth embodiment of the present invention.

FIG. 9B shows a schematic cross-sectional view of the component arrangement in step B2 of the fourth embodiment of the present invention.

FIG. 9C shows another schematic cross-sectional view of the device arrangement in step B2 of the fourth embodiment of the present invention.

FIG. 9D shows a schematic cross-sectional view of the device arrangement in step C2 of the fourth embodiment of the present invention.

FIG. 9E shows another schematic cross-sectional view of the device arrangement in step C2 of the fourth embodiment of the present invention.

FIG. 9F shows a schematic cross-sectional view of the device arrangement in step D2 of the fourth embodiment of the present invention.

FIG. 9G shows a schematic diagram of the application of the fourth embodiment of the present application.

FIG. 10A shows a schematic cross-sectional view of the component combination of the fourth embodiment of the present invention.

FIG. 10B shows a schematic cross-sectional view of an application example of the combination of components in FIG. 10A .

FIG. 11 shows a flow chart of the steps of the manufacturing method of the first embodiment of the present invention.

FIG. 12 shows a flow chart of the steps of the manufacturing method of the second embodiment of the present invention.

FIG. 13 shows a flow chart of the steps of the manufacturing method of the third embodiment of the present invention.

FIG. 14 shows a flow chart of the steps of the manufacturing method of the fourth embodiment of the present invention.

Hereby, I would like to cite the structure of this case, as well as the functions and advantages that can be produced, in conjunction with the diagram. A preferred embodiment of the scheme is described in detail as follows.

Please refer to FIG. 1 to FIG. 2F, and shown in FIG. 11, which shows the first embodiment of the manufacturing method of the packaging structure with the FOWBCSP chip type of the present invention, including the following steps:

Step A: As shown in FIG. 2A , take a wafer 10 with contacts 11 under the wafer 10 . A non-adhesive film 100 is placed under the chip 10 , and a carrier 110 is placed under the non-adhesive film 100 ; and a first packaging structure 1 is formed on the top and side of the chip 10 . Then transport the whole structure to the predetermined location;

Step B: As shown in FIG. 2B, remove the carrier plate 110 and the non-adhesive film 100, and reverse the wafer 10 (as shown in FIG. 2C ), so that the contacts 11 of the wafer 10 are located on the wafer. 10; and the first package structure 1 is reversed to the bottom.

Step C: As shown in FIG. 2D, a substrate 20 is placed above the chip 10, wherein the position of the substrate 20 corresponding to the contact point 11 of the chip 10 forms a plate hole 22 penetrating, and on the substrate 20 Contacts 21 are formed above. Wires 60 are used to connect the contacts 21 of the substrate 20 and the contacts 11 of the chip 10 through the holes 22 of the substrate 20 .

Step D: As shown in FIG. 2E , apply glue 200 to seal the plate hole 22 of the substrate 20 to form a second packaging structure 2, and form a connection ball 30 at the contact point 21 above the substrate 20 (the connection ball 30 is as shown in FIG. solder balls or solder balls) to form an integrated structure.

As shown in FIG. 2F , a circuit board 40 can be disposed above the substrate 20 of the above-mentioned integrated structure during application, wherein the circuit board 40 can form contacts 41 to connect the contacts on the contacts 21 above the substrate 20. ball 30 to form electrical communication.

In this case, the above-mentioned structure is used to form a package structure 300 in the form of a FOWBCSP chip, as shown in FIG. 3A , including:

A chip 10 includes contacts 11 above the chip 10 .

A first packaging structure 1 is located below and beside the chip 10 .

A substrate 20 is placed on top of the chip 10 , where the substrate 20 is formed at a position corresponding to the contact 11 of the chip 10 through a plate hole 22 , and the top of the substrate 20 is formed with a contact 21 . The contacts 21 of the substrate 20 and the contacts 11 of the chip 10 are connected by wires 60 through the holes 22 of the substrate 20 .

Wherein each of the board holes 22 of the substrate 20 respectively forms a second package structure 2, which is formed by sealing the board holes 22 with an adhesive material 200, and the contact 21 above the substrate 20 has a conductive ball 30 (the conductive ball 30 such as solder balls or solder balls).

As shown in FIG. 3B , a circuit board 40 is disposed above the substrate 20 during application, wherein the circuit board 40 can form contacts 41 to connect the conductive balls 30 on the contacts 21 above the substrate 20 to form Electrically connected.

This case still includes the second embodiment, as shown in FIG. 4A to FIG. 4E and FIG. 12 . Wherein the steps of the second embodiment are exactly the same as the steps of the first embodiment, step A shown in Figure 3A and step B shown in Figure 3B to Figure 3C, its content is completely the same as the steps A and B of the first embodiment above The same, so I won't repeat its content here. However, in step C, as shown in FIG. 3D, a hollow area 23 is formed under the substrate 20, and at least one inner chip 50 is installed on the hollow area 23 (to be different from other chips 10 not in the hollow area 23). 50 connects the internal contact 231 of the substrate 20 on the inner wall surface of the hollow area 23 via the wire 61 with the contact 51 below it (to be different from the contact 21 above the substrate 20), wherein the internal contact 231 runs through the substrate 20 itself is exposed above the substrate 20 . And the encapsulation material 232 is used to encapsulate the hollow area 23 as a whole. Subsequent step D is shown in FIG. 3E , and its content is exactly the same as step D in the above-mentioned first embodiment, so it will not be repeated here.

As shown in Figure 5, so through the above steps, the original Figure 3 has a FOWBCSP wafer type The encapsulation structure 300 is further formed as shown in FIG. 5 . The structure in Fig. 5 has the same structure and effect as the same elements in Fig. 3, so the details thereof will not be repeated, but the structure in Fig. 5 still includes:

A hollowed-out area 23 is formed below the inside of the substrate 20, and at least one inner chip 50 is installed in the hollowed-out area 23 (to be different from other chips 10 not in the hollowed-out area 23), and the contacts 51 below the inner chip 50 are connected to the hollowed-out area via wires 61. The internal contact 231 of the substrate 20 on the inner wall of the region 23 (different from the contact 21 above the substrate 20 ), wherein the internal contact 231 is exposed above the substrate 20 through the substrate 20 itself. And the hollow area 23 is encapsulated by the encapsulation material 232 .

This case still includes the third embodiment, as shown in Figure 6 to Figure 7E and Figure 13, which shows the structure of packaging multiple chips 10 at the same time in this case, the processing steps are as follows:

Step A1: As shown in FIG. 7A, take a plurality of wafers 10, and each wafer 10 contains contacts 11 under it. A non-adhesive film 100 is placed under the plurality of chips 10, and a carrier 110 is placed under the non-adhesive film 100; and a first packaging structure 1 is formed on the top and sides of the plurality of chips 10 . Then transport the whole structure to the predetermined location;

Step B1: As shown in FIG. 7B, remove the carrier plate 110 and the non-adhesive film 100, and reverse the plurality of wafers 10 (as shown in FIG. 7C ), so that the contacts of each wafer 10 have 11 positions above the corresponding chips 10; and the first packaging structure 1 is reversed to the bottom.

Step C1: As shown in FIG. 7D , place a substrate 20 above the plurality of chips 10 , where the positions of the substrate 20 corresponding to the contacts 11 of the plurality of chips 10 form a plurality of plate holes 22 penetrating through, A plurality of contacts 21 are formed on the substrate 20 . A plurality of wires 60 are used to connect the plurality of contacts 21 of the substrate 20 and the contacts 11 of the plurality of chips 10 through the plurality of holes 22 of the substrate 20 .

Step D1: As shown in FIG. 7E , apply glue 200 to seal the plurality of plate holes 22 of the substrate 20 to form a second packaging structure 2 , and form a plurality of conductive balls 30 at the plurality of contacts 21 above the substrate 20 ( The lead ball 30 such as solder balls or solder balls).

As shown in FIG. 7F , during application, cutting may be performed according to the position of each wafer 10 as required, so that each wafer 10 and its related substrate 20 etc. form an integrated structure; 40 , the circuit board 40 can form contact points 41 to connect the conductive balls 30 on the contact points 21 above the substrate 20 to form electrical communication.

In this case, the chip 10 mentioned above can be a chip of various forms such as an MCU chip or a logic chip.

This case still includes the fourth embodiment, as shown in Fig. 8 to Fig. 9G and Fig. 14, wherein the chip 10 in each of the above-mentioned embodiments may also be a CMOS chip 70, and its detailed operation steps are as follows:

Step A2: As shown in FIG. 9A, take a chip 10, which is a CMOS chip 70, and the bottom of the chip 10 includes contacts 11 and photosensitive regions 12 for receiving external light and passing it inside to make CMOS photosensitive. A non-adhesive film 100 is placed under the chip 10 , and a carrier 110 is placed under the non-adhesive film 100 ; and a first packaging structure 1 is formed on the top and side of the chip 10 . Then transport the whole structure to the predetermined location;

Step B2: As shown in FIG. 9B, remove the carrier plate 110 and the non-adhesive film 100, and reverse the wafer 10 (as shown in FIG. 9C ), so that the contact 11 of the wafer 10 and the light The sensing region 12 is located above the chip 10; and the first packaging structure 1 is reversed to the bottom.

Step C2: As shown in FIG. 9D , place a substrate 20 above the chip 10 , where the substrate 20 corresponds to the positions of the contact points 11 and the photosensitive regions 12 of the chip 10 to form through-holes 22 , and forming contacts 21 above the substrate 20;

Then an isolation film 80 is formed above the photosensitive region 12 of the wafer 10, and barrier banks 81 are respectively formed on both sides of the isolation film 80, and then the isolation film 80 is removed, and a barrier film is placed between the two barrier banks 81 glass 90 (as shown in Figure 9E); and

Then, wires 60 are used to connect the contacts 21 of the substrate 20 and the contacts 11 of the chip 10 through the holes 22 of the substrate 20 .

Step D2: As shown in FIG. 9F , apply adhesive material 200 to seal the plate hole 22 of the substrate 20 to form the second package structure 2 without covering the glass 90 so that the glass 90 is exposed so that external light can be directly The CMOS wafer 70 is irradiated through the glass 90 to form conductive balls 30 (such as solder balls or solder balls) on the contacts 21 above the substrate 20 to form an integrated structure.

As shown in FIG. 9G , a circuit board 40 can be arranged above the substrate 20 of the above-mentioned integrated structure during application, wherein the circuit board 40 is a flexible board, and a penetrating through hole 42 is formed on the circuit board 40 , the through hole 42 The position is corresponding to the glass 90 , so that external light can pass through the glass 90 through the through hole 42 to illuminate the CMOS wafer 70 . Wherein the circuit board 40 can form contact points 41 to connect the conductive balls 30 on the contact points 21 above the substrate 20 to form electrical communication.

In this case, the above-mentioned structure is used to form a package structure 300 in the form of a FOWBCSP chip, as shown in FIG. 10A , including:

A CMOS chip 70 , the top of the chip 10 includes contacts 11 and photo-sensing regions 12 .

A first packaging structure 1 is located below and beside the CMOS chip 70 .

A substrate 20 is placed on the top of the CMOS chip 70, wherein the substrate 20 corresponds to the position of the contact 11 and the photosensitive region 12 of the CMOS chip 70 to form a through plate hole 22; and the top of the substrate 20 forms a contact Point 21. The contact 21 of the substrate 20 and the contact 11 of the CMOS chip 70 are connected by the wire 60 through the hole 22 of the substrate 20 .

Two barrier banks 81 are located on two sides above the photo-sensing region 12 of the CMOS wafer 70 .

A glass 90 is placed between the two barrier banks 81 .

Each of the plate holes 22 of the substrate 20 respectively forms a second package structure 2, which is formed by sealing the plate holes 22 with an adhesive material 200, and does not cover the glass 90, so that the glass 90 is exposed, so the external light The CMOS wafer 70 can be illuminated directly through the glass 90 .

The contacts 21 above the substrate 20 have conductive balls 30 (such as solder balls or solder balls).

As shown in FIG. 10B , a circuit board 40 is arranged above the substrate 20 during application, wherein the circuit board 40 can form contacts 41 to connect the conductive balls 30 on the contacts 21 above the substrate 20 to form Electrically connected.

Similarly, like the above-mentioned third embodiment, multiple CMOS wafers 70 can be arranged side by side to carry out the above-mentioned packaging procedure in this case. Since the manufacturing process is the same as the third embodiment, the details will not be described here.

The advantage of this case is that only a few plate holes need to be formed on the substrate, so that multiple wires pass through one plate hole at the same time, unlike the traditional structure that must form multiple plate holes, so the manufacturing period is shortened and the cost is also reduced. In addition, in this case, only a small number of areas that may be exposed to wires need to be packaged during packaging, instead of the traditional structure and the packaged area is not above the entire chip and substrate, so the packaging method of this case can save costs and man-hours. Furthermore, because the length of the wire is short and most of it is hidden inside the plate hole, it will not cause the wire to be exposed and cause other hazards.

To sum up, the humanized and thoughtful design of this case is quite in line with actual needs. Its specific improvement has existing deficiencies, and compared with the prior art, it has the advantage of breakthrough progress, and indeed has the enhancement of efficacy, and it is not easy to achieve. This case has not been published or disclosed in domestic and foreign literature and market, which is in compliance with the provisions of the patent law.

The above detailed description is a specific description of a feasible embodiment of the present invention, but this embodiment is not used to limit the patent scope of the present invention, any equivalent practice that does not depart from the technical spirit of the present invention Any implementation or modification shall be included in the patent scope of this case.

1: The first package structure

2: The second package structure

10: Wafer

11: Contact

20: Substrate

21: Contact

22: plate hole

30: Guide and catch the ball

40: circuit board

41: contact

60: wire

200: Glue

Claims (6)

A packaging structure with a FOWBCSP chip type, comprising: a chip including contacts thereon; A first packaging structure is located on the bottom and side of the chip; A substrate is placed above the chip, wherein the position of the substrate corresponding to the contact of the chip forms a penetrating plate hole, and the top of the substrate forms a contact; the contact of the substrate is connected by a wire passing through the plate hole of the substrate and the contacts of the chip; and Wherein each of the plate holes of the substrate respectively forms a second packaging structure, which is formed by sealing the plate holes with adhesive material, and the contacts above the substrate have conductive balls; Two dams; wherein the chip is a CMOS chip; above the CMOS chip also includes a light sensing area; the penetrating plate hole of the substrate corresponds to the position of the contact point and the light sensing area of the CMOS chip; wherein the Two blocking banks are located on both sides above the photo-sensing area of the CMOS wafer; a glass is placed between the two barriers; and The second encapsulation structure does not cover the glass, so that the glass is exposed, so that external light can directly irradiate the CMOS chip through the glass. The packaging structure with the FOWBCSP chip type described in item 1 of the patent scope of the application also includes a circuit board located above the substrate, wherein the contacts on the circuit board are connected to the contacts on the substrate to form Electrical communication; wherein a penetrating hole is formed on the circuit board, and the position of the hole is corresponding to the glass, so that external light can pass through the glass through the hole to illuminate the CMOS chip. The packaging structure having a FOWBCSP chip type as described in item 2 of the scope of the patent application, wherein the circuit board is a flexible board. A method for manufacturing a packaging structure with a FOWBCSP chip type, comprising the following steps: Step A: Take a chip with contacts under the chip; place a non-adhesive film under the chip, then place the carrier under the non-adhesive film; Forming the first packaging structure; then transporting the overall structure to a predetermined location; Step B: removing the carrier board and the non-adhesive film, and turning the chip over so that the contacts of the chip are above the chip; and the first packaging structure is turned down; Step C: Place a substrate on top of the chip, wherein the position of the substrate corresponding to the contact point of the chip forms a penetrating plate hole, and forms a contact point above the substrate; use wires to connect through the plate hole of the substrate the contacts of the substrate and the contacts of the chip; Step D: sealing the plate hole of the substrate with adhesive material to form a second packaging structure, and forming conductive balls on the contacts above the substrate to form an integrated structure; Wherein the chip is a CMOS chip, and the bottom of the chip still includes a photosensitive area for receiving external light and passing it inside to make the CMOS photosensitive; And in the step C, the plate holes of the substrate correspond to the positions of the contact points and the light-sensing regions of the chip; And before using wires to connect the contacts of the substrate and the chips, an isolation film is formed above the photosensitive area of the chip, and barrier banks are formed on both sides of the isolation film, and then the isolation film is removed , place glass between the two dams. The manufacturing method of the FOWBCSP chip-type packaging structure as described in item 4 of the scope of the patent application, wherein after step D, a circuit board is arranged above the substrate, and the substrate is connected through the contacts on the circuit board The upper contact to form electrical connection; and form a penetrating hole on the circuit board, the position of the hole is corresponding to the glass, so that the external light can pass through The through hole penetrates the glass to illuminate the CMOS wafer. The manufacturing method of the packaging structure with FOWBCSP chip type as described in item 5 of the scope of patent application, wherein the circuit board is a flexible board.

Images