TW202127641A - Package structure with FOWBCSP CMOS chip module where most of wires are hidden in the plate aperture and capable of shortening manufacturing time with reduced cost - Google Patents

Abstract

A package structure with FOWBCSP CMOS chip module comprises a CMOS chip having joints and a light sensing area on the upper side thereof; two baffles located on both sides on the top of the light sensing area; a substrate placed on the CMOS chip and having a perforated plate aperture corresponding to the position of joints and the light sensing area of the CMOS chip, so that the light beam can pass through the plate aperture to illuminate the light sensing area; a glass located above the light sensing area of the CMOS chip, through which external light directly illuminates the CMOS chip. The present invention can arrange joints on the top of the substrate and connect the joints of the CMOS chip via wires; or arrange the upper and lower joints connected to each other above and under the substrate, whereby the lower joints is connected to joints of the CMOS chip; or at least one side of the substrate is extended to the outside of the CMOS chip, and lower joints can be arranged below the substrate, and the lower joints can simultaneously connect to the CMOS chip and joints of the circuit board located under the substrate.

Description

Package structure with FOWBCSP CMOS chip type

The present invention relates to a semiconductor packaging structure, in particular to a packaging structure with FOWBCSP CMOS chip type.

In the conventional semiconductor chip packaging structure, the contacts of the chip are placed on the top, and the contacts of the substrate are also placed on the top, and then the contacts of the chip are used to connect the contacts of the substrate with bare wires. In addition, a through hole is formed on the substrate to fill the conductive material, so that the contact crystal of the substrate is guided to the bottom of the substrate through the through hole filled with the conductive material. Then the circuit board is located below the substrate, so that the contacts on the circuit board are connected to the contacts on the substrate, and the purpose of electrical connection is achieved as a whole.

When packaging, the chip and the substrate must be completely covered and connected, so a larger area must be packaged to prevent the wires from being exposed, so the packaging cost is higher and the time is longer.

In addition, a plurality of through holes must be formed on the substrate to be respectively filled with conductive materials. These through holes must be formed separately and cannot communicate with each other to avoid short circuits. Therefore, the manufacturing is quite time-consuming and labor-consuming, which also increases the overall manufacturing cost.

Therefore, this case hopes to propose a new package structure with FOWBCSP CMOS chip type to solve the above-mentioned defects in the prior art.

Therefore, the purpose of the present invention is to solve the above-mentioned conventional technical problems. In the present invention, a package structure with FOWBCSP CMOS chip type is proposed. Only a single plate hole needs to be formed on the substrate, so that multiple wires can pass through the same at the same time. The plate hole is not required to form multiple plate holes in the traditional structure, so the manufacturing period is shortened and the cost is also reduced. In this case, contacts can be arranged above the substrate and connected to the contacts of the CMOS chip via wires; or above and below the substrate are arranged to connect the upper and lower contacts, and the lower contacts are connected to the CMOS chip contact; or extend at least one side of the substrate to the outside of the CMOS chip, and a lower contact is arranged under the substrate, and the lower contact is simultaneously connected to the CMOS chip and located under the substrate The contact point of the circuit board. Furthermore, in this case, only a few areas where the wires may be exposed are required to be packaged, instead of covering the entire chip and substrate as in the traditional structure and packaging area. Therefore, the packaging method in this case can save cost and man-hours. Furthermore, because the length of the wire is short and most of it is hidden inside the board hole, it will not cause the wire to be exposed and cause other hazards.

In order to achieve the above objective, the present invention proposes a package structure with FOWBCSP CMOS chip type, which includes a CMOS chip. The upper part of the CMOS chip includes contacts and a light sensing area; two barriers are located on the light sensing area of the CMOS chip. The upper two sides of the measurement area; a substrate is placed above the CMOS chip, wherein the substrate has a through hole, and the hole corresponds to the contact point of the CMOS chip and the position of the light sensing area, and The light can pass through the hole to illuminate the light sensing area, and a contact is formed above the substrate; a wire passes through the hole of the substrate to connect the contact of the substrate and the contact of the CMOS chip; a glass is located on the Above the light sensing area of the CMOS chip; and where the plate hole of the substrate forms a second package structure which is formed by sealing the plate hole with glue; where the second package structure does not cover the glass, so that The glass is exposed, so external light can directly illuminate the CMOS chip through the glass; wherein the contact point above the substrate has a conductive connection ball.

This case also proposes a package structure with FOWBCSP CMOS chip type, including a CMOS chip, the upper part of the CMOS chip includes contacts and a light sensing area; two barriers, located above the light sensing area of the CMOS chip On both sides; a substrate is placed above the CMOS chip, wherein the substrate has a through hole, the hole corresponds to the position of the light sensing area of the CMOS chip and the two barriers, so that light can be The light sensing area is irradiated through the plate hole; wherein an upper contact is formed above the substrate, and a lower contact is formed below the substrate; wherein the upper contact is connected to a corresponding corresponding via an inner wire located inside the substrate Lower contact; the substrate is connected to the corresponding contact on the CMOS chip via the lower contact; wherein the upper contact above the substrate has a conductive ball; and a glass is placed on the upper ends of the two barriers, and A gap is formed between the glass and the CMOS chip; therefore, external light can directly illuminate the CMOS chip through the glass.

This case also proposes a package structure with FOWBCSP CMOS chip type, including a CMOS chip, the upper part of the CMOS chip includes contacts and a light sensing area; two barriers, located above the light sensing area of the CMOS chip On both sides; a substrate is placed above the CMOS chip, wherein the substrate has a through hole, the hole corresponds to the position of the light sensing area of the CMOS chip and the two barriers, so that light can be The light sensing area is irradiated through the plate hole; wherein a lower contact is formed under the substrate; the substrate is connected to the corresponding contact on the CMOS chip through the lower contact; wherein at least one side of the substrate and the at least one The lower contact corresponding to the side extends to the outside of the CMOS chip; and a glass is placed on the upper ends of the two barriers, and a gap is formed between the glass and the CMOS chip; therefore, external light can directly pass through the CMOS chip. The glass irradiates the CMOS wafer.

The features and advantages of the present invention can be further understood from the following description. Please refer to the Consider the attached drawings.

1‧‧‧The first package structure

2‧‧‧Second package structure

11‧‧‧Contact

12‧‧‧Light sensing area

20‧‧‧Substrate

21‧‧‧Contact

22‧‧‧Plate hole

23‧‧‧Upper contact

24‧‧‧Lower contact

30‧‧‧Guiding the ball

40‧‧‧Circuit board

41‧‧‧Contact

42‧‧‧Perforation

60‧‧‧Wire

65‧‧‧Inner wire

70‧‧‧CMOS chip

81‧‧‧Block Dike

90‧‧‧Glass

95‧‧‧Gap

200‧‧‧Glue

300‧‧‧Packaging structure

FIG. 1A shows an exploded schematic diagram of the CMOS chip, substrate, and circuit board of the first embodiment of the present application.

FIG. 1B shows a schematic cross-sectional view of the component assembly of the first embodiment of the present application.

FIG. 1C shows a schematic cross-sectional view of an application example of the component combination of FIG. 1B.

2A shows an exploded schematic diagram of the CMOS chip, substrate and circuit board of the second embodiment of the present application.

2B shows a schematic cross-sectional view of the component combination of the second embodiment of the present application.

FIG. 2C shows a schematic cross-sectional view of an application example of the component combination of FIG. 2B.

FIG. 3A shows an exploded schematic diagram of the CMOS chip, substrate and circuit board of the third embodiment of the present application.

FIG. 3B shows a schematic cross-sectional view of the component combination of the third embodiment of the present application.

FIG. 3C shows a schematic cross-sectional view of an application example of the component combination of FIG. 3B.

4A shows an exploded schematic diagram of the CMOS chip, substrate and circuit board of the fourth embodiment of the present application.

FIG. 4B shows a schematic cross-sectional view of the component assembly of the fourth embodiment of the present application.

4C shows a schematic cross-sectional view of an application example of the component combination of FIG. 4B.

With regard to the structural composition of this case, and the effects and advantages that can be produced, in conjunction with the drawings, a preferred embodiment of this case is described in detail as follows.

Please refer to FIGS. 1A to 1C, which show the FOWBCSP CMOS chip type of the present invention The first embodiment of the package structure 300 includes the following components:

A CMOS chip 70, the upper part of the CMOS chip 70 includes the contact 11 and the light sensing area 12.

A first package structure 1 is located below and on the side of the CMOS chip 70.

Two barriers 81 are located on the upper two sides of the light sensing area 12 of the CMOS chip 70.

A substrate 20 is placed above the CMOS chip 70, wherein the substrate 20 has a through hole 22 corresponding to the position of the contact 11 of the CMOS chip 70 and the light sensing area 12, and The light can pass through the plate hole 22 to illuminate the light sensing area 12. A contact 21 is formed above the substrate 20. The contact 21 of the substrate 20 and the contact 11 of the CMOS chip 70 are connected by a wire 60 through the hole 22 of the substrate 20.

A glass 90 is located above the light sensing area 12 of the CMOS chip 70, and the glass 90 is placed between the two barriers 81.

The plate hole 22 of the substrate 20 forms a second packaging structure 2 which is formed by sealing the plate hole 22 with glue 200 without covering the glass 90, so that the glass 90 is exposed, so external light can be directly exposed. The CMOS wafer 70 is irradiated through the glass 90.

The contact 21 above the substrate 20 has a conductive ball 30 (the conductive ball 30 is a tin ball or a solder ball).

As shown in FIG. 1C, a circuit board 40 is disposed above the substrate 20 during application. The circuit board 40 is a flexible board, and a through hole 42 is formed on the circuit board 40. The position of the hole 42 corresponds to On the glass 90, external light can penetrate the glass 90 through the through hole 42 to illuminate the CMOS chip 70. The conductive ball 30 on the contact 21 above the substrate 20 is connected to the contact 41 on the circuit board 40 to form electrical communication.

2A to 2C show the second embodiment of this case. In this embodiment, the same elements as the above-mentioned embodiments are represented by the same symbols and have the same functions, so the details are not repeated here. Down Only the differences are explained in the article.

In this embodiment, the glass 90 is placed on the upper ends of the two barriers 81, and a gap 95 is formed between the glass 90 and the CMOS wafer 70.

As shown in FIG. 2C, a circuit board 40 is arranged above the substrate 20 during application. The conductive ball 30 on the contact 21 above the substrate 20 is connected to the contact 41 on the circuit board 40 to form electrical communication.

FIGS. 3A to 3C show the third embodiment of the present invention. The wire 60 is not provided, and the lower contact 24 is formed directly under the substrate 20 for connecting to the contact 11 above the CMOS chip 70. This embodiment includes the following elements:

A CMOS chip 70, the upper part of the CMOS chip 70 includes the contact 11 and the light sensing area 12.

A first package structure 1 is located below and on the side of the CMOS chip 70.

Two barriers 81 are located on the upper two sides of the light sensing area 12 of the CMOS chip 70.

A substrate 20 is placed above the CMOS chip 70, wherein the substrate 20 has a through hole 22 corresponding to the position of the light sensing area 12 and the two barriers 81 of the CMOS chip 70 , So that light can pass through the plate hole 22 to illuminate the light sensing area 12; wherein an upper contact 23 is formed above the substrate 20, and a lower contact 24 is formed below the substrate 20. The upper contact 23 is connected to a corresponding lower contact 24 via an inner wire 65 located inside the substrate 20. The substrate 20 is connected to the corresponding contact 11 on the CMOS chip 70 via the lower contact 24.

A glass 90 is placed on the upper ends of the two barriers 81, and a gap 95 is formed between the glass 90 and the CMOS chip 70.

Therefore, external light can directly illuminate the CMOS chip 70 through the glass 90.

The upper contact 23 above the substrate 20 has a conductive ball 30 (the conductive ball 30 is a tin ball or a solder ball).

As shown in FIG. 3C, a circuit board 40 is disposed above the substrate 20 during application. The circuit board 40 is a flexible board, and a through hole 42 is formed on the circuit board 40. The position of the hole 42 corresponds to On the glass 90, external light can penetrate the glass 90 through the through hole 42 to illuminate the CMOS chip 70. The conductive ball 30 on the contact 21 above the substrate 20 is connected to the contact 41 on the circuit board 40 to form electrical communication.

4A to 4C show the fourth embodiment of the present case, which is to extend the substrate 20 to the outside of the CMOS chip 70, and form a lower contact 24 below the substrate 20 for connecting the contact 11 above the CMOS chip 70 , And the contact 41 on the circuit board 40. This embodiment includes the following elements:

A CMOS chip 70, the upper part of the CMOS chip 70 includes the contact 11 and the light sensing area 12.

A first package structure 1 is located below and on the side of the CMOS chip 70.

Two barriers 81 are located on the upper two sides of the light sensing area 12 of the CMOS chip 70.

A substrate 20 is placed above the CMOS chip 70, wherein the substrate 20 has a through hole 22 corresponding to the position of the light sensing area 12 and the two barriers 81 of the CMOS chip 70 , So that light can pass through the plate hole 22 to illuminate the light sensing area 12. A lower contact 24 is formed under the substrate 20. The substrate 20 is connected to the corresponding contact 11 on the CMOS chip 70 via the lower contact 24.

At least one side of the substrate 20 and the lower contact 24 corresponding to the at least one side extend to the outside of the CMOS chip 70.

A glass 90 is placed on the upper ends of the two barriers 81, and a gap 95 is formed between the glass 90 and the CMOS chip 70.

Therefore, external light can directly illuminate the CMOS chip 70 through the glass 90.

As shown in FIG. 4C, a circuit board 40 is disposed under the substrate 20 during application, wherein the lower contact 24 on the substrate 20 that extends to the outside of the CMOS chip 70 is connected to the contact on the circuit board 40 41, so that the circuit board 40 and the CMOS chip 70 are in electrical communication.

In this case, a plurality of CMOS chips 70 can be arranged side by side to form the above-mentioned package structure. The rest of the structure is the same as the above-mentioned embodiments, so the details will not be repeated.

The advantage of this case is that only a single plate hole needs to be formed on the substrate, and multiple wires pass through the plate hole at the same time, instead of forming multiple plate holes in the traditional structure, the manufacturing period is shortened and the cost is also reduced. In this case, contacts can be arranged above the substrate and connected to the contacts of the CMOS chip via wires; or above and below the substrate are arranged to connect the upper and lower contacts, and the lower contacts are connected to the CMOS chip contact; or extend at least one side of the substrate to the outside of the CMOS chip, and a lower contact is arranged under the substrate, and the lower contact is simultaneously connected to the CMOS chip and located under the substrate The contact point of the circuit board. Furthermore, in this case, only a few areas where the wires may be exposed are required to be packaged, instead of covering the entire chip and substrate as in the traditional structure and packaging area. Therefore, the packaging method in this case can save cost and man-hours. Furthermore, because the length of the wire is short and most of it is hidden inside the board hole, it will not cause the wire to be exposed and cause other hazards.

In summary, the humanized and considerate design of this case is quite in line with actual needs. Compared with the conventional technology, the specific improvement of the existing defects is obviously a breakthrough advantage, and it does have an increase in efficacy, and it is not easy to achieve. This case has not been disclosed or disclosed in domestic and foreign documents and markets, and it has complied with the provisions of the Patent Law.

The above detailed description is a specific description of a possible embodiment of the present invention, but this embodiment is not intended to limit the scope of the patent of the present invention. Any equivalent implementation or modification that does not deviate from the technical spirit of the present invention should be included in In the scope of the patent in this case.

1‧‧‧The first package structure

2‧‧‧Second package structure

11‧‧‧Contact

12‧‧‧Light sensing area

20‧‧‧Substrate

30‧‧‧Guiding the ball

60‧‧‧Wire

70‧‧‧CMOS chip

81‧‧‧Block Dike

90‧‧‧Glass

21‧‧‧Contact

22‧‧‧Plate hole

200‧‧‧Glue

300‧‧‧Packaging structure

Claims (16)

A package structure with FOWBCSP CMOS chip type, including: A CMOS chip, the upper part of the CMOS chip includes contacts and a light sensing area; Two barriers are located on both sides of the upper side of the light sensing area of the CMOS chip; A substrate is placed above the CMOS chip, wherein the substrate has a through hole, and the hole corresponds to the position of the contact of the CMOS chip and the light sensing area, so that light can be irradiated through the hole The light-sensing area, and a contact is formed above the substrate; the contact of the substrate and the contact of the CMOS chip are connected by a wire through the hole of the substrate; A glass is located above the light sensing area of the CMOS chip; and Wherein the plate hole of the substrate forms a second package structure by applying glue to seal the plate hole; wherein the second package structure does not cover the glass, so that the glass is exposed, so external light can directly pass through the plate hole. The glass irradiates the CMOS chip; wherein the contact above the substrate has a conductive ball. The package structure with FOWBCSP CMOS chip type as described in item 1 of the scope of patent application, wherein the glass is placed between the two barriers. The package structure with FOWBCSP CMOS chip type as described in the first item of the scope of patent application, wherein the glass is placed on the upper ends of the two barriers, and a gap is formed between the glass and the CMOS chip. The package structure with FOWBCSP CMOS chip type as described in item 1 or 2 or 3 of the scope of patent application further includes a first package structure located below and on the side of the CMOS chip. As described in item 1, 2 or 3 of the scope of patent application, the package structure with FOWBCSP CMOS chip type, wherein the conductive ball is a solder ball or a solder ball. The package structure with FOWBCSP CMOS chip type as described in item 1 or 2 or 3 of the scope of patent application also includes a circuit board on the top of the substrate, wherein the conductive ball on the contact on the top of the substrate is connected To the contact point on the circuit board to form electrical communication; wherein a through hole is formed on the circuit board, and the position of the hole corresponds to the glass, so that external light can penetrate the glass through the hole Irradiate the CMOS wafer. The package structure with FOWBCSP CMOS chip type as described in item 6 of the scope of patent application, wherein the circuit board is a soft board. A package structure with FOWBCSP CMOS chip type, including: A CMOS chip, the upper part of the CMOS chip includes contacts and a light sensing area; Two barriers, located on both sides of the upper side of the light sensing area of the CMOS chip; A substrate is placed above the CMOS chip, wherein the substrate has a penetrating plate hole corresponding to the position of the light sensing area and the two barriers of the CMOS chip, so that light can pass through the The plate hole illuminates the light sensing area; wherein an upper contact is formed above the substrate, and a lower contact is formed under the substrate; wherein the upper contact is connected to a corresponding lower contact via an inner wire located inside the substrate Point; the substrate is connected to the corresponding contact on the CMOS chip via the lower contact; wherein the upper contact above the substrate has a conductive ball; and A glass is placed on the upper ends of the two barriers, and a gap is formed between the glass and the CMOS chip; therefore, external light can directly illuminate the CMOS chip through the glass. The package structure with FOWBCSP CMOS chip type described in item 8 of the scope of patent application further includes a first package structure located below and on the side of the CMOS chip. As described in item 8 of the scope of patent application, the package structure with FOWBCSP CMOS chip type, wherein the conductive ball is a solder ball or a solder ball. The package structure with FOWBCSP CMOS chip type as described in item 8 of the scope of patent application also includes a circuit board located above the substrate, wherein the conductive balls on the contacts above the substrate are connected to the circuit board The circuit board is formed with a through hole, and the position of the hole corresponds to the glass, so that external light can penetrate the glass through the hole and irradiate the CMOS chip . The package structure with FOWBCSP CMOS chip type as described in item 11 of the scope of patent application, wherein the circuit board is a soft board. A package structure with FOWBCSP CMOS chip type, including: A CMOS chip, the upper part of the CMOS chip includes contacts and a light sensing area; Two barriers, located on both sides of the upper side of the light sensing area of the CMOS chip; A substrate is placed above the CMOS chip, wherein the substrate has a penetrating plate hole corresponding to the position of the light sensing area and the two barriers of the CMOS chip, so that light can pass through the The plate hole illuminates the light sensing area; wherein a lower contact is formed under the substrate; the substrate is connected to the corresponding contact on the CMOS chip through the lower contact; wherein at least one side of the substrate corresponds to the at least one side The lower contact extends to the outside of the CMOS chip; and A glass is placed on the upper ends of the two barriers, and a gap is formed between the glass and the CMOS chip; therefore, external light can directly illuminate the CMOS chip through the glass. The package structure with FOWBCSP CMOS chip type as described in item 13 of the scope of patent application further includes a first package structure located below and on the side of the CMOS chip. The package structure with FOWBCSP CMOS chip type as described in item 13 of the scope of patent application further includes a circuit board located below the substrate, wherein the lower contacts on the substrate extending to the outside of the CMOS chip are connected to the circuit The contacts on the board make the circuit board and the CMOS Electrical communication is formed between the wafers. The package structure with FOWBCSP CMOS chip type as described in item 15 of the scope of patent application, wherein the circuit board is a soft board.

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