TWI800885B - 半導體結構的製作方法 - Google Patents

半導體結構的製作方法 Download PDF

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Publication number
TWI800885B
TWI800885B TW110128983A TW110128983A TWI800885B TW I800885 B TWI800885 B TW I800885B TW 110128983 A TW110128983 A TW 110128983A TW 110128983 A TW110128983 A TW 110128983A TW I800885 B TWI800885 B TW I800885B
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TW
Taiwan
Prior art keywords
semiconductor structure
fabricating semiconductor
fabricating
semiconductor
Prior art date
Application number
TW110128983A
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English (en)
Other versions
TW202213456A (zh
Inventor
陳濬凱
陳哲明
李資良
Original Assignee
台灣積體電路製造股份有限公司
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Publication of TW202213456A publication Critical patent/TW202213456A/zh
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Publication of TWI800885B publication Critical patent/TWI800885B/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/101—Forming openings in dielectrics

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW110128983A 2020-09-29 2021-08-05 半導體結構的製作方法 TWI800885B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US202063084823P 2020-09-29 2020-09-29
US63/084,823 2020-09-29
US17/332,553 2021-05-27
US17/332,553 US20220102143A1 (en) 2020-09-29 2021-05-27 Metal Hard Masks for Reducing Line Bending

Publications (2)

Publication Number Publication Date
TW202213456A TW202213456A (zh) 2022-04-01
TWI800885B true TWI800885B (zh) 2023-05-01

Family

ID=80233361

Family Applications (1)

Application Number Title Priority Date Filing Date
TW110128983A TWI800885B (zh) 2020-09-29 2021-08-05 半導體結構的製作方法

Country Status (5)

Country Link
US (1) US20220102143A1 (zh)
KR (1) KR102696330B1 (zh)
CN (1) CN114068402A (zh)
DE (1) DE102021114103A1 (zh)
TW (1) TWI800885B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW202403845A (zh) * 2022-06-06 2024-01-16 美商應用材料股份有限公司 用於dram電容器模具圖案化之碳化釕

Citations (3)

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TW200841391A (en) * 2007-04-11 2008-10-16 United Microelectronics Corp Multi cap layer and manufacturing method thereof
US20090176378A1 (en) * 2005-06-22 2009-07-09 United Microelectronics Corp. Manufacturing method of dual damascene structure
TW202018764A (zh) * 2018-10-31 2020-05-16 台灣積體電路製造股份有限公司 積體電路結構的形成方法

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US8247332B2 (en) * 2009-12-04 2012-08-21 Novellus Systems, Inc. Hardmask materials
US7871909B1 (en) * 2010-01-19 2011-01-18 Sandisk 3D Llc Methods of using single spacer to triple line/space frequency
US8901016B2 (en) * 2010-12-28 2014-12-02 Asm Japan K.K. Method of forming metal oxide hardmask
JP6061610B2 (ja) * 2012-10-18 2017-01-18 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US8987142B2 (en) * 2013-01-09 2015-03-24 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-patterning method and device formed by the method
US9454631B2 (en) * 2014-05-23 2016-09-27 International Business Machines Corporation Stitch-derived via structures and methods of generating the same
KR102269055B1 (ko) 2014-07-16 2021-06-28 삼성전자주식회사 반도체 소자의 제조 방법
US9679804B1 (en) * 2016-07-29 2017-06-13 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-patterning to form vias with straight profiles
US10026647B2 (en) * 2016-12-12 2018-07-17 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-metal fill with self-align patterning
US10340141B2 (en) * 2017-04-28 2019-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Patterning method for semiconductor device and structures resulting therefrom
US10475700B2 (en) * 2017-08-31 2019-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Etching to reduce line wiggling
US10529617B2 (en) * 2017-09-29 2020-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Metal routing with flexible space formed using self-aligned spacer patterning
US10636667B2 (en) * 2017-11-21 2020-04-28 Taiwan Semiconductor Manufacturing Company Ltd. Method for manufacturing semiconductor devices and structures thereof
US10699943B2 (en) * 2018-04-30 2020-06-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming contacts in a semiconductor device
US10867804B2 (en) * 2018-06-29 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Patterning method for semiconductor device and structures resulting therefrom
EP3599637B1 (en) * 2018-07-23 2023-07-12 IMEC vzw A method for forming a multi-level interconnect structure
US20200052196A1 (en) * 2018-08-07 2020-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Avoiding Oxygen Plasma Damage During Hard Mask Etching in Magnetic Tunnel Junction (MTJ) Fabrication Process
KR20200100555A (ko) * 2019-02-18 2020-08-26 도쿄엘렉트론가부시키가이샤 에칭 방법
US20220102212A1 (en) * 2020-09-30 2022-03-31 Taiwan Semiconductor Manufacturing Co., Ltd. Self-Aligned Via Formation Using Spacers

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090176378A1 (en) * 2005-06-22 2009-07-09 United Microelectronics Corp. Manufacturing method of dual damascene structure
TW200841391A (en) * 2007-04-11 2008-10-16 United Microelectronics Corp Multi cap layer and manufacturing method thereof
TW202018764A (zh) * 2018-10-31 2020-05-16 台灣積體電路製造股份有限公司 積體電路結構的形成方法

Also Published As

Publication number Publication date
KR102696330B1 (ko) 2024-08-19
DE102021114103A1 (de) 2022-03-31
KR20220043851A (ko) 2022-04-05
US20220102143A1 (en) 2022-03-31
CN114068402A (zh) 2022-02-18
TW202213456A (zh) 2022-04-01

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