TWI799642B - 應用處理器、系統單晶片以及操作記憶體管理單元之方法 - Google Patents

應用處理器、系統單晶片以及操作記憶體管理單元之方法 Download PDF

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Publication number
TWI799642B
TWI799642B TW108132006A TW108132006A TWI799642B TW I799642 B TWI799642 B TW I799642B TW 108132006 A TW108132006 A TW 108132006A TW 108132006 A TW108132006 A TW 108132006A TW I799642 B TWI799642 B TW I799642B
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TW
Taiwan
Prior art keywords
chip
management unit
memory management
application processor
operating memory
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TW108132006A
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English (en)
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TW202044042A (zh
Inventor
朴城範
莫紐 希德
崔周熙
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南韓商三星電子股份有限公司
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Publication of TW202044042A publication Critical patent/TW202044042A/zh
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Publication of TWI799642B publication Critical patent/TWI799642B/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0808—Multiuser, multiprocessor or multiprocessing cache systems with cache invalidating means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0871—Allocation or management of cache space
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]
    • G06F2212/683—Invalidation

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
TW108132006A 2019-05-15 2019-09-05 應用處理器、系統單晶片以及操作記憶體管理單元之方法 TWI799642B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US16/413,034 2019-05-15
US16/413,034 US11216385B2 (en) 2019-05-15 2019-05-15 Application processor, system-on chip and method of operating memory management unit
KR1020190062943A KR20200133165A (ko) 2019-05-15 2019-05-29 어플리케이션 프로세서, 시스템-온 칩 및 메모리 관리 유닛의 동작 방법
KR10-2019-0062943 2019-05-29

Publications (2)

Publication Number Publication Date
TW202044042A TW202044042A (zh) 2020-12-01
TWI799642B true TWI799642B (zh) 2023-04-21

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TW108132006A TWI799642B (zh) 2019-05-15 2019-09-05 應用處理器、系統單晶片以及操作記憶體管理單元之方法

Country Status (3)

Country Link
US (1) US11216385B2 (zh)
KR (1) KR20200133165A (zh)
TW (1) TWI799642B (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11755731B2 (en) 2020-07-23 2023-09-12 Ventana Micro Systems Inc. Processor that prevents speculative execution across translation context change boundaries to mitigate side channel attacks
US11755732B2 (en) 2020-07-23 2023-09-12 Ventana Micro Systems Inc. Microprocessor that conditions store-to-load forwarding on circumstances associated with a translation context update
US11803637B2 (en) * 2020-07-23 2023-10-31 Ventana Micro Systems Inc. Microprocessor that prevents store-to-load forwarding between different translation contexts
US11803638B2 (en) 2020-07-23 2023-10-31 Ventana Micro Systems Inc. Microprocessor core with a store dependence predictor accessed using a translation context
CN115344245A (zh) * 2021-05-14 2022-11-15 瑞昱半导体股份有限公司 加速比较函式执行的方法及加速比较函式执行的系统
KR102480300B1 (ko) * 2022-05-25 2022-12-23 리벨리온 주식회사 뉴럴 프로세싱 장치 및 그의 잡 스케쥴링 방법
KR20230164549A (ko) 2022-05-25 2023-12-04 리벨리온 주식회사 뉴럴 프로세싱 장치 및 그의 잡 스케쥴링 방법

Citations (3)

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US20160140048A1 (en) * 2014-11-14 2016-05-19 Cavium, Inc. Caching tlb translations using a unified page table walker cache
US9779028B1 (en) * 2016-04-01 2017-10-03 Cavium, Inc. Managing translation invalidation
TW201804328A (zh) * 2016-07-26 2018-02-01 三星電子股份有限公司 記憶體系統、其處理系統以及操作記憶體堆疊的方法

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US5282274A (en) 1990-05-24 1994-01-25 International Business Machines Corporation Translation of multiple virtual pages upon a TLB miss
US5222222A (en) 1990-12-18 1993-06-22 Sun Microsystems, Inc. Apparatus and method for a space saving translation lookaside buffer for content addressable memory
US6157986A (en) 1997-12-16 2000-12-05 Advanced Micro Devices, Inc. Fast linear tag validation unit for use in microprocessor
EP1182559B1 (en) 2000-08-21 2009-01-21 Texas Instruments Incorporated Improved microprocessor
US7366829B1 (en) 2004-06-30 2008-04-29 Sun Microsystems, Inc. TLB tag parity checking without CAM read
US8522253B1 (en) 2005-03-31 2013-08-27 Guillermo Rozas Hardware support for virtual machine and operating system context switching in translation lookaside buffers and virtually tagged caches
US9191441B2 (en) 2013-03-15 2015-11-17 International Business Machines Corporation Cell fabric hardware acceleration
US9436616B2 (en) 2013-05-06 2016-09-06 Qualcomm Incorporated Multi-core page table sets of attribute fields
US9323715B2 (en) * 2013-11-14 2016-04-26 Cavium, Inc. Method and apparatus to represent a processor context with fewer bits
US9703722B2 (en) 2014-11-14 2017-07-11 Cavium, Inc. Method and system for compressing data for a translation look aside buffer (TLB)
US10095620B2 (en) 2016-06-29 2018-10-09 International Business Machines Corporation Computer system including synchronous input/output and hardware assisted purge of address translation cache entries of synchronous input/output transactions

Patent Citations (3)

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Publication number Priority date Publication date Assignee Title
US20160140048A1 (en) * 2014-11-14 2016-05-19 Cavium, Inc. Caching tlb translations using a unified page table walker cache
US9779028B1 (en) * 2016-04-01 2017-10-03 Cavium, Inc. Managing translation invalidation
TW201804328A (zh) * 2016-07-26 2018-02-01 三星電子股份有限公司 記憶體系統、其處理系統以及操作記憶體堆疊的方法

Also Published As

Publication number Publication date
TW202044042A (zh) 2020-12-01
US20200364152A1 (en) 2020-11-19
KR20200133165A (ko) 2020-11-26
US11216385B2 (en) 2022-01-04

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