TWI799296B - Method for manufacutring semiconductor structure - Google Patents

Abstract

The present disclosure provides a method of manufacturing a semiconductor structure. The method includes several operations. A substrate including a device region and a scribe line region is provided. A first layer is formed over the substrate. A first photoluminescent layer is formed over the first layer in the scribe line region. The first layer and the first photoluminescent layer are patterned to form a first pattern in the scribe line region. A first patterned mask layer is formed over a second layer. An alignment of the first patterned mask layer and the first pattern is detected. A pattern of the first patterned mask layer is transferred to the second layer to form a second pattern in the scribe line region.

Description

Fabrication method of semiconductor structure

This application claims priority to US Patent Application Nos. 17/679,311 and 17/679,515 (ie, the priority date is "February 24, 2022"), the contents of which are incorporated herein by reference in their entirety.

The disclosure relates to a method for preparing a semiconductor structure. In particular, it relates to a method of manufacturing a semiconductor structure with overlay marks.

With the development of the semiconductor industry, it is becoming more and more important to reduce the overlay error in multiple photoresist patterns and multiple underlying patterns during the lithography step. Correctly measuring multiple overlay errors becomes more difficult due to various factors such as the asymmetric shape of the measurement structure, so a new overlay marker and a method that can more accurately determine overlay errors are needed.

The above "prior art" description is only to provide background technology, and does not acknowledge that the above "prior art" description discloses the subject of this disclosure, and does not constitute the prior art of this disclosure, and any description of the above "prior art" shall not form part of this case.

An embodiment of the present disclosure provides a method for fabricating a semiconductor structure. The preparation method comprises forming a first pattern on a substrate; forming a photoluminescent layer on the first pattern forming an intermediate layer on the photoluminescent layer and the substrate; forming a patterned mask layer on the intermediate layer; and detecting an alignment of the patterned mask layer and the first pattern.

In some embodiments, the manufacturing method further includes converting the patterned mask layer into the intermediate layer.

In some embodiments, the photoluminescent layer includes fluorescent powder, quantum dots, a plurality of nanomaterials or a combination thereof.

In some embodiments, the nanomaterials include Gd ₂ O ₂ S:R, and R represents Eu ³⁺ , Pr ³⁺ or Tb ³⁺ .

In some embodiments, the fabrication technique of the photoluminescent layer includes one or more of deposition, sputtering and coating.

In some embodiments, from a top view, the photoluminescent layer is exposed through the patterned mask layer.

In some embodiments, viewed from the top view, the first pattern is surrounded by at least a portion of the patterned mask layer.

In some embodiments, viewed from the top view, the first pattern is at least partially surrounded by the patterned mask layer.

In some embodiments, detecting the alignment includes: providing a first optical signal on the photoluminescent layer; receiving a second optical signal from the photoluminescent layer; filtering the second optical signal; The second optical signal is converted into a first electrical signal.

In some embodiments, detecting the alignment includes: providing a third optical signal on the patterned mask layer; receiving a fourth optical signal from the patterned mask layer; and the fourth optical signal converted into a second electrical signal.

In some embodiments, the first electrical signal and the second electrical signal are processed to display The alignment of the patterned mask layer and the photoluminescent layer is shown.

In some embodiments, the intermediate layer includes one or more dielectric materials.

In some embodiments, the first pattern is formed adjacent to a capacitor.

In some embodiments, the capacitor is formed at the same height as the first pattern.

In some embodiments, a height of the capacitor is greater than a thickness of the first pattern.

In some embodiments, a thickness of a first portion of the intermediate layer on the capacitor is smaller than a thickness of a second portion of the intermediate layer on the first pattern.

In some embodiments, forming the patterned mask layer includes: disposing a photoresist layer on the intermediate layer; and removing some parts of the photoresist layer to form the patterned mask layer.

In some embodiments, a thickness of a first portion of the photoresist layer on the capacitor is smaller than a thickness of a second portion of the photoresist layer on the first pattern.

In some embodiments, a distance between a top of the patterned mask layer and a top of the first pattern is greater than 5.7 microns.

An embodiment of the present disclosure provides a system for fabricating a semiconductor structure. The system includes a fabrication apparatus configured to perform steps to form a layer on a wafer; an exposure apparatus configured to perform patterning steps to form a pattern of the layer; and an alignment apparatus, configured to detect an alignment of two overlay marks at different heights on the wafer. The alignment apparatus includes: a stage configured to support the wafer; an optical element configured to emit a radiation to excite a photoluminescent material of one of the two stacked markers; an optical filter configured to to receive and filter a radiation emitted from the photoluminescent material; and an optical detector, configured to convert an optical signal filtered by the filter into an electrical signal.

In some embodiments, the alignment apparatus is configured to generate an alignment result of the two stacked alignment marks.

In some embodiments, the alignment apparatus further includes a controller electrically or wirelessly connected to the optical element and the optical detector and configured to process the electrical signal from the optical detector.

In some embodiments, the alignment device further includes an interface electrically connected to the controller and configured to display a result of the electrical signal after being processed by the processor.

In some embodiments, the filter includes a grating structure for passing the radiation in.

In some embodiments, the filter has a filtering range of wavelengths that differs from a range of wavelengths of radiation emitted from the optical element.

In some embodiments, the optical detector is electrically or physically connected to the filter.

In some embodiments, the optical element emits the radiation having a wavelength in a range of: near infrared (NIR), far infrared (FIR), ultraviolet (UV), near ultraviolet (NUV), far Ultraviolet (FUV), green, yellow, red, or combinations thereof.

In some embodiments, the system further includes a network wirelessly or electrically connected to the fabrication equipment, the exposure equipment and the alignment equipment.

In some embodiments, the system further includes another controller electrically or wirelessly connected to the fabrication equipment, the exposure equipment, and the alignment equipment.

In some embodiments, the controller is configured to generate an alignment result based on the electrical signal from the optical detector.

An embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure includes: a capacitor disposed on a substrate; an overlay mark disposed adjacent to the capacitor and at a same height as the capacitor; a photoluminescent layer disposed on the overlay mark; and An intermediate layer is arranged on the capacitor and the photoluminescent layer.

In some embodiments, the overlay mark contacts the capacitor.

In some embodiments, a height of the capacitor is greater than a thickness of the overlay mark.

In some embodiments, the photoluminescent layer includes phosphor, quantum dots, Gd ₂ O ₂ S:R or a combination thereof, and R represents Eu ³⁺ , Pr ³⁺ or Tb ³⁺ .

In some embodiments, a thickness of a first portion of the intermediate layer on the capacitor is less than a thickness of a second portion of the intermediate layer on the photoluminescent layer.

The technical features and advantages of the present disclosure have been broadly summarized above, so that the following detailed description of the present disclosure can be better understood. Other technical features and advantages constituting the subject matter of the claims of the present disclosure will be described below. Those skilled in the art of the present disclosure should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the technical field to which the disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the disclosure defined by the appended claims.

10:Wafer

20: Overlay Mark

21: Overlay Mark

21a: Photoluminescent layer

22: Overlay Mark

23: The third pattern

30: cutting line area

40: Component area

51: The first optical signal

52: Second optical signal

53: The third optical signal

54: The fourth optical signal

100: base

101: Electronic components

141: middle layer

142: middle layer

311: mask layer

312: Patterned mask layer

313: upper surface

700: Semiconductor Manufacturing Systems

710: Manufacturing equipment

720-1~720-N: manufacturing equipment

730: Exposure equipment

740: Alignment equipment

741: platform

742:Optical components

743: detection unit

743a: Filter

743b: Optical detector

743c: Grating structures

744:Controller

745: interface

750: network

760: controller

A: point

H1: height

H2: Thickness

H3: Thickness

H4: Thickness

H5: Thickness

H6: Thickness

H7: Distance

H8: Distance

H9: Distance

H10: Thickness

S1: Preparation method

S11: step

S12: step

S13: step

S14: step

S15: step

S151: step

S152: step

S153: step

S154: step

S155: step

S156: step

S157: step

S158: step

A more complete understanding of the present disclosure can be obtained by reference to the detailed description and claims. The disclosure should also be understood in association with drawing element numbers that represent like elements throughout the description.

FIG. 1 is a schematic diagram illustrating a wafer according to some embodiments of the present disclosure.

FIG. 2 is an enlarged schematic diagram illustrating some embodiments of the present disclosure, such as the dashed area shown in FIG. 1 .

3-4 are schematic top views illustrating a plurality of overlay marks at different heights according to some embodiments of the present disclosure.

FIG. 5 is a schematic cross-sectional view illustrating some embodiments of the present disclosure along the section line AA' in FIG. 3 or the section line BB' in FIG. 4 .

FIG. 6 is a schematic cross-sectional view illustrating some embodiments of the present disclosure along the section line AA' in FIG. 3 or the section line BB' in FIG. 4 .

7 is a schematic cross-sectional view illustrating some embodiments of the present disclosure along the section line AA' of FIG. 3 or the section line BB' of FIG. 4 .

FIG. 8 is a schematic flow diagram illustrating a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.

FIG. 9 is a schematic flow diagram illustrating a step of the preparation method in FIG. 8 of some embodiments of the present disclosure.

10-20 are schematic cross-sectional views illustrating intermediate stages in the fabrication of semiconductor structures according to some embodiments of the present disclosure.

FIG. 21 is a block diagram illustrating a semiconductor manufacturing system according to some embodiments of the present disclosure.

FIG. 22 is a schematic diagram illustrating an alignment device of the semiconductor manufacturing system shown in FIG. 21 according to some embodiments of the present disclosure.

FIG. 23 is a schematic diagram illustrating a detection unit of the alignment device shown in FIG. 22 according to some embodiments of the present disclosure.

Embodiments or examples of the present disclosure shown in the drawings will now be described using specific language. It should be understood that the scope of the present disclosure is not intended to be limited thereby. Any of the described embodiments Modifications or improvements, and any further applications of the principles described in this document, would occur as would normally occur to one of ordinary skill in the art. Element numbers may be repeated throughout the embodiments, but this does not necessarily mean that features of one embodiment apply to another, even if they share the same element number.

It should be understood that although the terms "first", "second", "third" etc. may be used herein to describe various elements, components, regions, layers and/or sections, These elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, a "first element", "component", "region", "layer" or "section" discussed below may be referred to as a second device , component, region, layer or section without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will be further understood that when the terms "comprises" and/or "comprising" are used in this specification, these terms specify the stated features, integers, steps, operations, elements, and/or components. Presence, but not excluding the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups of the above.

Please refer to FIG. 1 and FIG. 2 , FIG. 1 is a schematic top view illustrating a wafer 10 according to some embodiments of the present disclosure, and FIG. 2 is an enlarged schematic diagram of the dotted area shown in FIG. 1 .

As shown in FIGS. 1 and 2 , the wafer 10 includes a plurality of device regions 40 and a dicing line region 30 , and the dicing line region 30 surrounds each device region 40 . The device regions 40 can be separated by the dicing line region 30 . In some embodiments, a plurality of device regions 40 define a plurality of dies. In some embodiments, the dicing line region 30 defines a plurality of dicing lines between the plurality of dies. For ease of description, the device regions 40 can also be regarded as a plurality of crystal grains 40 , and the dicing line region 30 can also be regarded as a plurality of dicing lines 30 . The wafer 10 can be diced into a plurality of dies 40 along the dicing lines 30 . Each die 40 may include a plurality of semiconductor devices, and the semiconductor devices may include a plurality of active devices and/or a plurality of passive devices. The active components may include a memory die (such as a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (such as a power management integrated circuit (PMIC) die), a logic die (such as a system-on-chip (SoC), a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP), a microcontroller, etc.), a radio frequency (RF) die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (such as a digital signal processing (DSP) die), A front-end die (such as an analog front-end (AFE) die) or other active devices. The passive element may include a capacitor, a resistor, an inductor, a fuse or other passive elements.

In some embodiments, a stack of markers 20 may be provided on the cut lines 30 . In some embodiments, the overlay mark 20 may be disposed at a corner of an edge of each die 40 on one of the dicing lines 30 . In some embodiments, overlay marks 20 may be disposed inside the dies 40 . The overlay marks 20 can be used to determine whether a current layer (or an upper layer) is accurately aligned with a previous layer (or lower layer) during a semiconductor manufacturing process, for example, by identifying a photoresist whether an opening of the layer or a pattern of the photoresist layer is aligned with the front layer. The front layer may be disposed at a vertical plane different from a vertical plane of the current layer. In some embodiments, the current layer is disposed at a height higher than the front layer.

3 and 4 illustrate the alignment of an alignment mark 21 of the front layer and an alignment mark 22 of the current layer on a substrate 100 according to different embodiments of the present disclosure. From Figure 3 or Figure 4 From the top view shown, the overlay mark 22 can surround or enclose the overlay mark 21 . In some embodiments, from the top view as shown in FIG. 3 , the overlay mark 21 is surrounded by a square. In some embodiments, as shown in FIG. 4 , the overlay mark 21 includes a plurality of parts. In some embodiments, the portions of overlay marks 21 are spaced apart from each other. Viewed from a top view, the overlay mark 21 may include at least an x-axis alignment portion and a y-axis alignment portion to represent alignment with the overlay mark 22 along the x-axis and alignment with the overlay mark 22 along the y-axis. 22 alignment. In some embodiments, as shown in FIG. 4 , the overlay mark includes some portions along the x-axis direction and some portions along the y-axis direction.

In some embodiments, wafer 10 includes substrate 100 . The substrate 100 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. Substrate 100 may include an elemental semiconductor including silicon or germanium in a single crystal form, a polycrystalline silicon form, or an amorphous silicon form; a compound semiconductor material including at least one of the following: silicon carbide, gallium arsenide, phosphide gallium, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor material including at least one of the following: SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; or a combination thereof. In some embodiments, the alloy semiconductor substrate may be a SiGe alloy having a graded Si:Ge character, with the composition of Si and Ge changing from a ratio at one location to another in the graded Si:Ge character. Another ratio at one location. In other embodiments, the SiGe alloy is formed on a silicon substrate. In some embodiments, the SiGe alloy can be mechanically strained by another material in contact with the SiGe alloy. In some embodiments, the substrate 100 may have a multilayer structure, or the substrate 100 may include a multilayer compound semiconductor structure. In some embodiments, the substrate 100 includes a plurality of semiconductor elements, a plurality of electronic components, a plurality of electronic components, or a combination thereof. In some embodiments, the substrate 100 includes a plurality of transistors or a plurality of functional units of the plurality of transistors.

FIG. 5 is a schematic cross-sectional view illustrating some embodiments of the present disclosure along the section line AA' in FIG. 3 or the section line BB' in FIG. 4 . As shown in FIG. 5 , an overlay mark 21 may be disposed on the substrate 100 . The overlay mark 21 may indicate a position of a pattern disposed in the front layer or the lower layer in the middle layer 141 . A photoluminescent layer 21 a may be disposed on top of the overlay mark 21 . In some embodiments, the photoluminescent layer 21 a is a layer formed on the overlay mark 21 . In some embodiments, the photoluminescent layer 21a is a sub-layer formed at the top of the overlay mark 21 . The photoluminescent layer 21 a includes a photoluminescent material or a fluorescent material, and provides a better view of the overlay mark 21 , allowing easy inspection of the alignment between the overlay mark 21 and the overlay mark 22 . In some embodiments, the photoluminescent layer 21a includes one or more inorganic materials. In some embodiments, the photoluminescent layer 21a includes one or more of the following: phosphor, quantum dots, and a plurality of nanomaterials. In some embodiments, the nanomaterials include Gd ₂ O ₂ S:R, wherein R represents Eu ³⁺ , Pr ³⁺ or Tb ³⁺ .

In some embodiments, the overlay mark 21 may include the same material as an insulating structure. In some embodiments, the overlay mark 21 may be disposed at the same height as the insulating structure. For example, the isolation structure may include a shallow trench isolation (STI), a field oxide (FOX) feature, a local oxide of silicon (LOCOS) feature, and/or other suitable isolation elements. The insulating structure may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate (FSG), a low-k dielectric material, combinations thereof, and/or other suitable materials .

In some embodiments, the overlay mark 21 may comprise the same material as a gate structure. For example, the gate structure is sacrificial, such as a dummy gate structure. In some embodiments, the overlay mark 21 may be disposed at the same height as the gate structure. In some embodiments, the overlay mark 21 may include a dielectric layer including the same material as a gate dielectric layer, and a conductive layer including the same material as a gate electrode layer. of a material.

In some embodiments, the gate dielectric layer may include silicon oxide (SiO _x ), silicon nitride ( _Six N _y ), silicon oxynitride (SiON), or a combination thereof. In some embodiments, the gate dielectric layer may include a dielectric material, such as a high-k dielectric material. High-k dielectric materials may have a dielectric constant (k value) greater than 4. High dielectric constant dielectric materials can include hafnium oxide (HfO ₂ ), zirconium oxide (ZrO ₂ ), lanthanum oxide (La ₂ O ₃ ), yttrium oxide (Y ₂ O ₃ ), aluminum oxide (Al ₂ O ₃ ) , titanium oxide (TiO ₂ ) or other applicable materials. Other suitable materials are within the contemplation of the present disclosure.

In some embodiments, the gate electrode layer may include a polysilicon layer. In some embodiments, the gate electrode layer may include a conductive material such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta) or other applicable materials. In some embodiments, the gate dielectric layer may include a work function layer. The work function layer includes a metal material, and the metal material includes N work function metal or P work function metal. The N work function metals include tungsten (W), copper (Cu), titanium (Ti), silver (Ag), aluminum (Al), titanium aluminum alloy (TiAl), titanium aluminum nitride (WiAlN), tantalum carbide (TaC ), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr) or combinations thereof. P work function metals include titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), ruthenium (Ru), or combinations thereof. Other suitable materials are within the contemplation of the present disclosure. Fabrication techniques of the gate electrode layer may include low pressure chemical vapor deposition (LPCVD) and plasma enhanced CVD (PECVD).

In some embodiments, overlay mark 21 may comprise the same material as a conductive via that may be disposed on a conductive trace, such as the first metal layer (M1 layer). In some embodiments, the overlay mark 21 may comprise the same material as the conductive trace, and the conductive trace may be disposed in a dielectric layer and electrically connected to the conductive via. In some embodiments, the conductive trace and the conductive via are disposed in an interconnect structure, The interconnect structure is disposed on the transistors of the substrate 100 . In some embodiments, the conductive trace and the conductive via are disposed in a redistribution layer (RDL) disposed on the interconnect structure on the substrate 100 . In these embodiments, the overlay mark 21 may include a barrier layer and a conductive layer, and the conductive layer is surrounded by the barrier layer. The barrier layer may comprise metal nitride or other suitable materials. The conductive layer may include metals such as W, Ta, Ti, Ni, Co, Hf, Ru, Zr, Zn, Fe, Sn, Al, Cu, Ag, Mo, Cr, alloys or other suitable materials. In these embodiments, the fabrication technique of the overlay mark 21 may include suitable deposition processes, such as sputtering and physical vapor deposition (PVD), for example.

The intermediate layer 14 may include isolation materials such as silicon oxide or silicon nitride. In some embodiments, the intermediate layer 141 may include a conductive material, such as a metal or an alloy. In some embodiments, the fabrication technique of the intermediate layer 141 may include a suitable film-forming method, such as chemical vapor deposition (CVD), atomic layer deposition (ALD) or physical vapor deposition (PVD). After the intermediate layer 141 is formed, a thermal process such as rapid thermal annealing may be performed. In some embodiments, a planarization process such as a chemical mechanical polishing (CMP) process is performed. In some embodiments, a removal process such as an etch process may be performed. For example, the etching process includes a dry etching process or a wet etching process. It should be understood that for additional embodiments of the method, additional steps may be provided before, during, and after the processes described above, and that some of the steps described above may be replaced or eliminated. The order of the steps/processes is interchangeable.

In some embodiments, overlay marks 22 are formed on the intermediate layer 141 . In some embodiments, overlay marks 22 physically contact intermediate layer 141 . Overlay marks 22 may indicate an alignment of the current layer (or an upper layer) with the middle layer 141 . In some embodiments, overlay mark 22 is a portion of the current plane in cut line 30 . A material of the overlay mark 22 may be similar or identical to that of the overlay mark 21 , and repeated descriptions thereof are omitted herein. In some embodiments, the current layer is directly on the intermediate layer 141 , while the overlay mark 22 is on the intermediate layer 141 . In some embodiments, overlay marks 22 are designated to show an alignment of the upper layer with the middle layer 141 . In some embodiments, the upper layer is disposed on and spaced apart from the middle layer 141 .

FIG. 6 is a schematic cross-sectional view illustrating some embodiments of the present disclosure along the section line AA' in FIG. 3 or the section line BB' in FIG. 4 . The overlay mark 21 shown in FIG. 6 is similar to the overlay mark 21 shown in FIG. 5 except that the photoluminescent layer 21 a is at a bottom of the overlay mark 21 . In some embodiments, the photoluminescent layer 21 is a layer formed prior to the formation of the overlay marks 21 . In some embodiments, the photoluminescent layer 21a is considered a sublayer of the overlay mark 21 .

7 is a schematic cross-sectional view illustrating another embodiment of the present disclosure along the section line AA' of FIG. 3 or the section line BB' of FIG. 4 . In some embodiments, an intermediate layer 142 is disposed on the overlay mark 21 and the intermediate layer 141 . In some embodiments, the intermediate layer 142 physically contacts the overlay mark 21 and the intermediate layer 141 . A material and/or a manufacturing method of the middle layer 142 may be similar or identical to that of the middle layer 141 , and repeated descriptions thereof are omitted herein. In some embodiments, overlay marks 22 are disposed on intermediate layer 142 . The overlay mark 22 can be separated from the middle layer 141 by the middle layer 142 . The overlay mark 22 can be disposed on one or more layers on the overlay mark 21 and the intermediate layer 141 , with any number of intermediate layers 142 disposed therebetween; the present disclosure is not limited to only one intermediate layer 142 .

FIG. 8 is a schematic flowchart illustrating a method S1 for fabricating a semiconductor structure according to some embodiments of the present disclosure. The preparation method S1 includes: (S11) forming a first pattern on a substrate; (S12) forming a photoluminescent layer on the first pattern; (S13) forming an intermediate layer between the photoluminescent layer and the substrate (S14) forming a patterned mask layer on the intermediate layer; and (S15) detecting an alignment of the patterned mask layer and the first pattern.

FIG. 9 is a schematic flowchart illustrating step S15 of some embodiments of the present disclosure. In some embodiments, step S15 includes several steps: (S151) providing a first optical signal at the (S152) receiving a second optical signal from the photoluminescent layer; (S153) filtering the second optical signal; (S154) converting the second optical signal into a first electrical signal; ( S155) providing a third optical signal on the patterned mask layer; (S156) receiving a fourth optical signal from the patterned mask layer; (S157) converting the fourth optical signal into a second electrical signal ; (158) processing the first electrical signal and the second electrical signal to determine the alignment of the patterned mask layer and the first pattern.

僅簡短地在文中進行描述。因此，在文中所描述的各式不同方面的範圍內，其他之實現是可能的。 The preparation method S1 includes multiple operations and multiple steps, and the description and illustration are not considered to limit the sequence of these operations and these steps. It should be understood that the steps of preparation method S1 may be reconfigured or otherwise modified within the scope of a variety of different aspects. Several additional processes may be provided before, during and after preparation method S1, and some other processes

Only briefly described in the text. Thus, other implementations are possible within the scope of the various aspects described herein.

FIG. 10 is a schematic cross-sectional view of a stage of the preparation method S1 according to some embodiments of the present disclosure. In step S11 , a substrate 100 is disposed on a wafer 10 , and a first pattern 21 is formed on the substrate 100 . In some embodiments, the first pattern 21 is formed in a scribe line region 30 . In some embodiments, the first pattern 21 is formed in a device region 40 . One or more electronic components 101 may be formed on the substrate 100 . The electronic component can be an active component or a passive component. Examples of the active elements or the passive elements may include those elements described above, and repeated descriptions thereof are omitted herein. In some embodiments, the electronic component 101 is a capacitor. In some embodiments, a height H1 of the electronic component 101 is different from a thickness H2 of the first pattern 21 . In some embodiments, the height H1 of the electronic component 101 is greater than the thickness H2 of the first pattern 21 . In some embodiments, height H1 is in the range of 0.5 to 3 microns. In some embodiments, height H1 is in the range of 1 to 2 microns. In some embodiments, the height H2 is between 0.1 and 1 range of microns. In some embodiments, the first pattern 21 and the electronic component 101 are disposed at the same height on the substrate 100 . In some embodiments, the lower surface of the first pattern 21 and the lower surface of the electronic component 101 are coplanar. In some embodiments, the first pattern 21 is disposed adjacent to the electronic component 101 . In some embodiments, the first pattern 21 is disposed directly adjacent to the electronic component 101 . In some embodiments, electronic components 101 are formed in component region 40 . In some embodiments, the electronic components 101 are formed around the component region 40 . In some embodiments, the electronic components 101 are formed in the scribe line area 30 for electrical examination. In some embodiments, the first pattern 21 is considered as a stack of pairs of marks.

FIG. 11 is a schematic cross-sectional view of different stages of the preparation method S1 according to some embodiments of the present disclosure. In step S12 , a photoluminescent layer 21 a is formed on the first pattern 21 . In some embodiments, the photoluminescent layer 21 a is formed only in the scribe line region 30 . In some embodiments, the photoluminescent layer 21 a is formed only on the first pattern 21 . In some embodiments, the photoluminescent layer 21 a overlaps the first pattern 21 . In some embodiments, the photoluminescent layer 21 a completely overlaps the first pattern 21 .

In some embodiments, the photoluminescent layer 21a includes one or more inorganic materials. In some embodiments, the photoluminescent layer 21a includes one or more of the following: phosphor, quantum dots, and a plurality of nanomaterials. In some embodiments, the nanomaterials include Gd ₂ O ₂ S:R, wherein R represents Eu ³⁺ , Pr ³⁺ or Tb ³⁺ . In some embodiments, the fabrication techniques of the photoluminescent layer 21 a include sputtering, coating and/or deposition, and are formed on the first pattern 21 . In these embodiments, a total thickness of the first pattern 21 and the photoluminescent layer 21a is greater than the thickness H2. In some embodiments, the fabrication technique of the photoluminescent layer 21 a includes doping, and is formed at a top of the first pattern 21 as shown in FIG. 11 . In these embodiments, the total thickness of the first pattern 21 and the photoluminescent layer 21a is approximately equal to the thickness H2.

In some embodiments, before the first pattern 21 is formed, the photoluminescent layer 21a is formed on the substrate 100 to form a configuration similar to that shown in FIG. 6 . In these embodiments, the fabrication techniques of the photoluminescent layer 21a include sputtering, coating and/or deposition. In some embodiments, the photoluminescent layer 21a and the first pattern 21 are patterned together, and the photoluminescent layer 21a may be completely covered by the first pattern 21 .

FIG. 12 is a schematic cross-sectional view of different stages of the preparation method S1 according to some embodiments of the present disclosure. In step S13 , an intermediate layer 141 is formed on the photoluminescent layer 21 a , the first pattern 21 and the substrate 100 . In some embodiments, the intermediate layer 141 is a dielectric layer of the interconnect structure for providing electrical isolation between different electrical paths of the interconnect structure. In some embodiments, the dielectric layer includes a dielectric material similar to or identical to the dielectric material of the insulating structure described above. In some embodiments, the fabrication technique of the intermediate layer 141 includes deposition. In some embodiments, the intermediate layer 141 includes oxide, and the fabrication technique includes a deposition having a temperature above 350°C. In some embodiments, the temperature of deposition ranges from 350°C to 375°C. In some embodiments, the photoluminescent or fluorescent material of photoluminescent layer 21a is stable at a temperature approximately equal to or greater than 375°C.

In some embodiments, a conformal deposition is performed to form the intermediate layer 141 . A contour of the middle layer 141 can conform to a contour of the electronic device 101 and the first pattern 21 . In some embodiments, the intermediate layer 141 may have different thicknesses at different portions at different heights due to the nature of the deposition. In some embodiments, a thickness H3 of a first portion of the intermediate layer 141 disposed on the electronic component 101 is substantially greater than a thickness H4 of a second portion of the intermediate layer 141 disposed on the first pattern 21 . In some embodiments, an overall thickness of the intermediate layer 141 ranges from 1.5 to 3 microns. In some embodiments, an overall thickness of the intermediate layer 141 ranges from 2 to 3 microns.

FIG. 13 is a schematic cross-sectional view of different stages of the preparation method S1 according to some embodiments of the present disclosure. Before step S14 , a mask layer 311 is formed on the intermediate layer 141 . In some embodiments, the mask layer 311 includes a photoresist material. In some embodiments, the mask layer 311 is a photoresist layer. In some embodiments, an upper surface 313 of the mask layer 311 is substantially a flat surface. In some embodiments, due to the different thicknesses of the electronic component 101 and the first pattern 21 , the upper surface 313 of the mask layer 311 includes an inclined portion as shown in FIG. 13 . In some embodiments, a thickness H5 of a first portion of the mask layer 311 on the electronic component 101 is smaller than a thickness H6 of a second portion of the mask layer 311 on the first pattern 21 . In some embodiments, thickness H5 is in the range of 1.5 to 2.5 microns. In some embodiments, thickness H6 is in the range of 2.5 to 3.5 microns.

In some embodiments, a distance H7 measured between a point A and an upper surface of the first pattern 21 is greater than 5.7 microns, wherein the point A is on the upper surface 313 of the first pattern 21, and the upper surface 313 is located at A position of the maximum thickness of the mask layer 311 . In some embodiments, a distance H8 is slightly greater than a distance H7 , wherein the distance H8 is measured between a top of the first portion of the upper limb of the electronic component 101 and the upper surface of the first pattern 21 of the mask layer 311 . In some embodiments, the difference between distance H8 and distance H7 is negligible and can be ignored.

Next, in step S14 of the manufacturing method S1, the mask layer 311 is patterned to form a patterned mask layer. A pattern of the patterned mask layer can be used as a current layer for the alignment detection performed in step S15.

Conventionally, a check of the alignment of the current layer with one of the previous layers depends solely on the reflection of a conventional overlay mark. A top of an overlay mark in a current layer and a top of an overlay mark in a previous layer are detected during inspection. However, a distance between the top of the overlay mark of the current layer and the top of the overlay mark in the previous layer The separation distance may be greater than the depth of field (DOF) of a detector, or a thickness of one or more interlayers between the two stacked pairs of marks may be greater than the DOF of the detector. Therefore, the overlay mark in the front layer may not be clearly or accurately detected. The present disclosure provides an overlay mark structure (such as the first pattern 21 in FIG. 13 ), which includes a photoluminescent or fluorescent material, and even if the distance H7 is greater than the DOF of the detector, it can still be accurately obtained at Detection of the overlay mark in the front layer.

14 is a schematic cross-sectional view along the line CC' of FIG. 3 or the line DD' of FIG. 4 at different stages of the preparation method S1 according to some embodiments of the present disclosure. In some embodiments, according to steps S11 to S13 and the formation of a mask layer 311 , as shown in FIG. 14 , an intermediate structure is formed.

15 is a schematic cross-sectional view along the section line CC' of FIG. 3 or the section line DD' of FIG. 4 at different stages of the preparation method S1 according to some embodiments of the present disclosure. In step S14 , the patterned mask layer 311 of FIG. 14 has formed the patterned mask layer 312 of FIG. 15 . In some embodiments, an exposure and a development process are performed on the mask layer 311 , and then some portions of the mask layer 311 are removed to form the patterned mask layer 312 . In some embodiments, an etching process is performed to remove the portions of the mask layer 311 . In some embodiments, a configuration of at least a portion of a pattern of the patterned mask layer 312 is similar to that shown in FIG. 3 or FIG. 4 from a top view. In some embodiments, from a top view, the photoluminescent layer 21 a or the first patterns 21 are exposed through the patterned mask layer 312 . In some embodiments, from a top view, the photoluminescent layer 21a or the first pattern 21 is surrounded by at least a part of the patterned mask layer 312, wherein the part of the patterned mask layer 312 is regarded as a Overlay markers. In some embodiments, from the top view, the photoluminescent layer 21 a or the first pattern 21 is surrounded by the portion of the patterned mask layer 312 .

The portion of the patterned mask layer 312 serving as a stack of marks can also be regarded as a second pattern 22 . In some embodiments, a distance H9 between a top of the second pattern 22 and a top of the first pattern 21 is substantially equal to the distance H7. In some embodiments, distance H9 is greater than the DOF of the detector. In some embodiments, distance H9 is greater than 5.7 microns.

16 is a schematic cross-sectional view along the section line CC' of FIG. 3 or the section line DD' of FIG. 4 at different stages of the preparation method S1 according to some embodiments of the present disclosure. In step S151 of step S15 , a first optical signal 51 is provided on the photoluminescent layer 21 a of the first pattern 21 . In some embodiments, the first optical signal 51 is provided across the entire wafer 10 . In some embodiments, the first optical signal 51 is provided in both the scribe line area 30 and the device area 40 . In some embodiments, the first optical signal 51 is only provided on the photoluminescent layer 21a. A wavelength of the first optical signal 51 may be in the range of the following wavelengths: near infrared (NIR), far infrared (FIR), ultraviolet (UV), near ultraviolet (NUV), far ultraviolet (FUV), green, yellow light, red light, or a combination thereof. In some embodiments, the first optical signal 51 is provided on the substrate 100 . The photoluminescent or fluorescent material of the photoluminescent layer 21 a is excited by the first optical signal 51 . Electrons of the excited photoluminescent or fluorescent material are returned from excited states to ground states, and radiation is emitted on the electrons returned to the ground state.

17 is a schematic cross-sectional view along the section line CC' of FIG. 3 or the section line DD' of FIG. 4 at different stages of the preparation method S1 according to some embodiments of the present disclosure. In step S152 of step S15, a second optical signal 52 is received by a detector. In some embodiments, the second optical signal 52 is a result of radiation relaxation that excites the photoluminescent layer 21a. In some embodiments, the second optical signal 52 is radiation emitted by the photoluminescent layer 21a. In some embodiments, the second optical signal 52 is visible radiation. In some embodiments, the second optical signal 52 is invisible radiation. The second optical signal 52 is passed through one of the disclosed The system performs processing to determine a position of the first pattern 21 in steps S153 to S154 and step S158, and the system is described in the following description.

18 is a schematic cross-sectional view along the section line CC' of FIG. 3 or the section line DD' of FIG. 4 at different stages of the preparation method S1 according to some embodiments of the present disclosure. In step S155 of step S15 , a third optical signal 53 is provided on the second pattern 22 of the patterned mask layer 312 . In some embodiments, the third optical signal 53 is provided across the entire wafer 10 . In some embodiments, the third optical signal 53 is provided in the dicing line region 30 of the wafer 10 . In some embodiments, the third optical signal 53 is only provided on the second pattern 22 . The third optical signal 53 can be visible radiation or invisible radiation. A wavelength of the third optical signal 53 may be in the range of the following wavelengths: near infrared (NIR), far infrared (FIR), ultraviolet (UV), near ultraviolet (NUV), far ultraviolet (FUV), green, yellow light, red light, or a combination thereof. Part or all of the third optical signal 53 on the second pattern 22 is reflected into a feedback signal.

FIG. 19 is a schematic cross-sectional view along the section line CC' of FIG. 3 or the section line DD' of FIG. 4 at different stages of the preparation method S1 according to some embodiments of the present disclosure. In step S156 of step S15, a fourth optical signal 54 is received. In some embodiments, the fourth optical signal 54 is a reflection or feedback signal from the second pattern 22 . The fourth optical signal 54 is processed by the disclosed system to determine a position of the second pattern 22 in steps S157 to S158 of step S15, and this system is described in the following description. In some embodiments, the second optical signal 52 is combined with the fourth optical signal 54 to check the alignment of the first pattern 21 and the second pattern 22 . If the alignment is accurate, the manufacturing method proceeds to a subsequent step; or, if the first pattern 21 and the second pattern 22 are misaligned, the patterned mask layer 312 may be removed and repeated. Formation and patterning of a mask layer (eg step S14).

Figure 20 is a different stage of the preparation method S1 according to some embodiments of the present disclosure The section is a schematic cross-sectional view along the section line CC' in FIG. 3 or the section line DD' in FIG. 4 . After step S15 , the manufacturing method S1 further includes converting the pattern of the patterned mask layer 312 into the intermediate layer 141 to form a third pattern 23 . In some embodiments, the third pattern 23 is disposed in the scribe line area 30 . In some embodiments, the third pattern 23 is disposed in the device area 40 . In some embodiments, the third pattern 23 is disposed at a corner of the device region 40 . In some embodiments, the third pattern 23 has a configuration similar to the overlay mark 22 in FIG. 3 or the overlay mark 22 in FIG. 4 . In some embodiments, the third pattern 23 is disposed at the same height as the first pattern 21 . In some embodiments, a thickness H10 of the third pattern 23 is greater than a thickness H2 of the first pattern 21 .

The present disclosure provides a method comprising forming a photoluminescent layer on an overlay mark of a front layer to better detect the alignment between the overlay mark of the front layer and a current layer. Even if a distance between the top of each overlay mark of the front layer and the current layer is greater than a depth of field of a detector, an accurate position of the overlay mark of the front layer can still be detected. The photoluminescent layer can be formed at a bottom or a top of the overlay mark. In addition, the photoluminescent layer includes photoluminescent or fluorescent materials that can withstand temperatures equal to or greater than 375° C., and thus, the photoluminescent layer can be easily applied in a conventional semiconductor manufacturing process. It should be understood that the photoluminescent layer of the present disclosure may be applied to an overlay mark on any layer of a semiconductor structure requiring an alignment check.

In order to perform the fabrication method S1 , especially the detection in step S15 for alignment inspection, the present disclosure provides a system for fabricating a semiconductor structure.

FIG. 21 is a block diagram illustrating a semiconductor manufacturing system 700 according to some embodiments of the present disclosure.

The semiconductor manufacturing system 700 may include a plurality of manufacturing equipment 710, 720-1, 720 - 2 . . . 720 -N, an exposure device 730 and an alignment device 740 . The fabrication equipment 710 , 720 - 1 , 720 - 2 . . . 720 -N, the exposure equipment 730 and the alignment equipment 740 may be coupled to a controller 760 via a network 750 .

In order to form a layer or a structure on a wafer 10, the manufacturing equipment 710 may therefore be configured to perform a plurality of steps. In some embodiments, fabrication apparatus 710 may be configured to form conductive layers of an insulating structure, a gate structure, and a semiconductor structure. The manufacturing apparatuses 720-1, 720-2...720-N may be configured to form multiple layers, such as the first pattern 21, the intermediate layer 141, the photoluminescent layer 21a, and the mask layer as shown in FIGS. 10 to 20 312. Each fabrication tool 720-1, 720-2...720-N can be configured to perform a deposition process, an etching process, a chemical mechanical polishing process, a photoresist coating process, a baking process, a pair of quasi-process or other process.

The exposure apparatus 730 may be configured to perform a plurality of patterning steps to form, for example, the first pattern 21 , the second pattern 22 and the third pattern 23 as shown in FIGS. 10 to 20 .

Alignment apparatus 740 may be configured to produce an alignment result of two overlay marks at different heights. Alignment device 740 can be configured to obtain an optical image of a pattern of a front layer (eg, first pattern 21 ) and a pattern of a current layer (eg, second pattern 22 ), and according to the front layer and the current layer Each of the aforementioned optical images of each of the patterns produces an alignment result.

Network 750 may be the Internet or an intranet implementing a network protocol, such as Transmission Control Protocol (TCP). Via the network 750, each of the fabrication equipment 710, 720-1, 720-2...720-N, the exposure equipment 730, and the alignment equipment 740 can download from the controller 760 the WIP ( WIP), or upload it to the controller 760. In some embodiments, each of the fabrication equipment 710 , 720 - 1 , 720 - 2 . . . 720 -N, the exposure equipment 730 and the alignment equipment 740 is electrically connected to the network 750 . In some embodiments, each of fabrication equipment 710, 720-1, 720-2...720-N, exposure equipment 730, and alignment equipment 740 is wirelessly connected. Connect to the network 750.

The controller 760 is configured to control the fabrication of the semiconductor structure or wafer 10 . The controller 760 is electrically or wirelessly connected to each of the fabrication equipment 710 , 720 - 1 , 720 - 2 . . . 720 -N, the exposure equipment 730 and the alignment equipment 740 . Controller 760 may include a processor, such as a central processing unit (CPU). In some embodiments, the controller 760 can generate an alignment result according to the data from the alignment device 740 . In some embodiments, the alignment result is generated by another controller in the alignment device 740 , and the controller 760 can receive the alignment result from the alignment device 740 . In some embodiments, if the alignment result is positive or the alignment is accurate, the controller 760 may proceed the fabrication of the wafer 10 to the next stage of the fabrication method.

In some exemplary embodiments, a wafer 10 is transferred to fabrication facility 710 to begin a series of different processes. Wafer 10 may be processed according to different stages of the fabrication method to form at least one material layer. The illustrated embodiments are not meant to limit the processes performed on wafer 10 . In other exemplary embodiments, the wafer 10 may include different layers, and any stage of the fabrication method may be performed between the beginning and the completion of a product before the wafer 10 is transferred to the fabrication facility 710 . In the illustrated embodiments, wafer 10 may be sequentially processed by fabrication equipment 710 , 720 - 1 , 720 - 2 . . . 720 -N, exposure equipment 730 , and alignment equipment 740 .

Although FIG. 21 does not show any fabrication equipment prior to fabrication equipment 710, this illustrated embodiment is not meant to be limiting. In some other exemplary embodiments, different types of manufacturing equipment can be used before the manufacturing equipment 710, and can be used to perform different processes according to design requirements.

Alignment device 740 may comprise several units or elements. In some embodiments, The alignment device 740 is considered an alignment inspection system 740 .

FIG. 22 is a schematic diagram illustrating an alignment device 740 of some embodiments of the present disclosure. In some embodiments, the alignment device 740 includes a platform 741 , an optical element 742 , a detection unit 743 , a controller 744 and an interface 745 .

Platform 741 may be configured to support a wafer 10 to undergo an alignment inspection and/or an alignment inspection. In some embodiments, after step S16, the wafer 10 is transferred to the alignment device 740 to perform step S17. In some embodiments, wafer 10 is transferred from exposure facility 730 or one of fabrication facilities 720-1 through 720-N. In some embodiments, wafer 10 is conveyed into alignment apparatus 740 and disposed on platform 741 .

Optical element 742 may be configured to emit a radiation or an optical signal to excite a photoluminescent material of an overlay mark in a dicing line region 30 of wafer 10 . In some embodiments, the radiation is the first optical signal 51 as shown in FIG. 16 . In some embodiments, the radiation is provided on a previous layer of overlay marked photoluminescent material in a scribe line region 30 . In some embodiments, the radiation is provided in both the scribe line region 30 and a device region 40 . In some embodiments, the radiation is provided across the entire wafer 10 . A wavelength of the radiation may be in the range of the following wavelengths: near infrared (NIR), far infrared (FIR), ultraviolet (UV), near ultraviolet (NUV), far ultraviolet (FUV), green, yellow, red light or a combination thereof. The photoluminescent material is excited by the radiation. Electrons of the excited photoluminescent material return from the excited state to the ground state, and a radiation is emitted on the electrons returning to the ground state.

The detection unit 743 is configured to detect the radiation emitted from the photoluminescent material of the overlay marks on the wafer 10 . In some embodiments, the detection unit 743 includes a filter 743a and an optical detector 743b. Filter 743a can be configured to receive and filter the radiation emitted from the photoluminescent material, and optical detector 743b can be configured to convert radiation emitted by the filter to An optical signal filtered by the optical device is converted into an electrical signal.

FIG. 23 is a schematic diagram illustrating a detection unit 743 of some embodiments of the present disclosure. In some embodiments, the filter 743a is a waveguide. In some embodiments, the filter 743a includes a grating structure 743c. The grating structure 743c allows the radiation to pass therethrough. In some embodiments, the grating structure 743c includes grating elements of different depths. In some embodiments as shown in FIG. 23, the grating structure 743c includes two grating units with two different depths. However, the present disclosure is not limited thereto. In some embodiments, the grating structure 743c may include one or more grating units. In some embodiments, the one or more grating elements may comprise different depths. In some embodiments, the grating structure 743c is a semiconductor material. In some embodiments, the grating structure 743c is formed in a semiconductor substrate.

The radiation emitted from the photoluminescent material of the overlay marks on the wafer 10 is received by the filter 743a. This radiation may enter the grating structure 743c and travel within the semiconductor material of the filter 743a. This radiation can be redirected and delivered to optical detector 743b. In some embodiments, the optical filter 743a is formed in the same semiconductor substrate as the optical detector 743b. In some embodiments, the optical detector 743b and the optical filter 743a are two semiconductor devices bonded on the same substrate. In some embodiments, the optical filter 743a is included in the same semiconductor package as the optical detector 743b. The radiation or optical signal from the filter 743a is received by the optical detector 743b and converted into an electrical signal. The electrical signal is output from the optical detector 743b and sent to the controller 744, and generates a data with an overlay mark of photoluminescent material.

In some embodiments, the radiation required to excite the photoluminescent material has a different wavelength than the radiation emitted due to the relaxation of the electrons of the photoluminescent material. In some embodiments, a filtering range of the wavelengths of the filter 743a is different from that obtained by A range of the wavelengths of the radiation generated by optical element 742 . A wavelength of the radiation generated by the optical element 742 can be adjusted depending on the photoluminescent material. The filter range of the wavelengths of the filter 743a can also be adjusted according to the photoluminescent material. In some embodiments, the grating structure 743c of the filter 743a includes different depths to filter different ranges of the multiple wavelengths of the multiple radiations. The different radiations can be converted into different electrical signals by the optical detector 743b, and then the electrical signals can be processed and classified by the controller 744. In some embodiments, only the electrical signals corresponding to a desired range of wavelengths are used in an alignment result.

Please refer back to FIG. 22 , the controller 744 can be electrically or wirelessly connected to the optical element 742 or the detection unit 743 . The controller 744 may be configured to process electrical signals from the optical detector 743b of the detection unit 743 . In some embodiments, the controller 744 receives an electrical signal from the detection unit 743 . The electrical signal is processed by the controller 744 to generate a position of the overlay marks displayed in the dicing line area 30 on the wafer 10 . In some embodiments, controller 744 may include a processor, such as a central processing unit (CPU). In some embodiments, controller 744 is a logic element. In some embodiments, the data may be displayed on interface 745 . The interface 745 is electrically or wirelessly connected to the controller 744 .

In some embodiments, optical element 742 produces another radiation directed at a different overlay mark (eg, in the galvanic layer). The above process is repeated on the different overlay marks. A profile of the different overlay marks can be generated and combined with previously detected overlay marks (eg, in a previous layer). An alignment result is then generated by the controller 744 by combining and processing the two data for two different overlay marks at different heights. In some embodiments, alignment device 740 does not have a controller. In some embodiments, the electrical signal output from the detection unit 743 is sent to the controller 760 as shown in FIG. 21 . Controller 760 may be treated similarly to controller 744 to process the electrical signal and generate an alignment result.

An embodiment of the present disclosure provides a method for fabricating a semiconductor structure. The preparation method includes forming a first pattern on a substrate; forming a photoluminescent layer on the first pattern; forming an intermediate layer on the photoluminescent layer and the substrate; forming a patterned mask layer on the substrate on the intermediate layer; and detecting an alignment of the patterned mask layer and the first pattern.

An embodiment of the present disclosure provides a system for fabricating a semiconductor structure. The system includes a fabrication apparatus configured to perform steps to form a layer on a wafer; an exposure apparatus configured to perform patterning steps to form a pattern of the layer; and an alignment apparatus, configured to detect an alignment of two overlay marks at different heights on the wafer. The alignment apparatus includes: a stage configured to support the wafer; an optical element configured to emit a radiation to excite a photoluminescent material of one of the two stacked markers; an optical filter configured to to receive and filter a radiation emitted from the photoluminescent material; and an optical detector configured to convert an optical signal filtered by the filter into an electrical signal.

An embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure includes: a capacitor disposed on a substrate; an overlay mark disposed adjacent to the capacitor and at a same height as the capacitor; a photoluminescent layer disposed on the overlay mark; and An intermediate layer is arranged on the capacitor and the photoluminescent layer.

In conclusion, the application discloses a semiconductor structure, a method for fabricating the semiconductor structure, and a system for performing the method. A photoluminescent layer is included in an overlay mark and improves a detection of the overlay mark on a preceding layer.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the processes described above can be performed in different ways and replaced by other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that existing or future developed processes, machinery, manufacturing, A composition of matter, means, method, or step. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patent scope of this application.

100: base

21: Overlay Mark

22: Overlay Mark

Claims (19)

A method for preparing a semiconductor structure, comprising: forming a first pattern on a substrate; forming a photoluminescent layer on the first pattern; forming an intermediate layer on the photoluminescent layer and the substrate; forming a patterned mask layer on the intermediate layer; and An alignment of the patterned mask layer and the first pattern is detected. The preparation method according to claim 1, further comprising converting the patterned mask layer into the intermediate layer. The preparation method according to claim 1, wherein the photoluminescent layer includes phosphor powder, quantum dots, a plurality of nanometer materials or a combination thereof. The preparation method according to claim 3, wherein the nanomaterials include Gd ₂ O ₂ S:R, and R represents Eu ³⁺ , Pr ³⁺ or Tb ³⁺ . The preparation method according to claim 1, wherein the fabrication technique of the photoluminescent layer includes one or more of deposition, sputtering and coating. The preparation method according to claim 1, wherein the photoluminescent layer is exposed through the patterned mask layer viewed from a top view. The manufacturing method according to claim 6, wherein viewed from the top view, the first pattern is surrounded by at least a part of the patterned mask layer. The manufacturing method according to claim 6, wherein viewed from the top view, the first pattern is at least partially surrounded by the patterned mask layer. The preparation method as described in claim 1, wherein detecting the alignment comprises: providing a first optical signal on the photoluminescent layer; receiving a second optical signal from the photoluminescent layer; filtering the second optical signal; and The second optical signal is converted into a first electrical signal. The preparation method as described in claim item 9, wherein the detection of the alignment comprises: providing a third optical signal on the patterned mask layer; receiving a fourth optical signal from the patterned mask layer; and converting the fourth optical signal into a second electrical signal. The preparation method according to claim 10, wherein the first electrical signal and the second electrical signal are processed to show the alignment of the patterned mask layer and the photoluminescent layer. The preparation method as claimed in claim 1, wherein the intermediate layer comprises one or more dielectric materials. The manufacturing method as claimed in claim 1, wherein the first pattern is formed adjacent to a capacitor. The manufacturing method according to claim 13, wherein the capacitor is formed at the same height as the first pattern. The manufacturing method as claimed in claim 13, wherein a height of the capacitor is greater than a thickness of the first pattern. The manufacturing method as claimed in claim 13, wherein a thickness of a first portion of the intermediate layer on the capacitor is smaller than a thickness of a second portion of the intermediate layer on the first pattern. The preparation method as described in Claim 13, wherein the formation of the patterned mask layer comprises: disposing a photoresist layer on the intermediate layer; and Portions of the photoresist layer are removed to form the patterned mask layer. The manufacturing method as claimed in claim 17, wherein a thickness of a first portion of the photoresist layer on the capacitor is smaller than a thickness of a second portion of the photoresist layer on the first pattern. The manufacturing method according to claim 1, wherein a distance between a top of the patterned mask layer and a top of the first pattern is greater than 5.7 microns.

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