CN112018082B - Method for preparing overlay alignment mark and structure thereof - Google Patents
Method for preparing overlay alignment mark and structure thereof Download PDFInfo
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- CN112018082B CN112018082B CN201910470028.4A CN201910470028A CN112018082B CN 112018082 B CN112018082 B CN 112018082B CN 201910470028 A CN201910470028 A CN 201910470028A CN 112018082 B CN112018082 B CN 112018082B
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Abstract
The invention provides a preparation method and a structure of an overlay alignment mark, wherein the overlay alignment mark comprises the following steps: a metal mark and a current layer mark; the metal mark is used as a front layer mark, the metal mark penetrates through the film structure, the bottom of the metal mark is positioned in the substrate, the substrate comprises a first surface of the substrate and a second surface of the substrate, the second surface of the substrate is correspondingly arranged, and the film structure is positioned on the first surface of the substrate; when the layer mark is located on the second surface of the substrate. According to the invention, the metal mark is used as the front layer mark, so that the signal intensity of the front layer mark to infrared rays is improved, the measurement error of the alignment mark is reduced, the OVL is improved, the photoetching accuracy is improved, and the product quality is improved; the metal mark is formed at the same time of forming the metal interconnection structure, so that the cost can be further reduced.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a preparation method and a structure of an overlay alignment mark.
Background
In the fabrication of integrated circuit chips, similar to building construction in structure, the substrate is first built layer by layer, and the layers must be aligned with each other with a certain precision to ensure the normal function of the final chip.
The registration accuracy and the critical dimension are basic measurement indexes of the photoetching process, the critical dimension ensures the required line width on a chip, and the registration accuracy ensures the alignment degree between lines among different layers. Briefly, the OVL is the alignment accuracy between the current layer and the previous layer in the photolithography process, and if the alignment accuracy of the photolithography process exceeds the error tolerance, the interlayer design circuit may be broken or shorted due to displacement, thereby affecting the yield of the product.
With the rapid development of IC manufacturing, the photolithographic imaging technology is continuously improved, the production process becomes more and more complex, and the feature size of the chip is continuously reduced, which leads to higher requirements for OVL. In order to meet design requirements in a semiconductor device with a high integration level, it is important to reduce the error of each lithography step as much as possible in the lithography process and reduce device failures caused by the error.
Currently, an infrared measurement method is generally adopted for measuring the back overlay alignment mark, but when the back alignment is performed, the signal intensity of a front layer mark in the overlay alignment mark to infrared is weak, so that a measurement error of the overlay alignment mark is easily caused, an error is generated in a photolithography step, and a product fails.
In order to improve the alignment accuracy of the overlay, the improvement of the lithographic apparatus is partly satisfactory, but the improvement and the updating of the lithographic apparatus require a large investment of money, resulting in waste of money.
Therefore, it is necessary to provide a novel method for manufacturing overlay alignment marks and a structure thereof to improve the signal strength of the front layer mark to infrared rays when measuring the back overlay alignment mark, reduce the measurement error of the overlay alignment mark, improve the OVL, improve the yield of products, and reduce the cost.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a method for manufacturing an overlay alignment mark and a structure thereof, for solving the problems in the prior art that during back overlay alignment, a front layer mark of the overlay alignment mark has weak signal intensity to infrared rays, which easily causes measurement errors of the overlay alignment mark, an OVL between layers is low, and a photolithography step is prone to generate errors, which causes product failure.
To achieve the above and other related objects, the present invention provides a method for preparing an overlay alignment mark, comprising the steps of:
providing a substrate, wherein the substrate comprises a first substrate surface and a second substrate surface which is correspondingly arranged;
forming a thin film structure on the first surface of the substrate;
forming a groove, wherein the groove penetrates through the thin film structure, and the bottom of the groove is positioned in the substrate;
filling metal in the groove to form a metal mark, wherein the metal mark is used as a front layer mark;
forming a current layer mark on the second surface of the substrate, thereby obtaining the overlay alignment mark comprising the metal mark and the current layer mark.
Optionally, the method further comprises a step of forming a metal interconnection structure, and the metal mark is formed simultaneously with the metal connection structure.
Optionally, the overlay alignment mark is located in a scribe line; the pattern of the overlay alignment mark comprises one or a combination of Box in Box, Bar in Bar and Frame in Frame.
Optionally, the groove is filled with a metal, and the step of forming the metal mark includes:
depositing a first metal layer in the groove, wherein the first metal layer covers the bottom and the side wall of the groove;
and depositing a second metal layer on the first metal layer, wherein the second metal layer fills the groove to form the metal mark comprising the first metal layer and the second metal layer.
Optionally, the first metal layer includes one or a combination of a titanium metal layer, a tungsten metal layer, a tantalum metal layer, a molybdenum metal layer, a platinum metal layer, a titanium nitride metal layer, and a titanium-tungsten metal layer; the second metal layer comprises one or a combination of a tungsten metal layer, a copper metal layer and an aluminum metal layer.
Optionally, the thin film structure comprises a composite laminate.
Optionally, after the metal mark is formed and before the current-layer mark is formed, a process step of thinning the substrate is further included.
Optionally, after the metal mark is formed and before the current-layer mark is formed, a step of forming a dielectric layer on the second surface of the substrate is further included.
The present invention also provides an overlay alignment mark, comprising:
a metal mark as a front layer mark, wherein the metal mark penetrates through the thin film structure and the bottom of the metal mark is positioned in the substrate; the substrate comprises a substrate first surface and a substrate second surface which is correspondingly arranged, and the thin film structure is positioned on the substrate first surface;
the layer-time mark is positioned on the second surface of the substrate.
Optionally, the overlay alignment mark is located in a scribe line; the pattern of the overlay alignment mark comprises one or a combination of Box in Box, Bar in Bar and Frame in Frame.
Optionally, the metal mark includes a first metal layer and a second metal layer located on the surface of the first metal layer; the first metal layer comprises one or a combination of a titanium metal layer, a tungsten metal layer, a tantalum metal layer, a molybdenum metal layer, a platinum metal layer, a titanium nitride metal layer and a titanium-tungsten metal layer; the second metal layer comprises one or a combination of a tungsten metal layer, a copper metal layer and an aluminum metal layer.
Optionally, the thin film structure comprises a composite laminate; and a dielectric layer is also arranged between the current-layer mark and the second surface of the substrate.
As described above, according to the method for manufacturing the overlay alignment mark and the structure thereof, the metal mark is used as the front layer mark to improve the signal intensity of the front layer mark to infrared rays and reduce the measurement error of the overlay alignment mark, so that the OVL is improved, the photolithography accuracy is improved, and the product quality is improved; the metal mark is formed at the same time of forming the metal interconnection structure, so that the cost can be further reduced.
Drawings
FIG. 1 is a schematic diagram of a process for preparing an overlay alignment mark according to the present invention.
FIGS. 2 to 8 are schematic structural views showing steps of preparing an alignment mark according to the present invention; fig. 8 also shows a schematic structural diagram of the alignment mark in the present invention.
FIG. 9 is a schematic view of the alignment mark alignment structure using infrared measurement according to the present invention.
FIG. 10 is a schematic diagram showing an image structure of an overlay alignment mark obtained by infrared measurement according to the present invention.
Description of the element reference numerals
100 substrate
200 thin film structure
201 silicon oxide thin film layer
202 dielectric layer
300 groove
400 metal mark
401 first metal layer
402 second metal layer
500 photo resist layer
600 Photoresist marker
700 infrared ray
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1-10. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Referring to fig. 1 to 8, the present invention provides a method for preparing an overlay alignment mark, which may include the following steps:
providing a substrate 100, wherein the substrate 100 comprises a substrate first surface and a substrate second surface arranged correspondingly;
forming a thin film structure 200, wherein the thin film structure 200 is located on the first surface of the substrate;
forming a groove 300, wherein the groove 300 penetrates through the thin film structure 200 and the bottom of the groove 300 is positioned in the substrate 100;
filling metal in the groove 300 to form a metal mark 400, wherein the metal mark 400 is used as a front layer mark;
forming a current layer mark on the second surface of the substrate, thereby obtaining the overlay alignment mark including the metal mark 400 and the current layer mark.
According to the invention, the metal mark 400 is used as a front layer mark, and when infrared rays are adopted for back overlay alignment, the signal intensity of the front layer mark to the infrared rays can be improved, so that the measurement error of the overlay alignment mark is reduced, and the overlay precision (OVL) is improved, thereby improving the photoetching precision and improving the product quality.
As shown in fig. 2, a substrate 100 is first provided, and the thin-film structure 200 is formed on a first surface of the substrate.
Specifically, the substrate 100 may be a silicon substrate, but is not limited thereto. The thin-film structure 200 may comprise a composite laminate structure, or a single-layer structure may be selected as desired. In the present embodiment, the thin film structure 200 is a composite laminate including a silicon oxide thin film layer 201 and a dielectric layer 202, but is not limited thereto. The method of forming the thin film structure 200 may employ one or a combination of PVD and CVD. In this embodiment, the thin film structure 200 is formed by depositing the silicon oxide thin film layer 201 and the dielectric layer 202 on the first surface of the substrate in sequence by CVD to form the composite laminate, the dielectric layer 202 is a silicon nitride layer, and the structure and the preparation method of the thin film structure 200 may be selected according to the requirement, but are not limited thereto.
As shown in fig. 3, the groove 300 is formed, the groove 300 penetrates through the thin film structure 200, and the bottom of the groove 300 is located in the substrate 100.
As a further embodiment of this embodiment, a step of forming a metal interconnection structure (not shown) is further included, and the metal mark 400 is preferably formed simultaneously with the metal interconnection structure, so as to simplify the process and reduce the process cost.
Specifically, the overlay alignment mark and the metal interconnection structure are preferably prepared by using the same material and process, so that the process is simplified and the process cost is reduced. That is, the groove 300 and the groove for forming the metal interconnection structure may be performed simultaneously, and preferably, the groove 300 is located in the scribe line, so as to prevent the overlay alignment mark from occupying the effective area of the wafer, thereby improving the utilization rate of the wafer. The step of forming the groove 300 may include: depositing a mask layer on the surface of the dielectric layer 202, patterning the mask layer to form a window with the groove 300, and then etching the thin film structure 200 and the substrate 100 to form the groove 300, wherein the shape of the groove 300 may include a square shape, a frame shape, or a rod shape, and the depth and width of the groove are not limited herein, and are preferably the same as those of the groove of the metal connection structure. In this embodiment, the groove 300 is a frame-shaped structure having a rectangular shape, but the shape of the groove 300 is not limited thereto.
As shown in fig. 4 to 5, the groove 300 is filled with metal to form the metal mark 400, and the metal mark 400 is used as a front layer mark. Wherein the step of forming the metal mark 400 may include:
depositing a first metal layer 401 in the groove 300, wherein the first metal layer 401 covers the bottom and the side wall of the groove 300;
a second metal layer 402 is deposited on the surface of the first metal layer 401, and the recess 300 is filled with the second metal layer 402 to form the metal mark 400 including the first metal layer 401 and the second metal layer 402.
Specifically, the first metal layer 401 can serve as a metal barrier layer, which can prevent the second metal layer 402 from diffusing, and has good adhesion with the second metal layer 402 and the substrate 100, thereby enhancing the structural stability. The first metal layer 401 may include one or a combination of a titanium metal layer, a tungsten metal layer, a tantalum metal layer, a molybdenum metal layer, a platinum metal layer, a titanium nitride metal layer, and a titanium tungsten metal layer; the second metal layer 402 may comprise one or a combination of a tungsten metal layer, a copper metal layer, and an aluminum metal layer. After the first metal layer 401 and the second metal layer 402 are formed, a step of removing the second metal layer 402 and the first metal layer 401 on the upper surface of the dielectric layer 202 by etching or grinding is further included. In this embodiment, the first metal layer 401 is a titanium metal layer, the second metal layer 402 is a tungsten metal layer, and the metal mark 400 and the metal interconnection structure are formed simultaneously to simplify the process steps, so that the metal mark 400 has a structure including the first metal layer 401 and the second metal layer 402, and preferably, the first metal layer 401 covers the bottom and the sidewall of the groove 300. In another example, the first metal layer 401 may only cover the bottom of the groove 300, or the metal mark 400 may only include the first metal layer 401 or the second metal layer 402, which is not limited herein.
As a further embodiment of this embodiment, after forming the metal mark 400, a process step of thinning the substrate 100 may be further included.
Specifically, as shown in fig. 6, according to the process requirement, the substrate 100 may be thinned from the second side of the substrate after the metal mark 400 is formed, so as to prepare a functional device and the like on the second side of the substrate, and of course, the thinning process may not be performed, which is not limited herein. The thinning process may include physical polishing or chemical mechanical planarization, and the specific type may be selected according to the requirement, which is not limited herein.
Next, as shown in fig. 7 to 8, the current layer mark is formed on the second surface of the substrate, so as to obtain the overlay alignment mark including the metal mark 400 and the current layer mark.
Specifically, in order to simplify the process steps and reduce the cost, the current-layer mark is preferably a photoresist mark 600, but the type of the current-layer mark is not limited thereto and can be selected as needed. The step of forming the photoresist mark 600 may include: forming a photoresist layer 500 on the second surface of the substrate, and patterning the photoresist layer 500 to form the photoresist mark 600, and using the photoresist mark 600 as the current layer mark, thereby obtaining the overlay alignment mark including the metal mark 400 and the photoresist mark 600. The photoresist mark 600 preferably has the same shape and appearance as the metal mark 400, and the cross-sectional area of the photoresist mark 600 is smaller than that of the metal mark 400, so as to form the overlay alignment mark having a nested structure. The pattern of the overlay alignment mark preferably comprises one or a combination of Box in Box, Bar in Bar and Frame in Frame. The overlay alignment mark is preferably located in the scribe line to prevent the overlay alignment mark from occupying an effective area of the wafer, so as to improve the utilization rate of the wafer.
As a further embodiment of this embodiment, after forming the metal mark 400 and before forming the current-layer mark, a step of forming a dielectric layer (not shown) on the second surface of the substrate may be further included.
Specifically, the dielectric layer may include a composite laminated layer, and the specific type of the dielectric layer may be selected according to the process requirement, for example, the dielectric layer may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and the like, which is not limited herein.
As shown in fig. 8, the present invention further provides an overlay alignment mark, which can be prepared by the above-mentioned preparation method, but is not limited thereto, wherein the overlay alignment mark can be used in the preparation process of the IGBT, but is not limited thereto.
Specifically, the overlay alignment mark includes the metal mark 400 as a previous layer mark and the photoresist mark 600 as a current layer mark. The metal mark 400 penetrates through the thin film structure 200 and the bottom of the metal mark 400 is located in the substrate 100; the substrate 100 includes a substrate first surface and a substrate second surface correspondingly disposed, the thin film structure 200 is located on the substrate first surface, and the thin film structure 200 includes the silicon oxide thin film layer 201 and a dielectric layer 202; the photoresist marks 600 are located on the substrate second surface.
As a further embodiment of this embodiment, the overlay alignment mark is preferably located in the scribe lane; the pattern of the overlay alignment mark may include one or a combination of Box in Box, Bar in Bar, and Frame in Frame.
As a further embodiment of this embodiment, the metal mark 400 may include the first metal layer 401 and the second metal layer 402 on the surface of the first metal layer 401; the first metal layer 401 may include one or a combination of a titanium metal layer, a tungsten metal layer, a tantalum metal layer, a molybdenum metal layer, a platinum metal layer, a titanium nitride metal layer, and a titanium-tungsten metal layer; the second metal layer 402 may comprise one or a combination of a tungsten metal layer, a copper metal layer, and an aluminum metal layer.
As a further example of this embodiment, the thin-film structure 200 may comprise a composite laminate; the dielectric layer (not shown) may also be included between the photoresist marker 600 and the second surface of the substrate.
As shown in fig. 9, when measuring the overlay alignment mark by using infrared measurement, infrared 700(IR) penetrates through the substrate 100 to obtain an image of the overlay alignment mark, as shown in fig. 10, and the overlay accuracy OVL can be determined according to the image of the overlay alignment mark, so as to determine the alignment accuracy in the photolithography process and improve the product quality.
The inventors have studied that when the metal mark 400 is used as a front layer mark, a better IR signal intensity can be obtained. When the metal mark 400 is used as a front layer mark and the silica mark is used as a front layer mark, the signal intensity score (92.6) of the metal mark 400 to the IR is significantly larger than the signal intensity score (82.13) of the silica mark to the IR, as in the IR transmission measurement using the KLA Archer 500 apparatus. Therefore, when the metal mark 400 is used as a front layer mark, the signal strength of the front layer mark to the IR can be improved to reduce the measurement error of the overlay alignment mark, thereby improving the OVL, improving the photolithography accuracy, and improving the product quality.
In summary, according to the preparation method and the structure of the overlay alignment mark of the present invention, the metal mark is used as the front layer mark to improve the signal intensity of the front layer mark to the infrared ray, so as to reduce the measurement error of the overlay alignment mark, thereby improving the OVL, improving the photolithography accuracy, and improving the product quality; the metal mark is formed at the same time of forming the metal interconnection structure, so that the cost can be further reduced. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (12)
1. A preparation method of an overlay alignment mark is characterized by comprising the following steps:
providing a substrate, wherein the substrate comprises a first substrate surface and a second substrate surface which is correspondingly arranged;
forming a thin film structure on the first surface of the substrate;
forming a groove, wherein the groove penetrates through the thin film structure, and the bottom of the groove is positioned in the substrate;
filling metal in the groove to form a metal mark, wherein the metal mark is used as a front layer mark;
forming a current layer mark on the second surface of the substrate, thereby obtaining the overlay alignment mark comprising the metal mark and the current layer mark.
2. The method for preparing an overlay alignment mark according to claim 1, wherein: the method further comprises a step of forming a metal interconnection structure, and the metal mark and the metal connection structure are formed synchronously.
3. The method for preparing an overlay alignment mark according to claim 1, wherein: the overlay alignment mark is positioned in the cutting channel; the pattern of the overlay alignment mark comprises one or a combination of Box in Box, Bar in Bar and Frame in Frame.
4. The method according to claim 1, wherein the groove is filled with a metal, and the step of forming the metal mark comprises:
depositing a first metal layer in the groove, wherein the first metal layer covers the bottom and the side wall of the groove;
and depositing a second metal layer on the first metal layer, wherein the second metal layer fills the groove to form the metal mark comprising the first metal layer and the second metal layer.
5. The method for preparing an overlay alignment mark according to claim 4, wherein: the first metal layer comprises one or a combination of a titanium metal layer, a tungsten metal layer, a tantalum metal layer, a molybdenum metal layer, a platinum metal layer, a titanium nitride metal layer and a titanium-tungsten metal layer; the second metal layer comprises one or a combination of a tungsten metal layer, a copper metal layer and an aluminum metal layer.
6. The method for preparing an overlay alignment mark according to claim 1, wherein: the thin film structure includes a composite laminate.
7. The method for preparing an overlay alignment mark according to claim 1, wherein: after the metal mark is formed and before the current-layer mark is formed, the method also comprises the process step of thinning the substrate.
8. The method for preparing an overlay alignment mark according to claim 1, wherein: after the metal mark is formed and before the current layer mark is formed, a step of forming a dielectric layer on the second surface of the substrate is further included.
9. An overlay alignment mark, wherein the overlay alignment mark is located in a scribe line, and the overlay alignment mark comprises:
a metal mark as a front layer mark, wherein the metal mark penetrates through the thin film structure and the bottom of the metal mark is positioned in the substrate; the substrate comprises a substrate first surface and a substrate second surface which is correspondingly arranged, and the thin film structure is positioned on the substrate first surface;
a layer-time mark, the layer-time mark being located on the second surface of the substrate.
10. The overlay alignment mark of claim 9, wherein: the pattern of the overlay alignment mark comprises one or a combination of Box inBox, Bar in Bar and Frame in Frame.
11. The overlay alignment mark of claim 9, wherein: the metal mark comprises a first metal layer and a second metal layer positioned on the surface of the first metal layer; the first metal layer comprises one or a combination of a titanium metal layer, a tungsten metal layer, a tantalum metal layer, a molybdenum metal layer, a platinum metal layer, a titanium nitride metal layer and a titanium-tungsten metal layer; the second metal layer comprises one or a combination of a tungsten metal layer, a copper metal layer and an aluminum metal layer.
12. The overlay alignment mark of claim 9, wherein: the thin film structure comprises a composite laminate; and a dielectric layer is also arranged between the current-layer mark and the second surface of the substrate.
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| CN112687757B (en) * | 2020-12-24 | 2023-02-03 | 芯思杰技术(深圳)股份有限公司 | Photoelectric detection chip manufacturing method |
| CN116682724B (en) * | 2023-06-08 | 2024-04-26 | 荣芯半导体(淮安)有限公司 | Semiconductor structure, forming method and related device |
| CN118571863A (en) * | 2024-07-30 | 2024-08-30 | 合肥晶合集成电路股份有限公司 | Preparation method of alignment mark and semiconductor structure |
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| US7192845B2 (en) * | 2004-06-08 | 2007-03-20 | Macronix International Co., Ltd. | Method of reducing alignment measurement errors between device layers |
| KR20060108873A (en) * | 2005-04-14 | 2006-10-18 | 주식회사 하이닉스반도체 | Method for forming multi layer alignment mark of semiconductor device |
| US7588993B2 (en) * | 2007-12-06 | 2009-09-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Alignment for backside illumination sensor |
| US8143731B2 (en) * | 2009-07-14 | 2012-03-27 | Nanya Technology Corp. | Integrated alignment and overlay mark |
| US8928159B2 (en) * | 2010-09-02 | 2015-01-06 | Taiwan Semiconductor Manufacturing & Company, Ltd. | Alignment marks in substrate having through-substrate via (TSV) |
| CN103050480B (en) * | 2012-08-14 | 2015-08-19 | 上海华虹宏力半导体制造有限公司 | The back-patterned process of silicon chip |
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