CN116682724B - Semiconductor structure, forming method and related device - Google Patents
Semiconductor structure, forming method and related device Download PDFInfo
- Publication number
- CN116682724B CN116682724B CN202310674827.XA CN202310674827A CN116682724B CN 116682724 B CN116682724 B CN 116682724B CN 202310674827 A CN202310674827 A CN 202310674827A CN 116682724 B CN116682724 B CN 116682724B
- Authority
- CN
- China
- Prior art keywords
- layer
- substrate
- marking groove
- marking
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 82
- 239000004065 semiconductor Substances 0.000 title claims abstract description 61
- 239000010410 layer Substances 0.000 claims abstract description 373
- 239000000758 substrate Substances 0.000 claims abstract description 219
- 239000002346 layers by function Substances 0.000 claims abstract description 54
- 230000008569 process Effects 0.000 claims abstract description 49
- 239000013078 crystal Substances 0.000 claims abstract description 39
- 238000001259 photo etching Methods 0.000 claims abstract description 38
- 238000005530 etching Methods 0.000 claims description 24
- 238000000227 grinding Methods 0.000 claims description 17
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 238000001465 metallisation Methods 0.000 claims description 11
- 238000000206 photolithography Methods 0.000 claims description 10
- 229910021332 silicide Inorganic materials 0.000 claims description 8
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 8
- 238000000137 annealing Methods 0.000 claims description 3
- 239000011241 protective layer Substances 0.000 claims description 3
- 238000003746 solid phase reaction Methods 0.000 claims description 3
- 239000003550 marker Substances 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims 2
- 230000000694 effects Effects 0.000 abstract description 13
- 239000000463 material Substances 0.000 description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 15
- 229910052710 silicon Inorganic materials 0.000 description 15
- 239000010703 silicon Substances 0.000 description 15
- 238000010586 diagram Methods 0.000 description 7
- 238000005498 polishing Methods 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 239000010936 titanium Substances 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000011575 calcium Substances 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 239000011651 chromium Substances 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 239000011572 manganese Substances 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- OYPRJOBELJOOCE-UHFFFAOYSA-N Calcium Chemical compound [Ca] OYPRJOBELJOOCE-UHFFFAOYSA-N 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- PWHULOQIROXLJO-UHFFFAOYSA-N Manganese Chemical compound [Mn] PWHULOQIROXLJO-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 229910052791 calcium Inorganic materials 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 238000005286 illumination Methods 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 229910052748 manganese Inorganic materials 0.000 description 2
- 229910021645 metal ion Inorganic materials 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 229910052712 strontium Inorganic materials 0.000 description 2
- CIOAGBVUUVVLOB-UHFFFAOYSA-N strontium atom Chemical compound [Sr] CIOAGBVUUVVLOB-UHFFFAOYSA-N 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000011104 metalized film Substances 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
- H01L21/3043—Making grooves, e.g. cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54493—Peripheral marks on wafers, e.g. orientation flats, notches, lot number
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The embodiment of the invention provides a semiconductor structure, a forming method and a related device, wherein the forming method of the semiconductor structure comprises the following steps: providing a substrate; forming a marking groove on the substrate; forming a reflecting layer on the side wall and the bottom of the marking groove; forming an epitaxial layer covering the surface of the substrate on one side of the substrate facing the marking groove; and taking the reflecting layer in the marking groove as a mark, and overlapping the marking groove on the front surface and/or the back surface of the substrate to form a device functional layer. The embodiment of the invention can simultaneously improve the alignment precision of the crystal face and the crystal back process, improve the photoetching alignment effect and further improve the yield of the semiconductor device.
Description
Technical Field
The embodiment of the invention relates to the technical field of semiconductors, in particular to a semiconductor structure, a forming method and a related device.
Background
With the development of semiconductor technology, to obtain a semiconductor device with high power requirements, BCD (Bipolar CMOS DMOS) processes may be used to integrate three different devices on the same chip, or to form a Super Junction device (SJ) with a Super Junction voltage-resistant layer. In the process of manufacturing a semiconductor device, a marking structure for marking positions is usually formed on a substrate, and the marking structure is called Zero Mark (ZM), when device layers are formed on the front and back surfaces of the substrate, the Zero Mark can be used as a reference position for forming various device layers subsequently, namely: the Alignment (Alignment) and Overlay (Overlay) marks on the back side of the crystal plane, and the zero layer mark may also be used as a polishing stop mark on the back side of the substrate when forming the device layer on the back side of the substrate.
However, the performance of the semiconductor device formed by the zero layer mark prepared in the prior art is poor, and the yield of the semiconductor device is affected.
Disclosure of Invention
In view of this, embodiments of the present invention provide a semiconductor structure, a forming method and a related device, so as to improve the photo-etching alignment effect and overlay accuracy of the mark structure, improve the performance of the semiconductor device, and further improve the yield of the semiconductor device.
The embodiment of the invention provides a method for forming a semiconductor structure, which comprises the following steps:
Providing a substrate;
forming a marking groove on the substrate;
Forming a reflecting layer on the side wall and the bottom of the marking groove;
forming an epitaxial layer covering the surface of the substrate on one side of the substrate facing the marking groove;
and taking the reflecting layer in the marking groove as a mark, and overlapping the marking groove on the front surface and/or the back surface of the substrate to form a device functional layer.
Optionally, the thickness of the light reflecting layer is greater than or equal to 4nm.
Optionally, the material of the light reflecting layer is a metalization.
Optionally, in the step of forming an epitaxial layer covering the surface of the substrate on the side of the substrate facing the marking groove, the epitaxial layers on two sides of the marking groove are not connected;
And the light reflecting layer in the marking groove is used as a mark, the marking groove is sleeved on the front surface and/or the back surface of the substrate to form a device functional layer, specifically, the light reflecting layer in the marking groove is used as a mark, and the marking groove is sleeved on the front surface of the substrate to form the device functional layer.
Optionally, the device functional layer includes: a crystal face functional layer;
and the reflecting layer in the marking groove is used as a mark, the marking groove is sleeved on the front surface of the substrate to form a device functional layer, specifically, the reflecting layer in the marking groove is used as a mark, and a crystal face functional layer is formed on the epitaxial layer.
Optionally, in the step of forming an epitaxial layer covering the surface of the substrate on the side of the substrate facing the marking groove, the epitaxial layers on two sides of the marking groove are connected or not connected; when the epitaxial layers on two sides of the marking groove are connected, the epitaxial layers on the connected part are provided with recesses corresponding to the positions of the marking groove, and the bottoms of the recesses are higher than the surface of the substrate;
And the light reflecting layer in the marking groove is used as a mark, the marking groove is sleeved on the front side and/or the back side of the substrate to form a device functional layer, specifically, the light reflecting layer in the marking groove is used as a mark, and the marking groove is sleeved on the back side of the substrate to form the device functional layer.
Optionally, after the epitaxial layer covering the surface of the substrate is formed on the side of the substrate facing the marking groove, the step of using the reflective layer in the marking groove as a mark, and before the step of overlaying the marking groove on the back surface of the substrate to form the device functional layer, further includes:
And thinning the back surface of the substrate by taking the reflecting layer in the marking groove as a stop layer.
Optionally, the marking the reflective layer in the marking groove is used as a mark, and the marking groove is aligned on the back surface of the substrate, including:
Forming a patterned second photoetching mask layer on the back surface of the substrate according to the reflecting layer in the marking groove, wherein an opening of the second photoetching mask layer corresponds to the marking groove;
and removing the substrate exposed by the opening until the reflecting layer is exposed, so as to form an expansion hole.
Optionally, the device functional layer includes: rewiring layers;
And the reflective layer in the marking groove is used as a mark, the marking groove is sleeved on the back surface of the substrate to form a device function layer, and the device function layer further comprises a rewiring layer which comprises conductive plugs filled in the expansion holes is formed on the back surface of the substrate.
Optionally, a hard mask layer is formed on the substrate, and the forming a marking groove on the substrate includes:
forming a patterned first photoetching mask layer on the hard mask layer, wherein the first photoetching mask layer exposes preset positions of the marking grooves and covers other areas of the hard mask layer;
etching to remove the hard mask layer exposed by the first photoetching mask layer by taking the first photoetching mask layer as a mask;
And taking the first photoetching mask layer or the etched hard mask layer as a mask, removing a part of the thickness of the substrate, and forming a mark groove at the preset position.
Optionally, a reflective layer is formed on the side wall and the bottom of the marking groove, specifically, the first photo-etching mask layer and/or the etched hard mask layer are used as protective layers, and a metallization process is adopted to form the reflective layer on the side wall and the bottom of the marking groove.
Optionally, after the light reflecting layer is formed on the side wall and the bottom of the marking groove, before the epitaxial layer covering the surface of the substrate is formed on the side of the substrate facing the marking groove, the method further comprises:
and grinding and removing the first photoetching mask layer and/or the hard mask layer on the surface of the substrate.
The embodiment of the invention also provides a semiconductor structure, which comprises:
A substrate;
the side wall and the bottom of the marking groove comprise a reflecting layer;
the epitaxial layer is positioned on one side of the substrate facing the marking groove and covers the surface of the substrate;
And the device functional layer is positioned on the front surface and/or the back surface of the substrate.
Optionally, the thickness of the light reflecting layer is greater than or equal to 4nm.
Optionally, the material of the light reflecting layer is a metalization.
Optionally, when the device functional layer is located on the front surface of the substrate, the epitaxial layers on two sides of the marking groove are not connected.
Optionally, when the device functional layer is located on the back surface of the substrate, the epitaxial layers on two sides of the marking groove are connected or not connected;
When the epitaxial layers on two sides of the marking groove are connected, the epitaxial layers on the connected part are provided with depressions corresponding to the positions of the marking groove, and the bottoms of the depressions are higher than the surface of the substrate.
The embodiment of the invention also provides a packaging structure which comprises the semiconductor structure.
The embodiment of the invention also provides a chip, which comprises the semiconductor structure or the packaging structure.
The embodiment of the invention also provides an integrated circuit structure, which comprises the semiconductor structure or the packaging structure.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
The embodiment of the invention provides a semiconductor structure, a forming method and a related device, wherein the forming method of the semiconductor structure comprises the following steps: providing a substrate; forming a marking groove on the substrate; forming a reflecting layer on the side wall and the bottom of the marking groove; forming an epitaxial layer covering the surface of the substrate on one side of the substrate facing the marking groove; and taking the reflecting layer in the marking groove as a mark, and overlapping the marking groove on the front surface and/or the back surface of the substrate to form a device functional layer.
It can be seen that, in the embodiment of the invention, the marking groove is formed in the substrate, and then the reflective layer is formed on the side wall and the bottom of the marking groove, wherein when the front surface and/or the back surface of the substrate are subjected to alignment, the reflective layer in the marking groove can be used as a mark, the position of the marking groove is more obviously prompted based on the light shadow change displayed by the reflective layer, and further the photoetching alignment effect and alignment precision of crystal faces and/or crystal backs are improved, and when the back surface of the substrate is subjected to etching or grinding process, the reflective layer can be used as a stop layer, so that the stop position of crystal back etching or grinding is accurately marked, and the preparation yield of the semiconductor device is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram illustrating a semiconductor structure formed by steps in a method for forming the semiconductor structure;
fig. 2 to 13 are schematic structural diagrams corresponding to each step in the method for forming a semiconductor structure according to an embodiment of the present invention;
Fig. 14 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As known from the background art, the performance of the semiconductor device formed by the zero layer mark prepared in the prior art is poor, and the yield of the semiconductor device is affected. Now, with reference to the schematic structural diagram corresponding to each step in the method for forming a semiconductor structure shown in fig. 1, the reason for the poor performance of the semiconductor device formed by the zero layer mark is analyzed.
Specifically, referring to fig. 1, a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure is shown: first, a hard mask material layer 11 is formed on a substrate 10 to protect the substrate surface; forming a photolithography mask layer 12 on the hard mask material layer 11; removing the hard mask material layer and a portion of the thickness of the substrate exposed by the photolithographic mask layer 12 by an etching process, forming a hard mask layer 11' and a trench 13 in the substrate 10, which may be a groove having an inverted trapezoidal profile in one specific example, on the substrate 10; further, the photolithographic mask layer 12 and the hard mask layer 11' are removed; an epitaxial layer 14 is grown on the substrate 10, which epitaxial layer (EPI) may be non-selectively grown on the substrate 10.
It should be noted that during the non-selective growth of the epitaxial layer, as shown in fig. 1, the epitaxial layer is correspondingly grown in the trench in the substrate, and, due to the smaller top dimension and larger bottom dimension of the trench having the inverted trapezoid profile, as the epitaxial layer grows, a hole 15 is formed in the trench, or a step-like shape 16 corresponding to the trench is formed on the top of the epitaxial layer 14 on the trench. In the above-mentioned semiconductor structure forming process, the zero layer mark may be a hole 15 of the epitaxial layer formed in the trench, or may be a step-like feature 16 of the top of the epitaxial layer corresponding to the trench.
It can be appreciated that, no matter the trench in the substrate is in an inverted trapezoid profile or other shapes, when the epitaxial layer is non-selectively grown on the substrate, the holes in the trench gradually tend to be in a closed state along with the increase of the thickness of the epitaxial layer, and then a step-like morphology corresponding to the trench is generated at the top of the epitaxial layer. However, when the thickness of the epitaxial layer is continuously increased, the light transmittance of the voids 15 in the closed state gradually becomes worse, so that the subsequent photolithography process is gradually weakened in the ability to align through the alignment marks of the epitaxial layer and the front layer, that is: the effect of the photolithographic Alignment (Alignment) and the accuracy of the Overlay (Overlay) are degraded. In addition, as the thickness of the epitaxial layer increases, the step-like morphology 16 (i.e. zero layer mark) in fig. 1 is not obvious or disappears, so that the alignment effect of the subsequent device structure is poor, the performance of the device is further affected, and the yield of the prepared semiconductor device is low. In addition, in the wafer back process, due to the fact that the holes are smaller, refraction or reflection of the wafer back is inaccurate, the alignment effect of a subsequent device structure is poor, and due to the fact that the epitaxial layer with a certain thickness is grown on the substrate, the effect of the step-shaped zero layer mark in the wafer back process is not obvious, the alignment precision of the wafer back is affected, and the yield of the manufactured semiconductor device is reduced.
In view of this, embodiments of the present invention provide a semiconductor structure, a forming method and a related device, where the method includes: providing a substrate; forming a marking groove on the substrate; forming a reflecting layer on the side wall and the bottom of the marking groove; forming an epitaxial layer covering the surface of the substrate on one side of the substrate facing the marking groove; and taking the reflecting layer in the marking groove as a mark, and overlapping the marking groove on the front surface and/or the back surface of the substrate to form a device functional layer.
It can be seen that, in the embodiment of the invention, the marking groove is formed in the substrate, and further, the reflective layer is formed on the side wall and the bottom of the marking groove, wherein when the front surface and/or the back surface of the substrate are subjected to alignment, the reflective layer in the marking groove can be used as a mark, the position of the marking groove is more obviously prompted based on the light shadow change displayed by the reflective layer, and further, the photoetching alignment effect and the alignment precision of the crystal face and/or the crystal back are improved, and when the back surface of the substrate is subjected to the etching or grinding process, the reflective layer can be used as a stop layer, so that the stop position of the crystal back etching or grinding is accurately marked, and the preparation yield of the semiconductor device is improved.
In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 2 to 13 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 2, a substrate 100 is provided.
The substrate 100 is used to provide a process basis for forming zero layer marks.
Wherein, the materials of the substrate 100 may be silicon. In other embodiments, the material of the substrate 100 may be, for example, one or more of silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, or the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. Semiconductor devices, such as one or more of PMOS transistors, CMOS transistors, NMOS transistors, resistors, capacitors, or inductors, etc., may also be formed within the substrate 100. In a further example, an interface layer may be formed on the surface of the substrate 100, where a material of the interface layer may be, for example, silicon oxide, silicon nitride, or silicon oxynitride, and is used to isolate and protect the surface of the substrate 100.
Specifically, the substrate 100 includes opposite top and bottom surfaces, and the top surface of the substrate 100 may further include a hard mask layer 110, where the hard mask layer may be used as an interface layer and a stop layer in a subsequent process to avoid the substrate from being damaged in the subsequent process, and the hard mask layer may be made of one or more of silicon nitride, silicon oxide, or silicon oxynitride, for example. In a specific embodiment, when the materials of the hard mask layer are multiple, the hard mask layer may be a stack of multiple materials, for example, a stack of silicon nitride and silicon oxide.
Referring to fig. 3, a marking groove 120 is formed on the substrate.
Wherein the marking recess 120 is used to indicate a reference position of the device. In an alternative example, the marking grooves may be used to indicate edge locations of the device, or to indicate scribe areas of the device, etc., so that the overlay can be performed based on where the marking grooves are located during subsequent device structure formation.
In an alternative implementation, the marker grooves may be formed based on a photolithographic and etching process. Specifically, a patterned first photo-etching mask layer (not shown in the figure) may be first formed on the substrate, where the first photo-etching mask layer may expose a preset position of the marking groove and cover other areas of the substrate, and then the first photo-etching mask layer is used as a mask to etch and remove a portion of the substrate with a thickness exposed by the first photo-etching mask layer, so as to form the marking groove at the preset position.
In a specific example, if the hard mask layer 110 is formed on the surface of the substrate, a corresponding first photo-etching mask layer (not shown in the figure) is formed on the hard mask layer 110, the photo-etching mask layer exposes a preset position of the marking groove and covers other areas of the hard mask layer 110, then the first photo-etching mask layer is used as a mask, the hard mask layer 110 exposed by the first photo-etching mask layer is etched and removed, and further the first photo-etching mask layer or the etched hard mask layer is used as a mask, and a substrate with a partial thickness is removed, so that the marking groove is formed at the preset position.
The etching may be a wet etching process, a dry etching process or a process combining wet etching and dry etching, which is not particularly limited herein.
Referring to fig. 4, a reflective layer 130 is formed on the sidewalls and bottom of the marking groove 120;
The reflective layer 130 may be a structure for realizing an optical effect, so as to perform a recognition function in an alignment process of a crystal face and/or a back of the crystal. For example: when grinding or etching is carried out, determining the stop position of grinding or etching by identifying the reflecting layer; also for example: when the alignment is carried out, the positions of the marking grooves are determined through refraction or reflection light shadow of the reflecting layer, so that the alignment of the device structure is realized.
It should be noted that, based on the existence of the reflective layer, the growth of the epitaxial layer on the side wall and the bottom of the marking groove 120 can be avoided, so that the epitaxial layer is selectively grown on the surface of the substrate, and the surface of the reflective layer is selectively avoided, and in one example, the material of the reflective layer may be lattice mismatched with, or even greatly different from, the material of the epitaxial layer to be grown, so as to realize the selective growth of the epitaxial layer. The material of the light reflecting layer can be metalization, and when multiple materials are contained, the light reflecting layer can also be a lamination of multiple material layers.
In an alternative example, the thickness of the reflective layer may be greater than or equal to 4nm, so that light cannot penetrate through the reflective layer, thereby reducing transmissivity of the reflective layer, ensuring that refraction or reflection of the reflective layer can better occur, and further, when a crystal face and/or a crystal back are subjected to photoetching, the obtained reflection or refraction shadow is clearer, the overlay precision is improved, and the photoetching alignment effect is improved.
In a specific implementation, the material of the light reflecting layer is a metalate. Specifically, when the substrate is silicon, the metal silicide may be a metal silicide containing one or more of titanium (Ti), cobalt (Co), tungsten (W), nickel (Ni), manganese (Mn), indium (In), chromium (Cr), strontium (Sr), calcium (Ca), etc., so as to achieve refraction or reflection of light. The metallization may be formed by using a metallization process, and specifically, a plasma annealing method may be used to enable a sputtered metal film (such as a Ti film) to perform a solid phase reaction with the substrate exposed by the marking groove, so as to directly generate a low-resistance metallized film, i.e., a metal silicide.
It should be noted that, in order to make the reflective layer formed only on the side wall and the bottom of the marking groove, other areas of the substrate may be isolated and protected by covering a protection layer. In a specific example, when the first photolithography mask layer and the hard mask material layer are used for etching to form the mark groove, the first photolithography mask layer and/or the etched hard mask layer may be reserved, so that the first photolithography mask layer and/or the etched hard mask layer are used as a protection layer, and a process of forming an epitaxial barrier layer on the side wall and the bottom of the mark groove is performed, so that the area of the top surface of the substrate is prevented from being processed simultaneously. For example, the first photoetching mask layer and/or the etched hard mask layer are used as protective layers, and a metallization process is adopted to form a reflecting layer on the side wall and the bottom of the marking groove.
In an example where the first photolithographic mask layer and/or the hard mask layer are left, the first photolithographic mask layer and/or the hard mask layer may be further abraded to remove the light reflecting layer, referring to fig. 5.
Referring to fig. 6, an epitaxial layer 140 is formed on the side of the substrate 100 facing the marking groove 120 to cover the surface of the substrate;
The epitaxial layer 140 is used to provide a process basis for forming a corresponding device structure on the substrate 100, for example, the epitaxial layer may be used to form an alternating layer of PN junctions in BCD devices and/or superjunction devices (SJ), or the epitaxial layer may be used to form a device well region, a source drain region of a device, etc., and the invention is not specifically limited herein.
The material of the epitaxial layer can be the same as the substrate, or can be other materials lattice matched with the substrate. For example, where the substrate is silicon, the epitaxial layer may be silicon, silicon germanium, or the like. In alternative examples, the epitaxial layer may be, for example, one or more of silicon, germanium, silicon carbide, and the like.
It should be noted that, based on the existence of the reflective layer in the marking groove, the epitaxial layer may be selectively grown on the surface of the substrate, and selectively avoid the surface of the reflective layer, so that enough space can be left in the marking groove as a hole, so that when a subsequent process such as alignment is performed on the substrate, obvious light and shadow changes can be generated to embody the position of the marking groove.
In an alternative example, in the step of forming the epitaxial layer covering the surface of the substrate on the side of the substrate facing the marking groove, the epitaxial layer may be in a non-connected state on both sides of the marking groove, as shown in fig. 6, the epitaxial layer on both sides of the marking groove is in a non-connected structure, so that when the front surface of the substrate is aligned, the reflective layer 130 is light-tight and has a clear light shadow when being refracted or reflected, and the position of the marking groove can be accurately determined based on the reflective layer.
In another alternative example, when the epitaxial layer is formed on the substrate surfaces on two sides of the marking groove, the epitaxial layer has a tendency to bridge in the direction of the marking groove during the forming process. In the step of forming the epitaxial layer covering the surface of the substrate on the side of the substrate facing the marking groove, the epitaxial layer may be in a connected or disconnected state on both sides of the marking groove, as shown in fig. 6, and based on the reflection image of the reflection layer formed by the bottom and the side wall of the marking groove, which is refracted or reflected under the action of light, the reflection layer 130 may be regarded as a zero layer mark, so that the position of the marking groove is accurately determined.
Fig. 7 illustrates a structure of the epitaxial layers 140 on two sides of the marking groove when they are connected, and based on that no epitaxial layer is formed in the marking groove 120, the epitaxial layer on the connected portion has a recess 150 corresponding to the position of the marking groove while a larger hole is formed, and the bottom of the recess is higher than the surface of the substrate. In one specific example, as shown in fig. 7, the recess 150 has a greater height h, which may be represented as an inverted triangle-like morphology.
It should be noted that, referring to fig. 8, referring to fig. 7, the epitaxial layer with the predetermined thickness may be polished and removed. After the epitaxial layer is formed, the epitaxial layer with the preset thickness can be removed through a grinding process, so that the uniformity of the surface of the epitaxial layer is ensured. The polishing process may be, for example, mechanical polishing, chemical polishing, or chemical mechanical polishing.
Referring to fig. 9 to 12, the reflective layer 130 in the marking groove 120 is used as a mark, and the marking groove 120 is aligned on the front and/or back of the substrate 100, so as to form a device functional layer. Fig. 9 to 12 are schematic structural diagrams based on the structure of fig. 6.
For the crystal face process, after the epitaxial layer is formed, a process of forming a device layer structure on the front surface of the substrate can be performed based on the position marked by the zero layer mark. For example, BCD devices and/or superjunction devices (SJ) and the like may be formed layer by layer on the basis of the epitaxial layer. In a specific example, the reflective layer is opaque, and has a clear light shadow when the reflective layer is refracted or reflected, so that the reflective layer in the marking groove can be used as a mark, and the marking groove is aligned on the front surface of the substrate, so that a device functional layer is formed.
In an alternative example, referring to fig. 9, the device functional layer may include a crystal plane functional layer 160, and in a specific example, the crystal plane functional layer 160 may be formed on the epitaxial layer 140 with the light reflecting layer 130 within the marking groove 120 as a marking.
The crystal plane functional layer 160 is a layer structure required for realizing the function of the device on the substrate of the wafer, and different device structures can be formed based on different layer structures.
It should be noted that, referring to fig. 10, as the functional requirements of the semiconductor integrated circuit are higher and higher, the carrier substrate 170 is further bonded on the crystal plane functional layer 160 by using a bonding process, and the carrier substrate 170 may be a substrate corresponding to another chip structure. Wherein a bonding interface exists between the crystal plane functional layer 160 and the carrier substrate 170.
For the wafer back process, after the epitaxial layer is formed, a process of forming a device layer structure on the back side of the substrate may be performed based on the zero layer mark. In a specific example, the reflective layer formed on the bottom and the side wall of the marking groove is used as a mark, and the marking groove is arranged on the back surface of the substrate in an overlapping manner to form a device functional layer based on the reflection or reflection light shadow of the reflective layer formed on the bottom and the side wall of the marking groove under the action of illumination.
It can be appreciated that in performing the back-of-the-wafer overlay process, the back surface of the substrate needs to be thinned in order to achieve the effects of reducing the device resistance, reducing the power consumption, and the like. Based on the reflection layer exhibiting a light shadow variation, in an alternative example, referring to fig. 11, the back surface of the substrate 100 may be thinned with the reflection layer 130 in the marking groove 120 as a stop layer. The thinning of the back surface of the substrate 100 may be performed using, for example, a polishing process, which may be, for example, mechanical polishing, chemical polishing, or Chemical Mechanical Polishing (CMP).
In the process of using the reflective layer 130 in the marking groove 120 as a mark and aligning the marking groove 120 on the back surface of the substrate 100, as an alternative implementation, referring to fig. 12, according to the reflective layer 130 in the marking groove 120, a patterned second photolithography mask layer (not shown in the drawing) is formed on the back surface of the substrate 100, where an opening of the second photolithography mask layer (not shown in the drawing) corresponds to the marking groove 120;
The position of the marking groove can be determined through the light and shadow refracted by the reflecting layer, and then an opening corresponding to the marking groove is formed on the back surface of the substrate, so that a process foundation is provided for forming different device structures. In one example, the opening may be formed by a photolithographic process. Specifically, a photoresist mask may be formed on the back surface of the substrate, and the photoresist mask may be formed through photolithography and development processes, so that a region of the back surface of the substrate corresponding to the marking groove may be exposed.
And removing the substrate 100 exposed by the opening until the reflective layer 130 is exposed, thereby forming an expansion hole 180.
The expansion hole 180 may be formed through an etching process. The etching process may be wet etching, dry etching or a combination of wet etching and dry etching, which is not particularly limited herein.
In the example of fig. 12, after the expansion hole is formed, the second photolithography mask layer (not shown in the drawing) may be further removed. In a specific example, the second photolithographic masking layer may be removed using a milling process.
In an alternative example, the device functional layer may include a rewiring layer (RDL). In the back-of-the-line process, a re-wiring layer may be used as an interface between the chip and the package, and the material of the re-wiring layer may be a conductive material, such as copper (Cu), through which a different device layer structure can be connected to the back side of the substrate.
Further, in an example of reserving the expansion holes 180, referring to fig. 13, a re-wiring layer 190 may be further formed on the back surface of the substrate 100, the re-wiring layer 190 including conductive plugs 200 filled in the expansion holes.
The re-wiring layer 190 may be a conductive layer structure formed on the back surface of the substrate based on a sputtering process, and the re-wiring layer can fill the expansion hole based on the existence of the expansion hole on the back surface of the substrate to form the conductive plug 200, thereby realizing the electrical connection of the device layer structure.
It should be noted that, in the embodiment of the present invention, the material of the reflective layer 130 is a metallization, so that when the formed conductive plug is connected with the reflective layer, diffusion of metal ions in the substrate can be effectively inhibited, thereby reducing the contact resistance of the device.
It can be seen that, in the embodiment of the invention, the marking groove is formed in the substrate, and then the reflective layer is formed on the side wall and the bottom of the marking groove, wherein when the front surface and/or the back surface of the substrate are subjected to alignment, the reflective layer in the marking groove can be used as a mark, the position of the marking groove is more obviously prompted based on the light shadow change displayed by the reflective layer, and further the photoetching alignment effect and alignment precision of crystal faces and/or crystal backs are improved, and when the back surface of the substrate is subjected to etching or grinding process, the reflective layer can be used as a stop layer, so that the stop position of crystal back etching or grinding is accurately marked, and the preparation yield of the semiconductor device is improved.
In another embodiment of the present invention, a semiconductor structure is provided, which may be formed based on the method described above, and referring to fig. 14, which is an alternative structural schematic diagram of the semiconductor structure, the semiconductor structure includes:
A substrate 300; a marking groove 310 positioned on the substrate 300, wherein a sidewall and a bottom of the marking groove 310 include a light reflecting layer 320; an epitaxial layer 330 located on the side of the substrate 300 facing the marking groove 310, and covering the surface of the substrate; a device functional layer 340 on the front side and/or a device functional layer 350 on the back side of the substrate 300.
Wherein, the materials of the substrate 300 may be silicon. In other embodiments, the material of the substrate 300 may be, for example, one or more of silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, or the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. The substrate 300 may also have formed therein a semiconductor device, such as one or more of a PMOS transistor, a CMOS transistor, an NMOS transistor, a resistor, a capacitor, or an inductor, etc. In a further example, the surface of the substrate 300 may further be formed with an interface layer, and the material of the interface layer may be, for example, silicon oxide, silicon nitride, or silicon oxynitride, etc., for isolating and protecting the surface of the substrate 300.
The marking recess 310 is used to indicate the reference position of the device. For example, in the wafer back process, the edge position of the device may be indicated by the marking groove, or the scribe area of the device may be indicated, so that the alignment can be performed based on the position where the marking groove is located when the device structure is formed later.
The reflective layer 320 may be a structure for achieving an optical effect, and may perform a recognition function during back alignment. For example: when the crystal back grinding or etching is carried out, determining the stop position of the crystal back grinding or etching by identifying the reflecting layer; also for example: when the back of the crystal is aligned, the position of the marking groove is determined through the refraction of the reflecting layer or the reflection light shadow so as to realize the alignment of the device structure.
In an alternative example, the thickness of the reflective layer is greater than or equal to 4nm, so that the reflective layer can be better refracted or reflected, and the obtained reflection or refracted light shadow is clearer when photoetching is performed on the back of the wafer, so that the alignment precision of the back of the wafer is improved, and the photoetching alignment effect is improved. When the back-of-body lithography is performed, light cannot penetrate through the reflecting layer, the transmissivity of the reflecting layer is reduced, and the definition of reflection or refraction shadow of the reflecting layer is ensured.
In a specific implementation, the material of the light reflecting layer may be a metallization. Specifically, when the substrate is silicon, the metallization may be a metal silicide doped with one or more of titanium (Ti), cobalt (Co), tungsten (W), nickel (Ni), manganese (Mn), indium (In), chromium (Cr), strontium (Sr), calcium (Ca), etc., so as to achieve refraction or reflection of light.
The epitaxial layer 330 is used to provide a process basis for forming a corresponding device structure on the substrate 300, for example, the epitaxial layer may be used to form an alternating layer of PN junctions in BCD devices and/or superjunction devices (SJ), or the epitaxial layer may be used to form a device well region, a source drain region of a device, etc., the invention is not specifically limited herein.
The material of the epitaxial layer can be the same as the substrate, or can be other materials lattice matched with the substrate. For example, where the substrate is silicon, the epitaxial layer may be silicon, silicon germanium, or the like. In alternative examples, the epitaxial layer may be, for example, one or more of silicon, germanium, and the like.
It should be noted that, based on the existence of the reflective layer in the marking groove, the epitaxial layer may be selectively grown on the surface of the substrate, and selectively avoid the surface of the reflective layer, so that enough space can be left in the marking groove as a hole, and thus, when the subsequent process such as alignment is performed on the substrate, obvious light and shadow changes can be generated, so as to embody the position of the marking groove. Thus, the marking groove with the light reflecting layer can be used as a zero layer marking to form a device layer structure.
In an alternative example, if the reflective layer in the marking groove is used as a mark, when the marking groove is aligned on the front surface of the substrate, the two sides of the epitaxial layer on the marking groove may be in a non-connected state, and when the alignment is performed on the front surface of the substrate, the reflective layer is opaque and has a clear light shadow when the reflective layer refracts or reflects, so that the reflective layer can be regarded as a zero layer mark aligned by lithography, and the position of the marking groove is accurately determined based on the reflective layer.
In another optional example, when the epitaxial layer is formed on the substrate surfaces on two sides of the marking groove, the epitaxial layer has a tendency to close the marking groove towards the direction of the marking groove in the forming process, if the reflective layer in the marking groove is used as a mark, when the marking groove is aligned on the back of the substrate, the epitaxial layer can be in a state of being connected or not connected on two sides of the marking groove, and based on the light and shadow of refraction or reflection of the reflective layer formed on the bottom and the side wall of the marking groove under the action of illumination, the reflective layer can be regarded as a zero layer mark when the photoetching alignment and alignment of the wafer back are performed, so that the position of the marking groove can be accurately determined. And based on the existence of the reflecting layer, the reflecting layer can be used as an etching stopping layer to indicate the etching stopping position of the substrate when the substrate is thinned in the wafer back process.
When the epitaxial layers on two sides of the marking groove are connected, the epitaxial layers are not formed in the marking groove, and meanwhile, the epitaxial layers on the connected part are provided with pits corresponding to the positions of the marking groove when larger holes are formed, and the bottoms of the pits are higher than the surface of the substrate. In one specific example, the depressions have a greater height and may exhibit an inverted triangle-like morphology.
The device functional layer 340 located on the front side of the substrate 300 and the device functional layer 350 located on the back side of the substrate 300 are layer structures required for implementing device functions, different device structures can be formed based on different layer structures, the device functional layer 340 may be, for example, a crystal face functional layer, etc., and the device functional layer 350 may be, for example, a crystal back functional layer, etc. The crystal face functional layer can be a device structure formed on the basis of the front face of the substrate, and the functional requirement of the semiconductor integrated circuit is higher and higher, so that the bearing substrate is further bonded on the crystal face functional layer; the back-of-the-crystal functional layer may be a device structure formed on the basis of the back surface of the substrate, and in an alternative example, the back-of-the-crystal functional layer may be formed on the basis of the thinned back surface of the substrate; in one specific example, the back-of-the-crystal functional layer may be a rewiring layer for implementing a bonding process on the back side of the substrate. Wherein, the back surface of the substrate 300 has an expansion hole exposing the reflective layer 320, when a re-wiring layer is formed on the back surface of the substrate, the re-wiring layer can fill the expansion hole to form a conductive plug 360, and the reflective layer 320 is made of a metal, so that diffusion of metal ions in the substrate can be effectively inhibited.
It should be noted that, in the above semiconductor structure, reference may be made to corresponding descriptions of method portions, and each portion associated with the description may be referred to correspondingly, which is not repeated herein.
It can be understood that, according to the embodiment of the invention, the marking groove is formed in the substrate, and the reflective layer is formed on the side wall and the bottom of the marking groove, wherein when the front surface and/or the back surface of the substrate are subjected to alignment, the reflective layer in the marking groove can be used as a mark, the position of the marking groove is more obviously prompted based on the light shadow change displayed by the reflective layer, and therefore the photoetching alignment effect and alignment precision of crystal faces and/or crystal backs are improved, and when the back surface of the substrate is subjected to the etching or grinding process, the reflective layer can be used as a stop layer to accurately mark the stop position of crystal back etching or grinding, so that the preparation yield of the semiconductor device is further improved.
In a further embodiment of the present invention, a package structure is also provided, where the package structure may include the semiconductor structure provided in the above embodiment.
In a further embodiment of the present invention, a chip is also provided, which may include the semiconductor structure provided in the above embodiment, or in a further example, the chip may include the package structure provided in the above embodiment.
In a further embodiment of the present invention, an integrated circuit structure is also provided, which may include the semiconductor structure provided in the above embodiment, or in a further example, the integrated circuit structure may include the package structure provided in the above embodiment.
The foregoing describes several embodiments of the present invention, and the various alternatives presented by the various embodiments may be combined, cross-referenced, with each other without conflict, extending beyond what is possible embodiments, all of which are considered to be embodiments of the present invention disclosed and disclosed.
Although the embodiments of the present invention are disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (18)
1. A method of forming a semiconductor structure, comprising:
Providing a substrate;
forming a marking groove on the substrate;
forming a reflecting layer on the side wall and the bottom of the marking groove, wherein the reflecting layer is made of metal silicide, and the reflecting layer adopts a plasma annealing method to enable a sputtered metal film to generate a solid phase reaction with a substrate exposed by the marking groove to generate the metal silicide;
forming an epitaxial layer covering the surface of the substrate on one side of the substrate facing the marking groove;
The reflective layer in the marking groove is used as a mark, and the marking groove is sleeved on the front side and/or the back side of the substrate to form a device functional layer;
the reflective layer is used as a stop layer for marking the etching or grinding stop position of the back surface of the substrate.
2. The method of claim 1, wherein the thickness of the light reflective layer is greater than or equal to 4nm.
3. The method of claim 1, wherein in the step of forming an epitaxial layer on a side of the substrate facing the marking groove, the epitaxial layers on both sides of the marking groove are not connected;
And the light reflecting layer in the marking groove is used as a mark, the marking groove is sleeved on the front surface and/or the back surface of the substrate to form a device functional layer, specifically, the light reflecting layer in the marking groove is used as a mark, and the marking groove is sleeved on the front surface of the substrate to form the device functional layer.
4. The method of forming a semiconductor structure of claim 3, wherein the device functional layer comprises: a crystal face functional layer;
and the reflecting layer in the marking groove is used as a mark, the marking groove is sleeved on the front surface of the substrate to form a device functional layer, specifically, the reflecting layer in the marking groove is used as a mark, and a crystal face functional layer is formed on the epitaxial layer.
5. The method according to claim 1, wherein in the step of forming an epitaxial layer covering the surface of the substrate on a side of the substrate facing the marking groove, the epitaxial layers on both sides of the marking groove are connected or not connected; when the epitaxial layers on two sides of the marking groove are connected, the epitaxial layers on the connected part are provided with recesses corresponding to the positions of the marking groove, and the bottoms of the recesses are higher than the surface of the substrate;
And the light reflecting layer in the marking groove is used as a mark, the marking groove is sleeved on the front side and/or the back side of the substrate to form a device functional layer, specifically, the light reflecting layer in the marking groove is used as a mark, and the marking groove is sleeved on the back side of the substrate to form the device functional layer.
6. The method of claim 5, wherein after forming an epitaxial layer covering the surface of the substrate on a side of the substrate facing the marking groove, the step of using the reflective layer in the marking groove as a mark, and before forming a device functional layer by patterning the marking groove on the back surface of the substrate, further comprises:
And thinning the back surface of the substrate by taking the reflecting layer in the marking groove as a stop layer.
7. The method of claim 6, wherein the patterning the marking recess on the back surface of the substrate with the reflective layer in the marking recess as a mark comprises:
Forming a patterned second photoetching mask layer on the back surface of the substrate according to the reflecting layer in the marking groove, wherein an opening of the second photoetching mask layer corresponds to the marking groove;
and removing the substrate exposed by the opening until the reflecting layer is exposed, so as to form an expansion hole.
8. The method of forming a semiconductor structure of claim 7, wherein the device functional layer comprises: rewiring layers;
And the reflective layer in the marking groove is used as a mark, the marking groove is sleeved on the back surface of the substrate to form a device function layer, and the device function layer further comprises a rewiring layer which comprises conductive plugs filled in the expansion holes is formed on the back surface of the substrate.
9. The method of claim 1, wherein the forming a hard mask layer on the substrate, the forming a mark recess on the substrate, comprises:
forming a patterned first photoetching mask layer on the hard mask layer, wherein the first photoetching mask layer exposes preset positions of the marking grooves and covers other areas of the hard mask layer;
etching to remove the hard mask layer exposed by the first photoetching mask layer by taking the first photoetching mask layer as a mask;
And taking the first photoetching mask layer or the etched hard mask layer as a mask, removing a part of the thickness of the substrate, and forming a mark groove at the preset position.
10. The method of claim 9, wherein the forming a reflective layer on the sidewall and the bottom of the marking groove, specifically, forming a reflective layer on the sidewall and the bottom of the marking groove by using the first photolithography mask layer and/or the etched hard mask layer as a protective layer and adopting a metallization process.
11. The method of claim 10, wherein after forming the reflective layer on the sidewall and the bottom of the marking groove, the forming an epitaxial layer covering the surface of the substrate on the side of the substrate facing the marking groove further comprises:
and grinding and removing the first photoetching mask layer and/or the hard mask layer on the surface of the substrate.
12. A semiconductor structure, comprising:
A substrate;
The side wall and the bottom of the marking groove comprise a reflecting layer, wherein the reflecting layer is made of metal silicide, and the reflecting layer adopts a plasma annealing method to enable a sputtered metal film to perform solid phase reaction with the substrate exposed by the marking groove to generate the metal silicide;
the epitaxial layer is positioned on one side of the substrate facing the marking groove and covers the surface of the substrate;
the device functional layer is positioned on the front side and/or the back side of the substrate, and is formed by taking the reflecting layer in the marking groove as a mark and overlapping the marking groove;
the reflective layer is used as a stop layer for marking the etching or grinding stop position of the back surface of the substrate.
13. The semiconductor structure of claim 12, wherein the thickness of the light reflective layer is greater than or equal to 4nm.
14. The semiconductor structure of claim 12, wherein when the device functional layer is on the front side of the substrate, the epitaxial layers on both sides of the marker recess do not meet.
15. The semiconductor structure of claim 12, wherein when the device functional layer is on the back side of the substrate, the epitaxial layers on both sides of the marking recess are connected or not connected;
When the epitaxial layers on two sides of the marking groove are connected, the epitaxial layers on the connected part are provided with depressions corresponding to the positions of the marking groove, and the bottoms of the depressions are higher than the surface of the substrate.
16. A package structure, characterized in that the package structure comprises the semiconductor structure of any one of claims 12 to 15.
17. A chip, characterized in that it comprises the semiconductor structure of any one of claims 12 to 15 or the package structure of claim 16.
18. An integrated circuit structure comprising the semiconductor structure of any one of claims 12 to 15, or the package structure of claim 16.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310674827.XA CN116682724B (en) | 2023-06-08 | 2023-06-08 | Semiconductor structure, forming method and related device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310674827.XA CN116682724B (en) | 2023-06-08 | 2023-06-08 | Semiconductor structure, forming method and related device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116682724A CN116682724A (en) | 2023-09-01 |
| CN116682724B true CN116682724B (en) | 2024-04-26 |
Family
ID=87786809
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310674827.XA Active CN116682724B (en) | 2023-06-08 | 2023-06-08 | Semiconductor structure, forming method and related device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116682724B (en) |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1399325A (en) * | 2001-07-19 | 2003-02-26 | 三洋电机株式会社 | Semiconductor device and its manufacture |
| US6583030B1 (en) * | 1998-11-20 | 2003-06-24 | Giesecke & Devrient Gmbh | Method for producing an integrated circuit processed on both sides |
| CN102386168A (en) * | 2010-09-02 | 2012-03-21 | 台湾积体电路制造股份有限公司 | Alignment marks in substrate having through-substrate via |
| CN102800566A (en) * | 2012-07-16 | 2012-11-28 | 中国电子科技集团公司第五十五研究所 | Method for protecting alignment mark through contact area lead wire process in semiconductor device |
| CN103811407A (en) * | 2012-11-06 | 2014-05-21 | 上海华虹宏力半导体制造有限公司 | Technique method for patterning back surface of silicon wafer |
| JP2016018807A (en) * | 2014-07-04 | 2016-02-01 | 富士通セミコンダクター株式会社 | Semiconductor device and manufacturing method of the same |
| CN112018082A (en) * | 2019-05-31 | 2020-12-01 | 芯恩（青岛）集成电路有限公司 | Method for preparing overlay alignment mark and structure thereof |
| CN112563246A (en) * | 2020-12-18 | 2021-03-26 | 河源市众拓光电科技有限公司 | Photoetching overlay mark and preparation method thereof |
| CN115621135A (en) * | 2021-07-15 | 2023-01-17 | 中芯国际集成电路制造(北京)有限公司 | Packaging method and packaging structure |
| CN116072519A (en) * | 2023-01-31 | 2023-05-05 | 上海积塔半导体有限公司 | Photoetching process method |
-
2023
- 2023-06-08 CN CN202310674827.XA patent/CN116682724B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6583030B1 (en) * | 1998-11-20 | 2003-06-24 | Giesecke & Devrient Gmbh | Method for producing an integrated circuit processed on both sides |
| CN1399325A (en) * | 2001-07-19 | 2003-02-26 | 三洋电机株式会社 | Semiconductor device and its manufacture |
| CN102386168A (en) * | 2010-09-02 | 2012-03-21 | 台湾积体电路制造股份有限公司 | Alignment marks in substrate having through-substrate via |
| CN102800566A (en) * | 2012-07-16 | 2012-11-28 | 中国电子科技集团公司第五十五研究所 | Method for protecting alignment mark through contact area lead wire process in semiconductor device |
| CN103811407A (en) * | 2012-11-06 | 2014-05-21 | 上海华虹宏力半导体制造有限公司 | Technique method for patterning back surface of silicon wafer |
| JP2016018807A (en) * | 2014-07-04 | 2016-02-01 | 富士通セミコンダクター株式会社 | Semiconductor device and manufacturing method of the same |
| CN112018082A (en) * | 2019-05-31 | 2020-12-01 | 芯恩（青岛）集成电路有限公司 | Method for preparing overlay alignment mark and structure thereof |
| CN112563246A (en) * | 2020-12-18 | 2021-03-26 | 河源市众拓光电科技有限公司 | Photoetching overlay mark and preparation method thereof |
| CN115621135A (en) * | 2021-07-15 | 2023-01-17 | 中芯国际集成电路制造(北京)有限公司 | Packaging method and packaging structure |
| CN116072519A (en) * | 2023-01-31 | 2023-05-05 | 上海积塔半导体有限公司 | Photoetching process method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116682724A (en) | 2023-09-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4307664B2 (en) | Semiconductor device | |
| US10157914B2 (en) | Multi-layer semiconductor device structure | |
| US8937359B2 (en) | Contact formation for ultra-scaled devices | |
| US7393737B2 (en) | Semiconductor device and a method of manufacturing the same | |
| TW201935660A (en) | Fin patterning for advanced integrated circuit structure fabrication | |
| US9520339B2 (en) | Semiconductor device and method of manufacturing the same | |
| TW201926473A (en) | Continuous gate and fin spacer for advanced integrated circuit structure fabrication | |
| US7910423B2 (en) | Semiconductor device and method of manufacturing the same | |
| US7169654B2 (en) | Method of forming a semiconductor device | |
| US10424513B2 (en) | Semiconductor device | |
| US5891808A (en) | Method for fabricating a die seal | |
| US20080171419A1 (en) | Method for forming SOI device | |
| KR20070116986A (en) | A non-critical complementary masking method for poly-1 definition in flash memory device fabrication | |
| US8237297B2 (en) | System and method for providing alignment mark for high-k metal gate process | |
| EP1020916A2 (en) | Method for making an integrated circuit including alignment marks | |
| CN116913897B (en) | Semiconductor structure, forming method thereof and related device | |
| CN116682724B (en) | Semiconductor structure, forming method and related device | |
| CN113206142A (en) | Integrated chip | |
| KR20040085912A (en) | Manufacturing method for semiconductor device | |
| US6436789B2 (en) | Method of forming a device separation region | |
| JP4398420B2 (en) | Manufacturing method of semiconductor device | |
| US20200357765A1 (en) | Method of manufacturing semiconductor device | |
| KR20050002443A (en) | Manufacturing method for semiconductor device | |
| US20230135946A1 (en) | Self-Aligned Gate Contact Fin Field Effect Transistor and Method for Manufacturing the Same | |
| US20230253322A1 (en) | Nano-tsv landing over buried power rail |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |