CN115621135A - Packaging method and packaging structure - Google Patents

Packaging method and packaging structure Download PDF

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Publication number
CN115621135A
CN115621135A CN202110802874.9A CN202110802874A CN115621135A CN 115621135 A CN115621135 A CN 115621135A CN 202110802874 A CN202110802874 A CN 202110802874A CN 115621135 A CN115621135 A CN 115621135A
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China
Prior art keywords
layer
dielectric layer
substrate
marking
groove
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Chinese (zh)
Inventor
马慧琳
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202110802874.9A priority Critical patent/CN115621135A/en
Publication of CN115621135A publication Critical patent/CN115621135A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment

Abstract

A packaging method and a packaging structure are provided, the packaging method comprises the following steps: providing a first device wafer, wherein the first device wafer comprises a first substrate and a first dielectric layer positioned on the first substrate, and the first device wafer comprises a marking area; forming a groove in the first dielectric layer in the mark region; forming a first marking layer in the groove, wherein the material of the first marking layer is a material containing metal elements; providing a second device wafer, wherein the second device wafer comprises a second substrate and a second dielectric layer positioned on the second substrate, a second marking layer is formed in the surface of the second dielectric layer, which faces away from the first substrate, and the material of the second marking layer is a material containing metal elements; and arranging the second dielectric layer and the first dielectric layer oppositely, aligning the second mark layer and the first mark layer with each other, and realizing the bonding of the second dielectric layer and the first dielectric layer through a bonding process. The accurate alignment of the first mark layer and the second mark layer can be realized, so that the packaging yield is further improved.

Description

Packaging method and packaging structure
Technical Field
The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a packaging method and a packaging structure.
Background
With the trend of very large scale integrated circuits, the feature size of the integrated circuits is continuously decreasing, and the requirements of people on the packaging technology of the integrated circuits are also increasing correspondingly. Conventional packaging technologies include Ball Grid Array (BGA), chip Scale Package (CSP), wafer Level Package (WLP), three-dimensional Package (3D), system In Package (SiP), and the like.
At present, in order to meet the objectives of lower cost, more reliability, faster performance and higher density of integrated circuit packaging, an advanced packaging method mainly adopts Wafer Level Package System In Package (WLPSiP), and compared with the conventional System packaging, the Wafer Level System packaging completes a packaging integration process on a Wafer, so that the Wafer Level System packaging has the advantages of greatly reducing the area of a packaging structure, reducing the manufacturing cost, optimizing the electrical performance, manufacturing in batches and the like, and can obviously reduce the workload and the requirements of equipment.
Wafer level system packaging mainly includes two important processes, namely physical connection and electrical connection, and usually a bonding method is adopted to realize physical connection between the device wafer and a chip to be integrated, and electrical connection between semiconductor devices is realized through a through hole etching process (for example, a through silicon via etching process) and an electroplating technology.
Disclosure of Invention
The embodiment of the invention provides a packaging method and a packaging structure, which are beneficial to further improving the packaging yield.
To solve the above problems, the present invention provides a package structure, including: a first device wafer comprising a first substrate and a first dielectric layer on the first substrate, the first device wafer comprising a marker region; the groove is positioned in the marking area and positioned in the surface of the first dielectric layer, which faces away from the first substrate; the first marking layer is positioned in the groove, and the material of the first marking layer is a material containing a metal element; and the second device wafer is bonded with the first device wafer and comprises a second substrate and a second dielectric layer positioned on the second substrate, wherein a second marking layer is formed in the surface, facing away from the second substrate, of the second dielectric layer, the second marking layer is made of a material containing a metal element, the second dielectric layer and the first dielectric layer are oppositely arranged and bonded, and the second marking layer and the first marking layer are aligned with each other.
Correspondingly, an embodiment of the present invention further provides a packaging method, including: providing a first device wafer, wherein the first device wafer comprises a first substrate and a first dielectric layer positioned on the first substrate, and the first device wafer comprises a marking area; forming a recess in the first dielectric layer in the mark region; forming a first marking layer in the groove, wherein the material of the first marking layer is a material containing metal elements; providing a second device wafer, wherein the second device wafer comprises a second substrate and a second dielectric layer located on the second substrate, a second marking layer is formed in the surface, facing away from the second substrate, of the second dielectric layer, and the material of the second marking layer is a material containing a metal element; and arranging the second dielectric layer opposite to the first dielectric layer, aligning the second mark layer and the first mark layer with each other, and bonding the second dielectric layer and the first dielectric layer through a bonding process.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
the embodiment of the invention provides a packaging method, wherein a groove is formed in a first dielectric layer in a mark area; forming a first marking layer in the groove, wherein the material of the first marking layer is a material containing a metal element; providing a second device wafer, wherein the second device wafer comprises a second substrate and a second dielectric layer positioned on the second substrate, a second marking layer is formed in the surface of the second dielectric layer, which faces away from the second substrate, and the material of the second marking layer is a material containing metal elements; and arranging the second dielectric layer opposite to the first dielectric layer, aligning the second mark layer with the first mark layer, and bonding the second dielectric layer and the first dielectric layer by a bonding process. Compared with the scheme that the first dielectric layer exposed out of the groove is used as the first mark layer at present, in the embodiment of the invention, after the groove is formed in the first dielectric layer, the first mark layer is formed at the bottom and the side wall of the groove, and the material of the first mark layer is the material containing the metal element.
Drawings
Fig. 1 to 2 are schematic structural diagrams corresponding to respective steps in a packaging method;
FIG. 3 is a schematic structural diagram of an embodiment of a package structure of the present invention;
fig. 4 to fig. 11 are schematic structural diagrams corresponding to steps in an embodiment of the packaging method of the present invention.
Detailed Description
The yield of the current packaging structure needs to be improved. The reason why the yield of the package structure needs to be improved is analyzed in combination with a forming method of the package structure.
Fig. 1 to fig. 2 are schematic structural diagrams corresponding to steps in a packaging method.
Referring to fig. 1, a first device wafer is provided, the first device wafer including a first substrate 10 and a first dielectric layer 11 on the first substrate 10, the first device wafer including a mark region 10A; a recess 12 is formed in the first dielectric layer 11 in the mark region 10A.
Wherein, the exposed part of the first dielectric layer 11 in the groove 12 is used as a first mark layer.
Referring to fig. 2, a second device wafer is provided, where the second device wafer includes a second substrate 20 and a second dielectric layer 21 located on the second substrate 20, a second mark layer 22 is formed in a surface of the second dielectric layer 21 facing away from the second substrate 20, and a material of the second mark layer 22 is a material containing a metal element.
With continued reference to fig. 2, the second dielectric layer 21 is disposed opposite to the first dielectric layer 11, and the second mark layer 22 and the groove 12 are aligned with each other, and the bonding of the second dielectric layer 21 and the first dielectric layer 11 is achieved through a bonding process.
It is found that, a portion of the first dielectric layer 11 exposed in the recess 12 serves as a first mark layer, a material of the first mark layer is a dielectric material, and a material of the second mark layer 22 is a metal-containing material, so that, in a bonding process between the second dielectric layer 21 and the first dielectric layer 11, since a reflectivity of the metal-containing material is higher than a reflectivity of the dielectric material, a process machine cannot accurately identify the first mark layer during the bonding process, and further the recess 12 and the second mark layer 22 cannot be precisely aligned (as shown by a dashed circle in fig. 2), thereby reducing a package yield.
In order to solve the technical problem, an embodiment of the present invention provides a package structure, including: providing a first device wafer, wherein the first device wafer comprises a first substrate and a first dielectric layer positioned on the first substrate, and the first device wafer comprises a marking area; forming a recess in the first dielectric layer in the mark region; forming a first marking layer in the groove, wherein the material of the first marking layer is a material containing a metal element; providing a second device wafer, wherein the second device wafer comprises a second substrate and a second dielectric layer located on the second substrate, a second marking layer is formed in a surface, opposite to the first substrate, of the second dielectric layer, and the second marking layer is made of a material containing a metal element; and arranging the second dielectric layer opposite to the first dielectric layer, aligning the second mark layer and the first mark layer with each other, and bonding the second dielectric layer and the first dielectric layer through a bonding process.
Compared with the scheme that the first dielectric layer exposed out of the groove is used as the first mark layer at present, in the embodiment of the invention, after the groove is formed in the first dielectric layer, the first mark layer is formed at the bottom and the side wall of the groove, and the material of the first mark layer is the material containing the metal element.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 3 is a schematic structural diagram of an embodiment of a package structure of the invention.
The packaging structure comprises: a first device wafer 60 comprising a first substrate (not labeled) and a first dielectric layer 201 on the first substrate, the first device wafer 60 comprising a marking region 200A; a groove 202 in the mark region 200A and in a surface of the first dielectric layer 201 facing away from the first substrate; the first mark layer 208 is located in the groove 202, and the material of the first mark layer 208 is a material containing a metal element; a second device wafer 61 bonded to the first device wafer 60, where the second device wafer 61 includes a second substrate (not labeled) and a second dielectric layer 210 located on the second substrate, a second mark layer 212 is formed in a surface of the second dielectric layer 210 facing away from the second substrate, the second mark layer 212 is made of a metal-containing material, the second dielectric layer 210 is disposed opposite to and bonded to the first dielectric layer 201, and the second mark layer 212 and the first mark layer 201 are aligned with each other.
In the embodiment, the first mark layer 208 is disposed in the groove 202, and the material of the first mark layer 208 is a material containing a metal element, and since the material containing the metal element has a strong reflectivity, the process tool can accurately identify the first mark layer 208 and the second mark layer 212, so as to achieve precise alignment between the first mark layer 208 and the second mark layer 212, thereby further improving the packaging yield.
In this embodiment, the package structure is a wafer level package structure, so that the package efficiency and reliability of obtaining the package structure are improved.
The first device wafer 60 is a wafer on which device fabrication is completed, and the first device wafer 60 may be fabricated using integrated circuit fabrication techniques.
In this embodiment, the first base includes a first substrate 200, devices such as an NMOS device and a PMOS device formed on the first substrate 200 by deposition, etching, and other processes, and structures such as a dielectric layer and a metal interconnection line formed on the devices.
It should be noted that, for convenience of illustration, in this embodiment, the first base only illustrates the first substrate 200, and devices formed on the first substrate 200 are not shown.
In this embodiment, the first device wafer 60 includes a mark region 200A.
The mark region 200A is a region where the first device wafer 60 and the second device wafer 61 can be aligned.
For convenience of illustration, in the present embodiment, a marking region 200A in the first device wafer 60 is taken as an example for description. In other embodiments, the number of marking regions in the first device wafer 60 is not limited to one.
In this embodiment, the first substrate 200 of the first device wafer 60 is a silicon substrate. In other embodiments, the material of the first substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the first substrate may also be a silicon-on-insulator substrate or another type of substrate such as a germanium-on-insulator substrate. The material of the first substrate may be a material suitable for process requirements or easy integration.
In this embodiment, the first substrate has a first front surface (not shown) and a first back surface (not shown) opposite to each other. Wherein the first front side refers to: the side of the first base facing away from the first substrate 200; the first back surface means: the bottom surface of the first substrate 200, i.e., the surface of the first substrate 200 that is exposed.
The first dielectric layer 201 serves as one of bonding layers for bonding the first device wafer 60 and the second device wafer 61, and the first dielectric layer 201 is further used for providing a process foundation for the groove 202.
The material of the first dielectric layer 201 is a dielectric material, and therefore, the first device wafer 60 and the second device wafer 61 are bonded by fusion bonding (fusion bonding).
In this embodiment, the material of the first dielectric layer 201 includes SiO 2 SiN and SiON.
In this embodiment, in the first device wafer 60, the first dielectric layer 201 is located on the first backside.
In this embodiment, the groove is located in the mark region 200A and located in a surface of the first dielectric layer 201 facing away from the first substrate.
The recess 202 provides a spatial location for the formation of the first marker layer 208.
It should be noted that the depth of the groove 202 is not too large or too small. If the depth of the groove 202 is too large, in the formation process of the semiconductor structure, the related etching process of the groove 202 is easy to damage the device at the bottom of the groove 202 and the first substrate 200, thereby affecting the performance of the semiconductor structure; if the depth of the groove 202 is too small, the etching process of the first mark layer 208 in the groove 202 is not easy to control during the formation process of the semiconductor structure of the first mark layer 208, thereby affecting the alignment effect of the first mark layer 208 and the second mark layer 212. For this reason, in the present embodiment, the depth of the groove 202 is 2000 to 5000 angstroms. For example, the depth of the recess 202 is 2500 angstroms, 3000 angstroms or 4000 angstroms.
In this embodiment, the first mark layer 208 is located in the groove, so that the surface of the first dielectric layer 201 facing away from the first substrate exposes the first mark layer 208, so that the first mark layer 208 can be accurately identified by a process tool of a bonding process during the bonding process between the first device wafer 60 and the second device wafer 61.
Moreover, the material of the first mark layer 208 is a material containing a metal element, and since the material containing a metal element has a strong reflectivity, in the bonding process of the first device wafer 60 and the first device wafer 60, a process machine of the bonding process can accurately identify the first mark layer 208 and the second mark layer 212, so as to achieve precise alignment of the first mark layer 208 and the second mark layer 212, thereby further improving the packaging yield.
It should be noted that, since the material containing the metal element has a strong reflectivity, as long as the first mark layer 208 is formed in the groove 202, in the forming process of the first mark layer 208, in order to reduce the consumption of the material for forming the first mark layer 208 and reduce the cost, in this embodiment, the first mark layer 208 is located at the bottom and the sidewall of the groove 202. In other embodiments, the first mark layer may also be filled in the groove.
In this embodiment, the material of the first mark layer 208 includes one or more of TiN, ti, taN, and Ta.
The TiN, ti, taN and Ta materials are all metal element-containing materials, and the metal element-containing materials have strong reflectivity, so that the first mark layer 208 and the second mark layer 212 can be accurately identified, and the alignment accuracy of the first mark layer 208 and the second mark layer 212 is improved.
It should be noted that the thickness of the first mark layer 208 is not too large, nor too small. If the thickness of the first mark layer 208 is too large, a void is easily formed between the first mark layer 208 and the sidewall of the groove 202, thereby affecting the reflectivity of the first mark layer 208, and further preventing the second mark layer 212 from being accurately aligned with the first mark layer 208; if the thickness of the first mark layer 208 is too small, the reflectivity of the first mark layer 208 is easily affected, so that the second mark layer 212 and the first mark layer 208 cannot be precisely aligned. For this reason, in the present embodiment, the thickness of the first mark layer 208 is 50 to 200 angstroms.
In this embodiment, the first marker layer 208 is located at the bottom and the sidewall of the groove 202, and therefore, the thickness of the first marker layer 208 refers to: the dimension of the first mark layer 208 at the bottom of the groove 202 in the depth direction of the groove 202, or the dimension of the first mark layer 208 at the side wall of the groove 202 in the direction perpendicular to the side wall of the groove 202.
In this embodiment, the semiconductor structure further includes: a protective layer 205 disposed in the groove 202 and covering the bottom and the sidewall of the first mark layer 208
In the formation process of the first mark layer 208, the protective layer 205 protects the top of the first mark layer 208, so that the probability of contamination of the first mark layer 208 is reduced, and the metal reflectivity of the first mark layer 208 is improved.
In this embodiment, the material of the protection layer 205 includes SiO 2 SiN and SiON.
The SiO 2 SiN and SiON materials have good insulating properties, which reduces the probability of contamination of the first mark layer 208.
Note that the thickness of the protective layer 205 is not too large or too small. If the thickness of the protection layer 205 is too large, the difficulty of removing the protection layer 205 exposed at two sides of the mark region 200A is increased in the formation process of the first mark layer 208; if the thickness of the protective layer 205 is too small, the protective effect of the protective layer 205 on the first mark layer 208 is reduced, and the probability of contamination of the first mark layer 208 is increased. For this reason, in the present embodiment, the thickness of the protective layer 205 is 50 to 500 angstroms.
The second device wafer 61 is a wafer on which device fabrication is completed, and the second device wafer 61 may be fabricated by using an integrated circuit fabrication technology.
In this embodiment, the second base includes a second substrate 211, devices such as an NMOS device and a PMOS device formed on the second substrate 211 by deposition, etching, and other processes, and structures such as a dielectric layer and a metal interconnection line formed on the devices.
It should be noted that, for convenience of illustration, in this embodiment, only the second substrate 211 is illustrated as the second base, and devices formed on the second substrate 211 are not illustrated.
In this embodiment, the second substrate 211 of the second device wafer 61 is a silicon substrate. In other embodiments, the material of the second substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium, and the second substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the second substrate may be a material suitable for process requirements or easy integration.
In this embodiment, the second substrate has a second front surface (not labeled) and a second back surface (not labeled) opposite to each other. Wherein the second front side refers to: the side of the second base facing away from the second substrate 211; the second back surface means: a bottom surface of the second substrate 211, i.e., a surface of the second substrate 211 exposed.
In this embodiment, a second dielectric layer 210 is formed on top of the second substrate. The second dielectric layer 210 serves as one of bonding layers for bonding the first device wafer 60 and the second device wafer 61, and the second dielectric layer 210 is further used for providing a process base for the second marking layer 212.
The material of the second dielectric layer 210 is a dielectric material, and therefore, the first device wafer 60 and the first device wafer 60 are bonded by fusion bonding (fusion bonding).
In this embodiment, the material of the second dielectric layer 210 includes SiO 2 SiN and SiON.
In this embodiment, the second dielectric layer 210 is located on the second front surface.
In this embodiment, the second mark layer 212 is exposed on a surface of the second dielectric layer 210 opposite to the second substrate, so that the second mark layer 212 can be accurately identified by a processing tool during the bonding process.
The material of the second mark layer 212 is a material containing a metal element, and since the material containing a metal element has a strong reflectivity, in the bonding process of the first device wafer 60 and the second device wafer 61, the second mark layer 212 can be accurately identified by a process machine of the bonding process, so that the first mark layer 208 and the second mark layer 212 are accurately aligned.
Since the first mark layer 208 and the second mark layer 212 both have strong reflectivity, the processing tool can accurately identify the positions of the first mark layer 208 and the second mark layer 212, so that the first mark layer 208 and the second mark layer 212 can be precisely aligned.
In this embodiment, the material of the second marker layer 212 includes one or both of Cu and AL.
It should be noted that, since the second mark layer 212 and the first mark layer 208 can be aligned with each other, the bonding degree of the second dielectric layer 210 and the first dielectric layer 201 is higher, thereby further improving the packaging yield.
Fig. 4 to fig. 11 are schematic structural diagrams corresponding to steps of a method for forming a package structure according to an embodiment of the invention.
Referring to fig. 4, a first device wafer 50 is provided, the first device wafer 50 including a first substrate and a first dielectric layer 101 on the first substrate, the first device wafer 50 including a mark region 100A.
In this embodiment, the packaging method is used to implement wafer level packaging, and the first device wafer 50 is used to bond with a second device wafer in a subsequent process.
The first device wafer 50 is a wafer on which device fabrication is completed, and the first device wafer 50 may be fabricated using integrated circuit fabrication techniques.
In this embodiment, the first base includes a first substrate 100, NMOS devices, PMOS devices, and other devices formed on the first substrate 200 by deposition, etching, and other processes, and structures formed on the devices, such as a dielectric layer and a metal interconnection line.
It should be noted that, for convenience of illustration, in this embodiment, the first base only illustrates the first substrate 100, and devices formed on the first substrate 100 are not shown.
In this embodiment, the first device wafer 50 includes a mark region 100A.
The mark area 100A is an area where the first device wafer 50 and the second device wafer can be self-aligned.
For convenience of illustration, in the present embodiment, a marking region 100A in the first device wafer 50 is taken as an example for description. In other embodiments, the number of marking regions in the first device wafer 50 is not limited to one.
In this embodiment, the first substrate 100 of the first device wafer 50 is a silicon substrate. In other embodiments, the material of the first substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium, and the first substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the first substrate may be a material suitable for process requirements or easy integration.
In this embodiment, the first substrate has a first front surface (not shown) and a first back surface (not shown) opposite to each other. Wherein the first front side refers to: the side of the first base facing away from the first substrate 100; the first back side refers to: the bottom surface of the first substrate 100, i.e., the surface of the first substrate 100 that is exposed.
In this embodiment, a first dielectric layer 101 is formed on the top of the first substrate. The first dielectric layer 101 serves as one of bonding layers for achieving bonding between a first device wafer and a subsequently provided second device wafer, and the first dielectric layer 101 is further used for providing a process basis for subsequently forming a groove in the marking region 100A.
The material of the first dielectric layer 201 is a dielectric material, and therefore, the first device wafer 50 and a subsequently provided second device wafer are bonded by fusion bonding (fusion bonding).
In this embodiment, the material of the first dielectric layer 101 includes SiO 2 SiN and SiON.
In this embodiment, in the first device wafer 50, the first dielectric layer 101 is located on the first back side.
Referring to fig. 5, in the mark region 100A, a groove 102 is formed in the first dielectric layer 101.
The recess 102 provides a spatial location for subsequent formation of the first mark layer.
It should be noted that the depth of the groove 102 is not too large or too small. If the depth of the groove 102 is too large, in the process of forming the groove 102, the related etching process is prone to damage the device at the bottom of the groove 102 and the first substrate 100, so that the performance of the semiconductor structure is affected; if the depth of the groove 102 is too small, the filling effect of the first mark layer in the groove 102 is poor in the subsequent process of forming the first mark layer in the groove, so that the alignment effect between the subsequent first mark layer and the second mark layer is affected. For this purpose, in this embodiment, the depth of the groove 102 is 2000 to 5000 angstroms. For example, the depth of the groove 102 is 2500 angstroms, 3000 angstroms or 4000 angstroms.
In this embodiment, the process of forming the groove 102 in the first dielectric layer 101 includes a dry etching process.
It should be noted that the dry etching process includes an anisotropic dry etching process, and the anisotropic dry etching process has an anisotropic etching characteristic, that is, a longitudinal etching rate is greater than a transverse etching rate, and can ensure the morphology quality of the sidewall of the groove 102 in the process of forming the groove 102 in the first dielectric layer 101.
Referring to fig. 6 to 10, a first mark layer 108 is formed in the recess 102, and a material of the first mark layer 108 is a metal element-containing material.
In this embodiment, after the groove 102 is formed in the first dielectric layer 101, the first mark layer 108 is formed on the bottom and the sidewall of the groove 102, so that the first mark layer 108 is exposed on the surface of the first dielectric layer 110 facing away from the first substrate, so that the first mark layer 108 can be accurately identified by a process tool of a bonding process during the bonding process between the first device wafer 50 and a subsequently provided second device wafer.
Moreover, the material of the first mark layer 108 is a material containing a metal element, and since the material containing the metal element has a relatively strong reflectivity, in the subsequent process of bonding the first device wafer 50 and the second device wafer, a process machine of the bonding process can accurately identify the first mark layer 108 and the second mark layer, so as to achieve precise alignment of the first mark layer 108 and the second mark layer, thereby further improving the packaging yield.
It should be noted that, since the material containing the metal element has a strong reflectivity, the first mark layer 108 only needs to be formed in the groove 102, and in order to reduce the consumption of the material for forming the first mark layer 108 and reduce the cost, in this embodiment, the first mark layer 108 is located at the bottom and the sidewall of the groove 102. In other embodiments, the first mark layer may also be filled in the groove.
In this embodiment, the step of forming the first mark layer 108 on the bottom and the sidewall of the groove 102 includes: forming a first marking material layer 103 on the bottom and sidewalls of the recess 102 and on top of the first dielectric layer 101; the first marking material layer 103 on top of the first dielectric layer 101 is removed, and the first marking material layer 103 on the bottom and sidewalls of the recess 102 remains as the first marking layer 108.
The process of forming the first marker layer 108 on the bottom and sidewalls of the recess 102 includes one or both of a physical vapor deposition process and a chemical vapor deposition process.
As an example, the process of forming the first mark layer 108 on the bottom and the sidewall of the groove 102 is a physical vapor deposition process. The physical vapor deposition process has the advantages of simple operation, low process cost, uniform and compact film formation and strong bonding force with the first dielectric layer 101.
It should be noted that the first marking material layer 103 on top of the first dielectric layer 101 is removed to expose the top of the first dielectric layer 101, so as to provide a process foundation for subsequently implementing the bonding of the first device wafer 50 and the second device wafer.
In this embodiment, the material of the first mark layer 108 includes one or more of TiN, ti, taN, and Ta.
The TiN, ti, taN and Ta materials are all materials containing metal elements, and the materials containing the metal elements have stronger reflectivity, so that the first mark layer 108 and the second mark layer can be identified accurately in the follow-up process, and the alignment precision of the first mark layer 108 and the second mark layer is improved.
Referring to fig. 7, after forming the first marking material 103 and before removing the first marking material layer 103 on top of the first dielectric layer 101, the method further includes: a protective layer 105 is formed in the recess 102, the protective layer 105 covering the bottom and sidewalls of the first marking material layer 103 and also extending to cover the first marking material layer 103 on top of the first dielectric layer 101.
The protective layer 105 protects the top of the first marking material 103, so that the probability of mutual contact between the first marking material 103 and a subsequently formed mask layer is reduced, the probability of contamination of the first marking material 103 is reduced, and the metal reflectivity of the first marking material 103 is improved.
In this embodiment, the process of forming the protection layer 105 in the groove 102 includes a chemical vapor deposition process.
The chemical vapor deposition process has the characteristics of simple operation, high process efficiency, good coverage and the like, so that the protective layer 105 can cover the bottom and the side wall of the first marking material layer 103.
In this embodiment, the material of the protection layer 105 includes SiO 2 SiN and SiON.
The SiO 2 SiN and SiON materials have good insulating properties, which reduces the probability of contamination of the first mark layer 208.
The thickness of the protective layer 105 is not necessarily too large, nor too small. If the thickness of the protection layer 105 is too large, the difficulty of removing the protection layer 105 exposed at both sides of the mark region 100A is increased in the formation process of the first mark layer 108; if the thickness of the protective layer 105 is too small, the protective effect of the protective layer 105 on the first mark layer 108 is reduced, and the probability of contamination of the first mark layer 108 is increased. For this reason, in the present embodiment, the thickness of the protective layer 105 is 50 to 500 angstroms.
In this embodiment, the step of removing the first marking material layer 103 on top of the first dielectric layer 101 includes: as shown in fig. 8, a mask layer 106 is formed over the first marking material layer 103 in the groove 102, wherein the mask layer 106 also extends to cover the top of the portion of the first marking material layer 103 outside the groove 102; as shown in fig. 9, performing a patterning process by using the mask layer 106 as a mask, and removing the first marking material layer 103 exposed by the mask layer 106; removing the mask layer 106 after removing the first marking material layer 103 exposed by the mask layer 106; as shown in fig. 10, after removing the mask layer 106, the remaining first marking material layer 103 on the top of the first dielectric layer 101 is planarized by using the top of the first dielectric layer 101 as a stop position.
In this embodiment, the material of the mask layer 106 includes an organic material. Specifically, the material of the mask layer 106 includes a bottom anti-reflective coating (BARC) material.
In this embodiment, in the step of forming the mask layer 106, the mask layer 106 is formed on the protection layer 105.
In order to avoid the mask layer 106 from contacting the first marking material layer 103 and reduce the probability of the mask layer 106 contaminating the first marking material layer 103, the mask layer 106 is formed on the protection layer 105.
In this embodiment, in the process of performing the patterning process by using the mask layer 106 as a mask, the protection layer 105 exposed by the mask layer 106 is also removed.
In the same step, the protective layer 105 and the first marking material layer 103 exposed by the mask layer 106 are removed, so that the process steps can be reduced, and the process cost can be reduced.
In this embodiment, in the step of performing the patterning process by using the mask layer 106 as a mask, the patterning process includes a wet etching process.
The wet etching process has an isotropic characteristic, and can reduce damage to the first dielectric layer 101 while removing the protective layer 105 and the first marker material layer 103 exposed by the mask layer 106, so that the first dielectric layer 101 is retained.
In this embodiment, during the planarization of the remaining first marking material layer 103 on the top of the first dielectric layer 101, the planarization of the remaining protection layer 105 on the top of the first dielectric layer 101 is performed, and the remaining protection layer 105 in the groove 102 is remained.
In this embodiment, the process of planarizing the remaining first marking material layer 103 on top of the first dielectric layer 101 includes a chemical mechanical polishing process.
Referring to fig. 11, a second device wafer 51 is provided, where the second device wafer 51 includes a second substrate and a second dielectric layer 110 located on the second substrate, a second mark layer 112 is formed in a surface of the second dielectric layer 110 facing away from the second substrate, and a material of the second mark layer 112 is a material containing a metal element.
The second device wafer 51 is a wafer on which device fabrication is completed, and the second device wafer 51 may be fabricated by using an integrated circuit fabrication technology.
In this embodiment, the second base includes a second substrate 111, devices such as an NMOS device and a PMOS device formed on the second substrate 111 by deposition, etching, and other processes, and structures such as a dielectric layer and a metal interconnection line formed on the devices.
It should be noted that, for convenience of illustration, in this embodiment, only the second substrate 111 is illustrated as the second base, and devices formed on the second substrate 111 are not illustrated.
In this embodiment, the second substrate 111 of the second device wafer 51 is a silicon substrate. In other embodiments, the material of the second substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium, and the second substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the second substrate may be a material suitable for process requirements or easy integration.
In this embodiment, the second substrate has a second front surface (not labeled) and a second back surface (not labeled) opposite to each other. Wherein the second front side refers to: the side of the second base facing away from the second substrate 111; the second back surface means: the bottom surface of the second substrate 111, i.e., the exposed surface of the second substrate 111.
In this embodiment, a second dielectric layer 110 is formed on top of the second substrate. The second dielectric layer 110 serves as one of bonding layers for bonding the first device wafer 50 and the second device wafer 51, and the second dielectric layer 110 is further used for providing a process base for forming the second mark layer 112.
The material of the second dielectric layer 110 is a dielectric material, and therefore, the first device wafer 50 and the first device wafer 51 are bonded by fusion bonding (fusion bonding).
In this embodiment, the material of the second dielectric layer 110 includes SiO 2 SiN and SiON.
In this embodiment, the second dielectric layer 110 is located on the second front surface.
In this embodiment, the second mark layer 112 is exposed on a surface of the second dielectric layer 110 opposite to the second substrate, so that the second mark layer 112 can be accurately identified by a processing tool during the bonding process.
In this embodiment, the material of the second marker layer 112 includes one or both of Cu and AL.
Specifically, the material of the second mark layer 112 is a material containing a metal element, and since the material containing a metal element has a relatively strong reflectivity, a process tool of a bonding process can accurately identify the second mark layer 112 in a bonding process performed on the first device wafer 50 and the second device wafer 51, so as to achieve precise alignment of the first mark layer 108 and the second mark layer 112.
With continued reference to fig. 11, the second dielectric layer 110 is disposed opposite to the first dielectric layer 101, and the second mark layer 112 and the first mark layer 108 are aligned with each other, and the bonding of the second dielectric layer 110 and the first dielectric layer 101 is achieved through a bonding process.
Since the first mark layer 108 and the second mark layer 112 both have strong reflectivity, the processing tool can accurately identify the positions of the first mark layer 108 and the second mark layer 112, so that the first mark layer 108 and the second mark layer 112 can be precisely aligned.
It should be noted that, because the second mark layer 112 and the first mark layer 108 can be aligned with each other, the bonding degree between the second dielectric layer 110 and the first dielectric layer 101 is higher, thereby further improving the packaging yield.
In this embodiment, the second dielectric layer 110 and the first dielectric layer 101 are both made of dielectric materials, and therefore, the bonding between the second dielectric layer 110 and the first dielectric layer 101 is achieved by using a fusion bonding method.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected by one skilled in the art without departing from the spirit and scope of the invention, as defined in the appended claims.

Claims (24)

1. A package structure, comprising:
a first device wafer comprising a first substrate and a first dielectric layer on the first substrate, the first device wafer comprising a marker region;
the groove is positioned in the mark area and in the surface of the first dielectric layer, which faces away from the first substrate;
the first marking layer is positioned in the groove, and the material of the first marking layer is a material containing metal elements;
and the second device wafer is bonded with the first device wafer and comprises a second substrate and a second dielectric layer positioned on the second substrate, wherein a second marking layer is formed in the surface, facing away from the second substrate, of the second dielectric layer, the second marking layer is made of a material containing a metal element, the second dielectric layer and the first dielectric layer are oppositely arranged and bonded, and the second marking layer and the first marking layer are aligned with each other.
2. The package structure of claim 1, wherein in the first device wafer, the first substrate has opposing first front and back sides, the first dielectric layer being on the first back side.
3. The packaging method of claim 1, wherein in the second device wafer, the second substrate has a second front side and a second back side opposite, the second dielectric layer being on the second front side.
4. The package structure of claim 1, wherein the first mark layer is located at the bottom and the sidewall of the groove, or wherein the first mark layer is filled in the groove.
5. The package structure of claim 1, wherein the first label layer is located at a bottom and sidewalls of the recess;
the semiconductor structure further includes: and the protective layer is positioned in the groove and covers the bottom and the side wall of the first marking layer.
6. The package structure of claim 1, wherein the depth of the recess is 2000 to 5000 angstroms.
7. The package structure of claim 1, wherein a material of the first marker layer comprises one or more of TiN, ti, taN, and Ta.
8. The encapsulation structure of claim 1 or 2, wherein the first marker layer has a thickness of 50 to 200 angstroms.
9. The package structure of claim 5, wherein the protective layer has a thickness of 50 to 500 angstroms.
10. The package structure of claim 5, wherein the guaranteeThe material of the protective layer comprises SiO 2 SiN and SiON.
11. The package structure of claim 1, wherein the material of the second indicia layer comprises one or both of Cu and Al.
12. A method of packaging, comprising:
providing a first device wafer, wherein the first device wafer comprises a first substrate and a first dielectric layer positioned on the first substrate, and the first device wafer comprises a marking area;
forming a groove in the first dielectric layer in the mark region;
forming a first marking layer in the groove, wherein the material of the first marking layer is a material containing a metal element;
providing a second device wafer, wherein the second device wafer comprises a second substrate and a second dielectric layer located on the second substrate, a second marking layer is formed in the surface, facing away from the second substrate, of the second dielectric layer, and the material of the second marking layer is a material containing a metal element;
and arranging the second dielectric layer opposite to the first dielectric layer, aligning the second mark layer and the first mark layer with each other, and bonding the second dielectric layer and the first dielectric layer through a bonding process.
13. The method of packaging of claim 12, wherein in the step of providing the first device wafer, the first substrate has opposing first front and back surfaces, and the first dielectric layer is on the first back surface.
14. The method of packaging of claim 12, wherein in the step of providing the second device wafer, the second substrate has a second front surface and a second back surface opposite to the second front surface, and the second dielectric layer is on the second front surface.
15. The method of claim 12, wherein in the step of forming the first mark layer in the groove, the first mark layer is located at a bottom and a sidewall of the groove, or the first mark layer is filled in the groove.
16. The packaging method according to claim 12, wherein in the step of forming a first mark layer in the groove, the first mark layer is located at a bottom and a sidewall of the groove;
the step of forming a first mark layer on the bottom and sidewalls of the groove includes: forming a first marking material layer on the bottom and the side wall of the groove and the top of the first dielectric layer; and removing the first marking material layer positioned on the top of the first dielectric layer, and reserving the first marking material layer positioned at the bottom and the side wall of the groove as the first marking layer.
17. The packaging method of claim 16, wherein removing the first marking material layer on top of the first dielectric layer comprises: forming a mask layer above the first marking material layer in the groove, wherein the mask layer also extends to cover the partial top of the first marking material layer outside the groove;
carrying out graphical processing by taking the mask layer as a mask, and removing the first marking material layer exposed by the mask layer;
after the first marking material layer exposed by the mask layer is removed, the top of the first dielectric layer is used as a stop position, and the rest first marking material layer positioned on the top of the first dielectric layer is subjected to planarization treatment;
and removing the mask layer after the planarization treatment.
18. The method of packaging of claim 17, wherein after forming the first marking material layer and before removing the first marking material layer on top of the first dielectric layer, further comprising: forming a protective layer in the groove, wherein the protective layer covers the bottom and the side wall of the first marking material layer and also extends to cover the first marking material layer positioned on the top of the first dielectric layer;
in the step of forming the mask layer, the mask layer is formed on the protective layer;
in the process of carrying out patterning treatment by taking the mask layer as a mask, removing the protective layer exposed by the mask layer;
and in the process of carrying out planarization treatment on the rest of the first marking material layer positioned on the top of the first dielectric layer, carrying out planarization treatment on the rest of the protective layer positioned on the top of the first dielectric layer, and reserving the rest of the protective layer positioned in the groove.
19. The packaging method according to claim 12, wherein the process of forming the first mark layer on the bottom and the sidewall of the groove comprises one or both of a physical vapor deposition process and a chemical vapor deposition process.
20. The wafer level packaging method of claim 12, wherein the material of the first marker layer comprises one or more of TiN, ti, taN, and Ta.
21. The packaging method of claim 18, wherein the process of forming a protective layer in the recess comprises a chemical vapor deposition process.
22. The packaging method of claim 12, wherein the material of the second indicia layer comprises one or both of Cu and Al.
23. The packaging method of claim 18, wherein the material of the protective layer comprises SiO 2 SiN and SiON.
24. The packaging method according to claim 17, wherein in the step of performing the patterning process using the mask layer as a mask, the patterning process includes a wet etching process.
CN202110802874.9A 2021-07-15 2021-07-15 Packaging method and packaging structure Pending CN115621135A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116682724A (en) * 2023-06-08 2023-09-01 荣芯半导体(淮安)有限公司 Semiconductor structure, forming method and related device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116682724A (en) * 2023-06-08 2023-09-01 荣芯半导体(淮安)有限公司 Semiconductor structure, forming method and related device
CN116682724B (en) * 2023-06-08 2024-04-26 荣芯半导体(淮安)有限公司 Semiconductor structure, forming method and related device

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