TWI795800B - 半導體裝置及其形成方法 - Google Patents
半導體裝置及其形成方法 Download PDFInfo
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- TWI795800B TWI795800B TW110120865A TW110120865A TWI795800B TW I795800 B TWI795800 B TW I795800B TW 110120865 A TW110120865 A TW 110120865A TW 110120865 A TW110120865 A TW 110120865A TW I795800 B TWI795800 B TW I795800B
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- 238000000034 method Methods 0.000 title claims abstract description 122
- 239000004065 semiconductor Substances 0.000 title claims description 35
- 230000004888 barrier function Effects 0.000 claims abstract description 214
- 239000000463 material Substances 0.000 claims abstract description 139
- 238000005530 etching Methods 0.000 claims abstract description 33
- 239000004020 conductor Substances 0.000 claims abstract description 29
- 229910052723 transition metal Inorganic materials 0.000 claims abstract description 14
- 150000003624 transition metals Chemical class 0.000 claims abstract description 14
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims description 98
- 239000002184 metal Substances 0.000 claims description 98
- 230000008569 process Effects 0.000 claims description 95
- 238000000151 deposition Methods 0.000 claims description 69
- 238000000231 atomic layer deposition Methods 0.000 claims description 46
- 239000002243 precursor Substances 0.000 claims description 39
- 239000007789 gas Substances 0.000 claims description 32
- QRUDEWIWKLJBPS-UHFFFAOYSA-N benzotriazole Chemical compound C1=CC=C2N[N][N]C2=C1 QRUDEWIWKLJBPS-UHFFFAOYSA-N 0.000 claims description 18
- 239000012964 benzotriazole Substances 0.000 claims description 18
- 239000002019 doping agent Substances 0.000 claims description 14
- 238000011049 filling Methods 0.000 claims description 13
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 12
- 238000009832 plasma treatment Methods 0.000 claims description 12
- 150000004767 nitrides Chemical class 0.000 claims description 9
- 238000005229 chemical vapour deposition Methods 0.000 claims description 8
- 229910052707 ruthenium Inorganic materials 0.000 claims description 8
- 230000008021 deposition Effects 0.000 claims description 7
- 229910052757 nitrogen Inorganic materials 0.000 claims description 7
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 5
- 239000001257 hydrogen Substances 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims description 2
- 238000000926 separation method Methods 0.000 claims description 2
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims 1
- 239000010410 layer Substances 0.000 description 358
- 239000000758 substrate Substances 0.000 description 18
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 14
- 230000015572 biosynthetic process Effects 0.000 description 13
- 239000000126 substance Substances 0.000 description 13
- 238000000137 annealing Methods 0.000 description 12
- 238000009792 diffusion process Methods 0.000 description 11
- 239000000203 mixture Substances 0.000 description 10
- 238000010926 purge Methods 0.000 description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 9
- 229910052802 copper Inorganic materials 0.000 description 9
- 239000010949 copper Substances 0.000 description 9
- JWBQJUFCNOLNNC-UHFFFAOYSA-N dec-5-yne Chemical compound CCCCC#CCCCC JWBQJUFCNOLNNC-UHFFFAOYSA-N 0.000 description 9
- 238000005137 deposition process Methods 0.000 description 9
- 150000002739 metals Chemical class 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 229910021529 ammonia Inorganic materials 0.000 description 7
- QMMFVYPAHWMCMS-UHFFFAOYSA-N Dimethyl sulfide Chemical compound CSC QMMFVYPAHWMCMS-UHFFFAOYSA-N 0.000 description 6
- LYCAIKOWRPUZTN-UHFFFAOYSA-N Ethylene glycol Chemical compound OCCO LYCAIKOWRPUZTN-UHFFFAOYSA-N 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 6
- 241001342895 Chorus Species 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- HAORKNGNJCEJBX-UHFFFAOYSA-N cyprodinil Chemical compound N=1C(C)=CC(C2CC2)=NC=1NC1=CC=CC=C1 HAORKNGNJCEJBX-UHFFFAOYSA-N 0.000 description 5
- 239000005360 phosphosilicate glass Substances 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 235000012431 wafers Nutrition 0.000 description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 4
- -1 PSG) Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 229910052799 carbon Inorganic materials 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 238000001179 sorption measurement Methods 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 150000001412 amines Chemical class 0.000 description 3
- 239000012159 carrier gas Substances 0.000 description 3
- 230000002209 hydrophobic effect Effects 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 229910052715 tantalum Inorganic materials 0.000 description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 3
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 2
- 229910019142 PO4 Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 239000005388 borosilicate glass Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 2
- RWRIWBAIICGTTQ-UHFFFAOYSA-N difluoromethane Chemical compound FCF RWRIWBAIICGTTQ-UHFFFAOYSA-N 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 125000001997 phenyl group Chemical group [H]C1=C([H])C([H])=C(*)C([H])=C1[H] 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-K phosphate Chemical compound [O-]P([O-])([O-])=O NBIIXXVUZAFLBC-UHFFFAOYSA-K 0.000 description 2
- 239000010452 phosphate Substances 0.000 description 2
- 239000003361 porogen Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 150000003573 thiols Chemical class 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- QDXQAOGNBCOEQX-UHFFFAOYSA-N 1-methylcyclohexa-1,4-diene Chemical compound CC1=CCC=CC1 QDXQAOGNBCOEQX-UHFFFAOYSA-N 0.000 description 1
- VRGHAGPVLMIIEL-UHFFFAOYSA-N 1H-indol-2-amine 3-(1,2,4-triazol-3-ylidene)-1,2,4-triazole Chemical compound N1=NC=NC1=C1N=NC=N1.C1=CC=C2NC(N)=CC2=C1 VRGHAGPVLMIIEL-UHFFFAOYSA-N 0.000 description 1
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- 229910052582 BN Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- ATNSDOISPHKKST-UHFFFAOYSA-N C(=O)=CC(C)(C)C#C.[Co] Chemical group C(=O)=CC(C)(C)C#C.[Co] ATNSDOISPHKKST-UHFFFAOYSA-N 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 238000005411 Van der Waals force Methods 0.000 description 1
- PRPAGESBURMWTI-UHFFFAOYSA-N [C].[F] Chemical compound [C].[F] PRPAGESBURMWTI-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 150000001336 alkenes Chemical class 0.000 description 1
- 150000001345 alkine derivatives Chemical class 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000013522 chelant Substances 0.000 description 1
- 230000009920 chelation Effects 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- VSLPMIMVDUOYFW-UHFFFAOYSA-N dimethylazanide;tantalum(5+) Chemical compound [Ta+5].C[N-]C.C[N-]C.C[N-]C.C[N-]C.C[N-]C VSLPMIMVDUOYFW-UHFFFAOYSA-N 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000009969 flowable effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052748 manganese Inorganic materials 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 125000004433 nitrogen atom Chemical group N* 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000002791 soaking Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000004094 surface-active agent Substances 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
- 230000036962 time dependent Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02458—Nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
- H01L21/28562—Selective deposition
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/7681—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving one or more buried masks
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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Abstract
本文描述了一種方法,包括於導電部件上方形成絕緣層;蝕刻絕緣層以露出導電部件的第一表面;用犧牲材料覆蓋導電部件的第一表面,其中絕緣層的側壁沒有犧牲材料;用阻障材料覆蓋絕緣層的側壁,其中導電部件的第一表面沒有阻障材料,其中阻障材料包含摻雜過渡金屬的氮化鉭(tantalum nitride, TaN);移除犧牲材料;及用導電材料覆蓋阻障材料及導電部件的第一表面。
Description
本發明實施例是關於一種半導體裝置及其形成方法,特別是關於一種具有擴散阻障層的半導體裝置及其形成方法。
整合電路包括內連線結構,其包括金屬線及導孔以作為三維佈線結構。內連線結構的功能是將密集封裝的裝置適當地連接在一起。
於內連線結構中形成金屬線及導孔。通常藉由鑲嵌製程來形成金屬線及導孔,在上述鑲嵌製程中溝槽及導孔開口形成於介電層中。然後沉積阻障層,隨後用銅填充溝槽及導孔開口。在化學機械拋光(Chemical Mechanical Polish, CMP)製程後,金屬線的頂表面被平坦化,留下金屬線及導孔。
本發明實施例提供一種半導體裝置的形成方法,包括:形成導電部件於第一介電層中;形成第二介電層於導電部件上方;蝕刻開口穿過第二介電層,蝕刻露出導電部件的表面;沉積犧牲層於開口中,其中犧牲層選擇性地形成在導電部件的露出表面上,多於形成在第二介電層的表面上;沉積阻障層於開口中,其中選擇性地形成阻障層於犧牲層上方之第二介電層的表面上,其中沉積阻障層的步驟包括:由一個或多個第一前驅物沉積導電阻障材料;及在沉積導電阻障材料之後,由一個或多個第二前驅物沉積摻雜金屬;移除犧牲層;及沉積導電材料,以填充開口,導電材料接觸導電部件。
本發明實施例提供一種半導體裝置的形成方法,包括:形成絕緣層於導電部件上方;蝕刻絕緣層,以露出導電部件的第一表面;用犧牲材料覆蓋導電部件的第一表面,其中絕緣層的側壁沒有犧牲材料;用阻障材料覆蓋絕緣層的側壁,其中導電部件的第一表面沒有阻障材料,其中阻障材料包括摻雜過渡金屬的氮化鉭(tantalum nitride, TaN);移除犧牲材料;及用導電材料覆蓋阻障材料及導電部件的第一表面。
本發明實施例提供一種半導體裝置,包括:第一導電部件,位於第一介電層中;蝕刻停止層,位於第一導電部件上方;第二介電層,位於蝕刻停止層上方;及第二導電部件,延伸穿過第二介電層及蝕刻停止層,以實體接觸第一導電部件,其中第二導電部件包括:阻障層,連續延伸於第二介電層的側壁上及蝕刻停止層的側壁上,其中阻障層包括一層過渡金屬,位於金屬氮化物的第一層及該金屬氮化物的第二層之間;及導電填充材料,位於阻障層上方,其中導電填充材料延伸於阻障層及第一導電部件之間。
以下揭露提供了許多的實施例或範例,用於實施所提供的標的物之不同元件。各元件和其配置的具體範例描述如下,以簡化本發明實施例之說明。當然,這些僅僅是範例,並非用以限定本發明實施例。舉例而言,敘述中若提及第一元件形成在第二元件之上,可能包含第一和第二元件直接接觸的實施例,也可能包含額外的元件形成在第一和第二元件之間,使得它們不直接接觸的實施例。此外,本發明實施例可能在各種範例中重複參考數值以及∕或字母。如此重複是為了簡明和清楚之目的,而非用以表示所討論的不同實施例及∕或配置之間的關係。
再者,其中可能用到與空間相對用詞,例如「在……之下」、「下方」、「較低的」、「上方」、「較高的」等類似用詞,是為了便於描述圖式中一個(些)部件或特徵與另一個(些)部件或特徵之間的關係。空間相對用詞用以包括使用中或操作中的裝置之不同方位,以及圖式中所描述的方位。當裝置被轉向不同方位時(旋轉90度或其他方位),其中所使用的空間相對形容詞也將依轉向後的方位來解釋。
根據各種實施例,提供了一種選擇性地形成用於導電部件的阻障層的方法。根據一些實施例,繪示出形成導電部件的中間階段。討論了一些實施例的一些變型。貫穿各種視圖及說明性實施例,相似的參考數值用於指示相似的元件。根據本揭露的一些實施例,導電部件的形成包括於開口中的導電區上方選擇性地形成阻障層,用金屬材料填充開口,並且進行平坦化。導電阻障層的選擇性形成是藉由在下方金屬部件上形成犧牲層來實現的。犧牲層阻抗(resist)阻障層材料的黏著,使得阻障層選擇性地生長在導孔開口的側壁上,而幾乎沒有或沒有阻障層形成在犧牲層上。將阻障層形成為具有摻質金屬,其中將摻質金屬摻入阻障層中(例如,作為摻質或作為阻障層的子層),以增加阻障層的密度。在形成阻障層之後,進行處理以移除犧牲層。然後,用金屬材料填充剩餘的開口,上述金屬材料例如銅,上述金屬材料形成於金屬部件上。
第1圖係根據本揭露的一些實施例,繪示出封裝元件100的剖面圖。封裝元件100可為包括例如電晶體及/或二極管的主動裝置的裝置晶圓(例如邏輯裝置晶圓),並且可包括例如電容器、電感器、電阻器等的被動裝置。根據本揭露的替代實施例,封裝元件100為中介(interposer)晶圓,其可包括或可不包括主動裝置及/或被動裝置。根據本揭露的另一替代實施例,封裝元件100為封裝基板條(strip),其可包括其中具有芯(core)的封裝基板或無芯的封裝基板。在隨後的討論中,將裝置晶圓用作封裝元件100的示例。本揭露內容的教示也可應用於中介晶圓、封裝基板、封裝等。
根據本揭露的一些實施例,封裝元件100包括半導體基板20及形成於半導體基板20之頂表面上的部件。半導體基板20可包括晶體矽、晶體鍺、矽鍺、 III-V族化合物半導體,例如GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP等、或其組合。在一些實施例中,半導體基板20也可為塊體矽基板或絕緣體上覆矽(Silicon-On-Insulator, SOI)基板。可於半導體基板20中形成淺溝槽隔離(Shallow Trench Isolation, STI)區(未繪示),以隔離半導體基板20中的主動區。儘管未繪示,但是可形成延伸進半導體基板20中的導通孔(through-via),以電性連接位於封裝元件100兩側上的部件。
根據本揭露的一些實施例,封裝元件100用於形成裝置晶粒。在這些實施例中,整合電路裝置22形成於半導體基板20的頂表面上。例示性整合電路裝置22包括互補式金屬氧化物半導體(Complementary Metal-Oxide Semiconductor, CMOS)電晶體、電阻器、電容器、二極管等。這裡並未繪示出整合電路裝置22的細節。根據替代實施例,封裝元件100用於形成中介物(interposers)。根據這些實施例,基板20也可例如為介電基板。
第1圖進一步繪示出介電層24。介電層24可例如為層間介電質(Inter-Layer Dielectric, ILD)或金屬間介電質(Inter-Metal Dielectric, IMD)。根據本揭露的一些實施例,介電層24為ILD,接觸插塞形成於其中。相應的介電層24可由例如下列材料所形成:磷矽酸鹽玻璃(Phospho Silicate Glass, PSG)、硼矽酸鹽玻璃(Boro Silicate Glass, BSG)、硼摻雜磷矽酸鹽玻璃(Boron-Doped Phospho Silicate Glass, BPSG)、氟摻雜矽酸鹽玻璃(Fluorine-Doped Silicate Glass, FSG)、(使用四乙氧基矽烷(Tetra Ethyl Ortho Silicate, TEOS)形成的)氧化矽層等或其組合。可使用下列製程來形成介電層24:旋轉塗佈、原子層沉積(Atomic Layer deposition, ALD)、流動式化學氣相沉積(Flowable Chemical Vapor Deposition, FCVD)、化學氣相沉積(Chemical Vapor Deposition, CVD)、電漿增強化學氣相沉積(Plasma-Enhanced Chemical Vapor Deposition, PECVD)、低壓化學氣相。沉積(Low-Pressure Chemical Vapor Deposition, LPCVD)等。
根據本揭露的一些實施例,介電層24為IMD,金屬線及/或導孔形成於其中。相應的介電層24可由下列材料所形成:含碳的低k介電材料、氫矽氧烷(Hydrogen SilsesQuioxane, HSQ)、甲基矽氧烷(MethylSilsesQuioxane, MSQ)、另一種低k介電材料等、或其組合。根據本揭露的一些實施例,介電層24的形成包括沉積含成孔劑(porogen-containing)的介電材料,然後進行固化(curing)製程以驅除(drive out)成孔劑,以形成多孔的介電層24。
繼續參照第1圖,於介電層24中形成導電部件30。導電部件30可為金屬線、導電導孔、接觸插塞等。根據一些實施例,導電部件30包括擴散阻障層26及位於擴散阻障層26上方的導電填充材料28。擴散阻障層26可由例如下列材料所形成:鈦、氮化鈦、鉭、氮化鉭等、或其組合。導電填充材料28可由下列材料所形成:銅、銅合金、鋁、另一種金屬、或金屬合金等、或其組合。擴散阻障層26具有防止導電填充材料28之導電材料(例如,銅)擴散進介電層24中的功能。根據本揭露的一些實施例,導電部件30的形成也可採用隨後討論的技術,從而不形成擴散阻障層26的底部。
同樣如第1圖所示,係根據一些實施例,於介電層24及導電部件30上方形成蝕刻停止層32。蝕刻停止層32是由介電材料所形成,上述介電材料可包括例如下列一種或多種材料:氧化鋁、氮化鋁、氧化矽、氮化矽、碳化矽、氮氧化矽、碳氮化矽、氮碳氧化矽等、或其組合。在一些情況下,使用包含金屬(例如,氮化鋁、氧化鋁等)的蝕刻停止層32可與隨後形成的犧牲層48 (參照第5圖)形成鍵結,因此用於蝕刻停止層之含金屬材料的使用可改善犧牲層48的阻擋能力。蝕刻停止層32可由相對於上方之介電層34具有高蝕刻選擇性的材料所形成,從而介電層34的蝕刻可停止於蝕刻停止層32上。在一些實施例中,蝕刻停止層32可具有介於約1nm至約10nm之間的厚度T0。
繼續參照第1圖,於蝕刻停止層32上方形成介電層34。在一些實施例中,介電層34為IMD或ILD。介電層34可包括例如下列介電材料:氧化物、氮化物、含碳介電材料等、或其組合。舉例而言,介電層34可由下列材料所形成:PSG、BSG、BPSG、FSG、TEOS氧化物、HSQ、MSQ等、或其組合。在一些實施例中,介電層34為具有介電常數值(dielectric constant value, k)小於約3.5或小於約3.0的低k介電層。
第2圖至第6B圖以及第8圖至第10圖係根據一些實施例,繪示出用於形成金屬線60及導孔58(參照第10圖)的製程。應理解的是,這些附圖中所示的示例描述了雙鑲嵌製程,但是在其他實施例中也可考慮形成金屬線、導孔、接觸插塞等的單鑲嵌製程。
第2圖及第3圖係根據一些實施例,於介電層34中形成導孔開口42及溝槽44。可使用例如光學微影及蝕刻技術來形成導孔開口42及溝槽44。如第2圖所示,在形成導孔開口42及溝槽44之製程的示例中,首先於介電層34上方形成金屬硬遮罩37,然後將金屬硬遮罩37圖案化以形成開口38。金屬硬遮罩37可由例如下列材料所形成:氮化鈦、氮化硼、另一種金屬氧化物、或金屬氮化物等、或其組合。金屬硬遮罩37中的開口38定義了溝槽的圖案(例如,第3圖中所示的溝槽44),隨後填充溝槽以形成金屬線(例如,第10圖中所示的金屬線60)。
在形成開口38之後,於介電層34上方及金屬硬遮罩37上方形成光阻40。光阻40可為單層光阻結構或多層光阻結構(例如,三層光阻結構)。可使用合適的技術來實現將光阻40圖案化以露出介電層34。如第2圖所示,接著蝕刻露出的介電層34,以形成至少部分地延伸進介電層34中的開口42。可使用濕式蝕刻製程及/或乾式蝕刻製程(例如,電漿蝕刻製程)來進行介電層34的蝕刻。舉例而言,可使用包含氟及碳的處理氣體來進行介電層34的蝕刻,其中氟用於蝕刻,而碳具有保護所得之開口的側壁的作用。藉由合適的的氟及碳的比例,可形成具有所需之輪廓的開口42。舉例而言,用於蝕刻的處理氣體可包括一種或多種例如下列含氟及碳的氣體:C4
F8
、CH2
F2
、CF4
等,並且可包括一種或多種載體氣體,例如Ar、N2
等。在蝕刻製程的示例中,C4
F8
的流速在約0sccm至約50sccm之間的範圍內,CF4
的流速在約0sccm至約300sccm之間的範圍內(與至少一個C4
F8
具有非零的流速),並且N2
的流速在約0sccm至約200sccm之間的範圍內。作為額外的示例,用於蝕刻的處理氣體可包括CH2
F2
及例如N2
的載體氣體。CH2
F2
的流速可在約10sccm至約200sccm之間的範圍內,並且N2
的流速可在約50sccm至約100sccm之間的範圍內。在蝕刻製程期間,可將封裝元件100保持在約30℃至約60℃之間的範圍內的溫度。在蝕刻製程中,可由蝕刻氣體產生電漿。用於蝕刻之電源的射頻(Radio Frequency, RF)功率可低於約700瓦特,且處理氣體的壓力在約15mTorr至約30mTorr之間的範圍內。這些為示例,且其他蝕刻製程或蝕刻參數為可能的。在一些實施例中,介電層34的蝕刻可進行一段時間,以使得開口42如第2圖所示延伸至介電層34的頂表面及底表面之間的中間層級。時間長度可為預定的。
參見第3圖,然後移除光阻40,接著使用金屬硬遮罩37作為蝕刻遮罩進一步蝕刻介電層34。用於蝕刻介電層34的蝕刻製程可例如為非等向性蝕刻製程。蝕刻製程將開口42延伸進介電層34中,直到開口42露出蝕刻停止層32為止。如第3圖所示,蝕刻製程將開口42延伸,並且也形成了部分地延伸進介電層34中的溝槽44。對於蝕刻製程之後所得的結構而言,最終的開口42被稱作導孔開口42,位於溝槽44的下方並且與溝槽44相連(contiguous with)。隨後填充導孔開口42,以形成導孔(例如,第10圖所示的導孔58)。
根據替代實施例,導孔開口42及溝槽44是在分開的光學微影製程中所形成的。舉例而言,在第一光學微影製程中,可形成延伸穿過介電層34至蝕刻停止層32的導孔開口42。在第二光學微影製程中,可形成溝槽44。根據各種實施例,導孔開口42與溝槽44形成的前後順序可互換。
然後,參照第4圖,進行蝕刻製程以蝕刻穿過蝕刻停止層32並露出導電填充材料28。在一些情況下,當蝕刻停止層32的蝕刻包括濕式蝕刻製程時,蝕刻製程也可稱作濕清潔製程。根據本揭露的一些實施例,蝕刻製程使用包括例如下列料料的溶液:乙二醇、二甲基硫、胺、H2
O2
等、或其組合。舉例而言,可將乙二醇作為表面活性劑使用,可將二甲基硫作為溶劑使用,可將胺用於移除封裝元件100表面上不需之有機殘留物,及/或可將H2
O2
與胺的組合用於將蝕刻停止層32蝕刻。
參見第5圖,係根據一些實施例,接著於導電填充材料28的露出表面上形成犧牲層48。可形成犧牲層48以阻擋、防止、或以其他方式抑制於導電填充材料28上之阻障層50的後續形成(參照第6A圖、第6B圖)。藉由阻止於導電填充材料28上方形成阻障層50,可減小導電填充材料28與隨後沉積之導電材料56之間的界面的電阻。在一些實施例中,犧牲層48可延伸於整個導孔開口42以完全覆蓋導電填充材料28的露出表面。在一些實施例中,將犧牲層48形成為具有介於約0.5nm至約5nm之間的厚度T1,例如介於約1nm至約2nm之間。犧牲層48的厚度T1可大於、約等於、或小於蝕刻停止層32的厚度T0。如第5圖所示,犧牲層48以這種方式可形成於導孔開口42內之蝕刻停止層32的側壁表面上。
根據一些實施例,犧牲層48包括黏著或鍵結至導電填充材料28並且並未黏著或鍵結至介電層34的材料。舉例而言,材料可與導電填充材料28中的金屬(例如,銅或鋁)形成螯合鍵(chelation bonds),但是並未與介電層34形成鍵結。在一些情況下,犧牲層48可與包含金屬(例如,鋁)的蝕刻停止層32形成螯合鍵。因此,由於犧牲層48可與導電填充材料28及含金屬的蝕刻停止層32兩者形成鍵結,所以含金屬的蝕刻停止層32的使用可允許犧牲層48更完整覆蓋導電填充材料28。舉例而言,位於含金屬蝕刻停止層32處之犧牲層48的厚度可大於位於不含金屬之蝕刻停止層32(例如,由碳氧化矽等形成的蝕刻停止層32)處之犧牲層48的厚度。以這種方式,隨後形成的阻障層50可形成於介電層34上(參照第6A圖、第6B圖),但是可被防止形成於導電填充材料28上。此外,犧牲層48可為不太可能或不能與隨後形成之阻障層50黏著或鍵結的材料。舉例而言,材料的化學結構可為疏水的及/或包括非極性基團,其不可能或不能與阻障層50的前驅物鍵結,或者材料的化學結構由於立障(steric hindrance)而可抑制阻障層50之前驅物的吸附。可選擇犧牲層48的材料,使得隨後形成之阻障層50的前驅物在位於犧牲層48上方的介電層34上具有高的吸附選擇性。舉例而言,介電層34之吸附相對於犧牲層48上之吸附的選擇性可大於約5:1,例如約7.5:1、約30:1、或大於30:1。選擇性可取決於所使用的各種材料及/或形成製程。以下針對第8圖描述,以這種方式,犧牲層48沒有被阻障層50覆蓋(或僅部分地被覆蓋),因此可藉由沉積後處理52更容易地移除犧牲層48。在一些情況下,犧牲層48的這些材料特性可能導致除了導電填充材料28之外,犧牲層48的一定數量的材料黏著或鍵結至金屬硬遮罩37 ,儘管在其他情況下,不形成任何材料於金屬硬遮罩37上。可藉由合適的技術來沉積犧牲層48,例如濕式化學浸泡或暴露於化學氣體,這可取決於構成犧牲層48的特定材料。
作為第一示例,犧牲層48可包括具有化學式C6
H4
N3
H的苯並三唑(benzotriazole, BTA)。BTA分子具有三個氮原子的第一面,上述氮原子可與例如銅的金屬鍵結,且BTA分子具有疏水苯環的第二面,阻障層50的前驅物不能與上述疏水苯環鍵結。BTA分子的第一面可與導電填充材料28鍵結,而第二面突出並阻止前驅物與導電填充材料28鍵結。以這種方式,犧牲層48包括BTA單層或BTA的複數個單層可防止阻障層50形成於導電填充材料28上或於犧牲層48上。在一些實施例中,可藉由將封裝元件100浸泡於含有BTA的濕化學溶液中而由BTA來形成犧牲層48。舉例而言,BTA可為包含H2
O及/或H2
O2
之溶液的一部分,儘管可使用具有其他組成的溶液。可將溶液加熱至約25℃至約50℃之間的溫度,並且可將封裝元件100浸泡約10秒至約60秒之間的時間。將封裝元件100浸泡於溶液中之後,可對封裝元件100進行濕式清潔製程。可使用除了這些之外的其他溶液、製程條件、或技術來形成包括BTA的犧牲層48。所述的材料及沉積技術為示例,並且可使用濕化學浸泡製程由例如下列其他材料來形成犧牲層48:雙三唑基吲哚胺(bis-triazolyl indoleamine)、硫醇(thiol)、磷酸鹽(phosphate)等、或其組合。
作為第二示例,犧牲層48可包括具有化學式C10
H18
的5-癸炔(5-Decyne)。5-癸炔分子可與例如銅的金屬形成鍵結,並且還可藉由凡得瓦爾力(van der Waals forces)彼此連接,但是5-癸炔分子並未與介電層34鍵結。此外,阻障層50的前驅物不與5-癸炔分子形成鍵結。以這種方式,包括一層5-癸炔分子的犧牲層48可防止於導電填充材料28上或犧牲層48上形成阻障層50。在一些實施例中,可藉由將封裝元件100暴露於包含5-癸炔分子的氣體混合物中而由5-癸炔來形成犧牲層48。舉例而言,5-癸炔可為包括載體氣體之氣體混合物的一部分,上述載體氣體例如He、Ar等,儘管可使用其他混合物。氣體混合物可流送進處理腔室中,上述處理腔室可為在其中進行例如下列其他製程的同一處理腔室:蝕刻製程、阻障層50的沉積、沉積後處理52、或其他製程。藉由以這種方式“原位” (in-situ)沉積犧牲層48,可減少封裝元件100的污染、成本、或整個製程時間。氣體混合物可以約600sccm至約3000sccm之間的流速流送進處理腔室中約10秒至約120秒之間的時間長度。可使用約100℃至約350℃之間的製程溫度,並且可使用約1Torr至約30Torr之間的製程壓力。可使用除了這些以外的其他氣體混合物、製程條件、或技術來形成包括5-癸炔的犧牲層48。所述的材料及沉積技術為一示例,並且可藉由使用氣體沉積製程由例如下列的其它材料來形成犧牲層48:氣相硫醇、氣相BTA、炔烴、烯烴等、或其組合。
參見第6A圖及第6B圖,係根據一些實施例,將導電阻障層50沉積於導孔開口42及溝槽44內的表面上。阻障層50具有防止隨後沉積之導電材料56(第9圖)中的原子擴散進介電層34中的功能。阻障層50形成於介電層34及蝕刻停止層32的露出表面上,但是犧牲層48阻止阻障層50形成於導電填充材料28上。此外,如前文所述,阻障層50並未顯著地形成於犧牲層48的露出表面上。阻障層50可包括例如下列阻障材料:鈦、氮化鈦、鉭、氮化鉭等、或其組合。在一些實施例中,阻障層50額外地包括摻雜金屬,上述摻雜金屬可為過渡金屬、另一種金屬等、或其組合,上述過渡金屬例如Ru、Co、Mn、Al、Nb等。阻障層50內包含摻雜金屬允許了更緻密(denser)的阻障層50,其可提供更佳的防止擴散,並且包含摻雜金屬也可改善阻障層50的熱穩定性及黏著性。第6A圖繪示出一實施例,其中將摻雜金屬(例如,Ru)與阻障材料(例如,TaN)一起沉積以形成阻障層50,並且第6B圖繪示出阻障層50包括摻雜金屬(例如,Ru )之子層51B的一實施例,上述子層51B位於阻障材料(例如,TaN)的兩個子層51A、51C之間。在一些情況下,藉由形成包括摻雜金屬的阻障層50,可形成具有大於約13g/cm3
之總密度的阻障層50。
在一些實施例中,可使用例如ALD製程及/或CVD製程的合適製程來沉積阻障層50。在一些情況下,相較於例如PVD製程的其他製程,使用ALD製程及/或CVD製程來形成阻障層50可允許更好的階梯覆蓋及更好的順應性。在一些實施例中,可在與形成犧牲層48相同的處理腔室中進行阻障層50的沉積。在一些實施例中,可將阻障層50形成為具有介於約10Å至約60Å之間的厚度T2,例如約15Å。
參見第6A圖,可使用沉積阻障材料以及摻雜金屬的製程來沉積阻障層50。可沉積阻障層50,使得阻障層50包括所需之濃度的摻雜金屬。在一些實施例中,可將阻障層50形成為具有介於約5%原子百分比至約30%原子百分比之間之摻雜金屬的濃度,但是其他濃度也是可能的。在一些情況下,較高濃度的摻雜金屬會降低阻障層50的電阻率(resistivity)。舉例而言,摻雜10%原子百分比Ru之TaN的阻障層50可具有的電阻率為無摻雜之TaN的阻障層50的電阻率的約59%,並且摻雜20%原子百分比Ru之TaN的阻障層50可具有的電阻率為無摻雜之TaN的阻障層50的電阻率的約17%。這些是示例,在其他情況下電阻率的降低可能不同。在一些實施例中,可藉由進行沉積後處理52(參照第8圖)來進一步減小阻障層50的電阻率。此外,較高濃度的摻雜金屬可導致更緻密的阻障層50,並且可導致阻障層50在沉積後處理52之後具有較低的氮濃度。
可使用包括進行一次或多次ALD循環的ALD製程來沉積阻障層50,其中每個ALD循環沉積一層材料。ALD循環可包括將阻障材料的前驅物引進處理腔室中,隨後使用驅氣(purging gas)驅淨(purging)處理腔室,然後將摻雜金屬的前驅物引進處理腔室中,隨後驅淨處理腔室。阻障材料及/或摻雜金屬可具有多於一個前驅物,可將每個前驅物引進處理腔室中,隨後進行相對應的驅淨。可將ALD循環重複多次,以將阻障層50沉積到所期望之厚度T2。舉例而言,可進行ALD循環介於約10次至約80次之間,儘管ALD循環可進行比這些次數更多或更少的次數。
參見第7A圖,係根據一些實施例,繪示出用於沉積阻障層50之ALD製程的例示性ALD循環。儘管在其他情況下可使用其他ALD循環,但是可使用第7A圖所示的ALD循環來沉積類似於第6A圖所示的阻障層50。第7A圖所示的例示性ALD循環包括三個步驟。在ALD循環的第一步中,阻障材料的第一前驅物P1在一段時間內流送進處理腔室中,然後驅氣在一段時間內流送進處理腔室中。在第二步中,將阻障材料的第二前驅物P2流送進處理腔室中,然後將驅氣流送進處理腔室中。在這例示性ALD循環中,步驟1及步驟2一起形成阻障材料的一個或多個單層。在第三步中,將摻雜金屬的前驅物D1流送進處理腔室中,然後將驅氣流送進處理腔室中。在一些情況下,可藉由控制第三步的參數來控制阻障層50內摻雜金屬的濃度,例如前驅物D1的流速或前驅物D1流送進處理腔室中的時間長度。舉例而言,較大的D1之流速或以較長時間流送D1可導致在步驟2之後於阻障材料表面上形成更多的摻雜金屬,因此可增加阻障層50中摻雜金屬的濃度。在一些情況下,在形成阻障層50之一些單獨的ALD循環中,可跳過步驟3,這可能導致阻障層50中較低的摻雜金屬的濃度。
根據本揭露的一些實施例,阻障層50包括將TaN作為阻障材料並且將Ru或Co作為摻雜金屬,並且使用ALD製程來沉積阻障層50。TaN的前驅物可包括例如將五(二甲氨基)鉭(Pentakis Dimethylamino Tantalum, “ PDMAT”)作為第一前驅物(例如,第7A圖中的P1)並將氨作為相對應的第二前驅物(例如,P2),上述PDMAT具有化學式為C10
H30
N5
Ta,上述氨具有化學式NH3
。在一些實施例中,沉積Ru作為摻雜金屬可使用三羰基(1-甲基-1,4-環己二烯基)釕(ruthenium tricarbonyl(1-methyl-1,4 cyclohexadiene),“ CHORuS”)作為前驅物(例如,D1),並且沉積Co作為摻雜金屬可使用羰基叔丁基乙炔基鈷(cobalt carbonyl tertiary-butyl acetylene, “ CCTBA”)作為前驅物(例如,D1)。其他前驅物或前驅物的組合可用於形成阻障材料或摻雜金屬。在一些實施例中,在ALD循環中,PDMAT以約500sccm至約1500sccm之間的流速流送進處理腔室中,並且氨以約500sccm至約3000sccm之間的流速流送進處理腔室中。在一些實施例中,流送PDMAT約1秒至約5秒之間,並且流送氨約1秒至約5秒之間。在一些實施例中,CHORuS以介於約50sccm至約300sccm之間的流速流送進處理腔室中,並且以介於約1秒至約10秒之間的時間長度流送。驅氣可例如為Ar,其可以約1000sccm至約3000sccm之間的驅淨流速流送進處理腔室中,並且可流送約1秒至約5秒之間。在一些實施例中,以介於約200 ℃至約350 ℃之間的製程溫度及介於約1Torr至約5Torr之間的製程壓力進行ALD循環。除了這些以外的其他製程參數也是可能的。
參見第6B圖,係根據一些實施例,可藉由沉積阻障材料及摻雜金屬的交替子層(alternating sublayers)來形成阻障層50。舉例而言,第6B圖繪示出一實施例,其中將阻障材料的子層51A沉積,然後將摻雜金屬的子層51B沉積於子層51A上方,然後將阻障材料的子層51C沉積於子層51B上方。第6B圖繪示出阻障層50在阻障材料的兩個子層之間具有摻雜金屬的單一子層的實施例,但是在其他實施例中,阻障層50相較於所繪示的可具有更多摻雜金屬的子層或更多阻障材料的子層。在一些實施例中,摻雜金屬的(多個)子層可具有介於約1Å至約6Å之間的厚度TB,例如約3Å。在一些實施例中,阻障材料的子層可具有介於約10Å至約60Å之間的厚度,例如約20Å。阻障層50的不同子層可具有不同的厚度,包括相同材料的不同子層。摻雜金屬的更多子層及/或更厚的子層可增加阻障層50的整體密度,因此可提高阻障層50阻止擴散的能力。
在一些實施例中,使用包括ALD循環的沉積製程來形成阻障層50,上述ALD循環進行一次或多次以沉積阻障材料的子層(例如,子層51A),隨後進行CVD製程以沉積摻雜金屬(例如,子層51B)的子層。藉由重複沉積製程,可沉積阻障材料及摻雜金屬的交替層以形成阻障層50。可沉積阻障材料的最終子層(例如,子層51C)。在一些實施例中,可進行ALD循環介於一次至約10次之間,以沉積阻障材料的子層至所期望之厚度,儘管在其他實施例中可進行多次ALD循環。可使用相同的處理腔室來進行(多個)ALD循環及CVD製程。
參見第7B圖,係根據一些實施例,繪示出用於沉積阻障層50的例示性沉積製程。儘管在其他情況下可使用其他沉積製程,但是可使用第7B圖中所示的沉積製程來沉積類似於第6B圖所示的阻障層50。第7B圖中所示的例示性沉積製程具有三個階段,包括標記為“ ALD循環A”的第一ALD循環、標記為“ CVD製程B”的CVD製程、及標記為“ ALD循環C”的第二ALD循環。在第一階段中,進行ALD循環A一次或多次,以沉積阻障材料的子層(例如,子層51A)。ALD循環A可包括類似於第7A圖中所示的ALD循環的步驟。舉例而言,ALD循環A可包括類似於第7A圖中的步驟1的第一步及類似於第7A圖中的步驟2的第二步。在第二階段中,進行CVD製程B以沉積摻雜金屬的子層(例如,子層51B)。CVD製程B可包括例如使摻雜金屬的前驅物D1流送進處理腔室中,然後使驅氣流送進處理腔室中。在前驅物D1流送的同時,其他氣體G1也可流送進處理腔室中。在一些情況下,可藉由控制CVD製程B的參數來控制摻雜金屬的子層的厚度,上述CVD製程B的參數例如前驅物D1的流速或前驅物D1流送進處理腔室中的時間長度。舉例而言,較大的D1的流速或以較長時間流送D1可於阻障材料表面上沉積較厚的摻雜金屬層。
根據本揭露的一些實施例,阻障層50包含包括TaN的阻障材料子層以及包括Ru的(多個)摻雜金屬子層。TaN的前驅物(例如,P1及P2)可包含例如PDMAT及氨。Ru的前驅物(例如,D1)可包含例如CHORuS。其他前驅物或前驅物的組合可用於形成阻障材料或摻雜金屬。氣體G1可包含例如H2
、另一種氣體、或氣體混合物。在一些實施例中,在ALD循環中,PDMAT以約500sccm至約1500sccm之間的流速流送進處理腔室中,並且氨以約500sccm至約3000sccm之間的流速流送進處理腔室中。在一些實施例中,PDMAT流送約1秒至約5秒之間,並且氨流送介於約1秒至約5秒之間。在一些實施例中,在介於約200 ℃至約350 ℃之間的製程溫度以及介於約1Torr至約5Torr的製程壓力下進行ALD循環。在一些實施例中,在CVD製程中,CHORuS以介於約50sccm至約300sccm之間的流速流送進處理腔室中,並流送約1秒至約10秒之間的時間長度。在一些實施例中,H2
以約500sccm至約5000sccm之間的流速流送進處理腔室中,並流送介於約1秒至約10秒之間的時間長度。CHORuS及H2
可同時流送進處理腔室中。在一些實施例中,在介於約150℃至約300℃之間的製程溫度以及介於約1Torr至約15Torr之間的製程壓力下進行CVD製程。驅氣可例如為Ar,其可以約1000sccm至約3000sccm之間的驅淨流速流送進處理腔室中,並且可流送約1秒至約5秒之間。除了這些以外的其他製程參數也是可能的。
參見第8圖,係根據一些實施例,進行沉積後處理52以移除犧牲層48並露出導電填充材料28。沉積後處理52可藉由減少阻障層50的氮含量並藉由降低阻障層50的電阻率來提高阻障層50的性能。在一些情況下,沉積後處理52也可改善阻障層50的黏著力。在進行沉積後處理52之後,可將阻障層50與導電填充材料28以距離T1'間隔開,上述距離T1'可近似於犧牲層48的厚度T1。舉例而言,距離T1'可介於約0.5nm至約5nm之間,儘管其它的距離是可能的。如第8圖所示,沉積後處理52可露出先前被犧牲層48所覆蓋之蝕刻停止層32的側壁。
在一些實施例中,沉積後處理52包括例如退火製程的熱處理。舉例而言,退火製程可包括於退火腔室中在介於約250℃至約400 ℃之間的溫度下將封裝元件100退火約30秒至約300秒之間的時間。在退火製程中,可將封裝元件100暴露於一種或多種氣體,例如惰性氣體(例如,He、Ar等)、還原性氣體(例如,H2
等)、或其組合。(多種)氣體可以介於約600sccm至約3000sccm之間的流速流送進退火腔室中。在退火製程期間,退火腔室可具有介於約1 Torr至約30Torr之間的壓力。包含退火製程的沉積後處理52可具有除了這些之外的其他退火參數。在一些實施例中,退火腔室與用於沉積阻障層50的處理腔室為相同的腔室。
在一些實施例中,沉積後處理52包括電漿處理。舉例而言,電漿處理可包含將封裝元件100暴露於一種或多種例如下列之處理氣體的電漿:H2
、NH3
、Ar等、或其組合。處理氣體可以約600sccm至約3000sccm之間的流速流送。可在介於約0.1Torr至約5Torr之間的壓力下進行電漿處理。在一些實施例中,使用約100瓦特至約600瓦特之間的功率來產生電漿。可在介於約25℃至約400℃之間的溫度下進行電漿處理,並且可進行約10秒至約30秒之間的時間。包含電漿處理的沉積後處理52可具有除了這些以外的其他參數。在一些實施例中,使用與用於沉積阻障層50的處理腔室相同的腔室進行電漿處理。在一些實施例中,進行退火處理或電漿處理中的一種。在其他實施例中,退火製程以及電漿處理皆可進行,且可以任何順序進行。
沉積後處理52可減少在阻障層50內氮的濃度,而可緻密化(densify)阻障層50。藉由以這種方式增加阻障層50的密度,可使阻障層50更有效地阻擋擴散進介電層34中。在一些情況下,沉積後處理52可將阻障層50中氮對鉭的比例(N:Ta)減小約一半。在一些情況下,在進行沉積後處理52之後,阻障層50可具有約0.65:1的N:Ta比例。然而,應注意的是,氮的減少可大於或小於這些實例,取決於沉積後處理52的製程細節及/或阻障層50的組成。
沉積後處理52可減小阻障層50的電阻率,從而可提高裝置性能。舉例而言,進行沉積後處理52之後的阻障層50的電阻率可為進行沉積後處理52之前的阻障層50的電阻率的約7%。在一些情況下,進行沉積後處理之後的阻障層50可具有小於200 µΩ-cm的電阻率。然而,應注意的是,電阻率的降低可大於或小於這些示例,取決於沉積後處理52的製程細節及/或阻障層50的組成。
參見第9圖,係根據一些實施例,沉積導電材料56以填充導孔開口42及溝槽44。可例如藉由下列製程來沉積導電材料56:使用物理氣相沉積(Physical Vapor Deposition, PVD)進行毯覆式(blanket)沉積以形成金屬晶種層(例如,銅層),然後使用例如電鍍、無電鍍、沉積等來填充導孔開口42及溝槽44的其餘部分。導電材料56可包括銅、銅合金、鈷、鎢等、其他金屬、或其組合。
藉由阻止於導電填充材料28上形成阻障層50 (參照第6A圖至第6B圖),將導電材料56沉積於露出的導電填充材料28上,從而於導電材料56及導電填充材料28之間形成“無阻障”(barrier-free)界面。在一些情況下,無阻障界面的接觸電阻(contact resistance, Rc)小於在導電材料56及導電填充材料28之間延伸有阻障層50的接觸電阻。此外,藉由將導電材料56形成於導電填充材料28上,可提高導電材料56及導電填充材料28之間的界面的熱穩定性。以這種方式,本文所述的技術可允許(藉由摻入摻雜金屬)形成緻密的阻障層50,並且可改善導孔58及金屬線60之間的接觸電阻(參照第10圖)。如第9圖所示,由於阻障層50與導電填充材料28之間的間隔距離T1',導電材料56可接觸未被阻障層50所覆蓋之蝕刻停止層32的側壁。以這種方式,部分的導電材料56可延伸於阻障層50下方,並且可將位於導電材料56以及導電填充材料28之間的界面形成為具有更大的橫向寬度。
參見第10圖,係根據一些實施例,可進行平坦化製程以移除導電材料56的多餘部分,因而形成導孔58及金屬線60,上述平坦化製程例如化學機械平坦化(Chemical Mechanical Planarization, CMP)製程、機械拋光製程、及/或研磨製程。導孔58及金屬線60各自包括阻障層50的一部分及導電材料56的一部分。第10圖也繪示出介電蝕刻停止層62的形成,其覆蓋並接觸介電層34及金屬線60。根據一些實施例,介電蝕刻停止層62由例如下列材料的一層或多層所形成:金屬氧化物、金屬氮化物、金屬碳氮化物、氮化矽等、或其組合。
本揭露的實施例具有一些有利特徵。藉由使用犧牲層來阻擋阻障層形成於導電部件上,可形成(例如,導孔的)導電材料直接接觸導電部件。這可減小導電部件及導電材料之間的界面的接觸電阻,從而可改善裝置性能。這也可提高界面的熱穩定性,從而可減少裝置的依時性介電質崩潰(time-dependent dielectric breakdown, TDDB)並提高產率。此外,藉由形成摻有摻雜金屬的阻障層,可增加阻障層的密度,從而可提高阻障層的擴散阻擋(diffusion-blocking)能力。這也可允許使用更保形的製程代替較不保形的沉積製程來形成有效緻密的阻障層,上述更保形的製程例如ALD或CVD。可在整個阻障層中摻入摻雜金屬,或者在阻障層內形成摻雜金屬的一個或多個子層。以這種方式形成的阻障層也可具有改善的粘合性及改善的電阻率。
根據本揭露的一些實施例,一種半導體裝置的形成方法,包括:形成導電部件於第一介電層中;形成第二介電層於導電部件上方;蝕刻開口穿過第二介電層,蝕刻露出導電部件的表面;沉積犧牲層於開口中,其中犧牲層選擇性地形成在導電部件的露出表面上,多於形成在第二介電層的表面上;沉積阻障層於開口中,其中選擇性地形成阻障層於犧牲層上方之第二介電層的表面上,其中沉積阻障層的步驟包括:由一個或多個第一前驅物沉積導電阻障材料;及在沉積導電阻障材料之後,由一個或多個第二前驅物沉積摻雜金屬;移除犧牲層;及沉積導電材料,以填充開口,導電材料接觸導電部件。在一實施例中,移除犧牲層的步驟包括進行電漿處理製程。在一實施例中,電漿處理製程增加了阻障層的密度。在一實施例中,沉積阻障層的步驟包括原子層沉積(Atomic Layer Deposition, ALD)製程。在一實施例中,導電阻障材料的步驟包括化學氣相沉積(Chemical Vapor Deposition, CVD)製程。
在一實施例中,藉由塗敷苯並三唑(benzotriazole, BTA)於導電部件的露出表面上來形成犧牲層。在一實施例中,摻雜金屬為釕。在一實施例中,導電阻障材料為氮化鉭。在一實施例中,沉積導電阻障材料的步驟包括沉積導電阻障材料的第一層,其中沉積摻雜金屬的步驟包括沉積一層摻雜金屬,並且更包括沉積導電阻障材料的第二層於一層摻雜金屬上。
根據本揭露的一些實施例,一種半導體裝置的形成方法,包括:形成絕緣層於導電部件上方;蝕刻絕緣層,以露出導電部件的第一表面;用犧牲材料覆蓋導電部件的第一表面,其中絕緣層的側壁沒有犧牲材料;用阻障材料覆蓋絕緣層的側壁,其中導電部件的第一表面沒有阻障材料,其中阻障材料包括摻雜過渡金屬的氮化鉭(tantalum nitride, TaN);移除犧牲材料;及用導電材料覆蓋阻障材料及導電部件的第一表面。在一實施例中,半導體裝置的形成方法形成蝕刻停止層於導電部件上方。在一實施例中,阻障層具有介於5%至30%原子百分比之過渡金屬。在一實施例中,犧牲材料包括苯並三唑(benzotriazole, BTA)。在一實施例中,移除犧牲材料的步驟包括使用氫氣(hydrogen, H2
)作為處理氣體的熱處理。
根據本揭露的一些實施例,一種半導體裝置,包括:第一導電部件,位於第一介電層中;蝕刻停止層,位於第一導電部件上方;第二介電層,位於蝕刻停止層上方;及第二導電部件,延伸穿過第二介電層及蝕刻停止層,以實體接觸第一導電部件,其中第二導電部件包括:阻障層,連續延伸於第二介電層的側壁上及蝕刻停止層的側壁上,其中阻障層包括一層過渡金屬,位於金屬氮化物的第一層及金屬氮化物的第二層之間;及導電填充材料,位於阻障層上方,其中導電填充材料延伸於阻障層及第一導電部件之間。在一實施例中,阻障層部分地覆該蝕刻停止層的側壁。在一實施例中,導電填充材料實體接觸蝕刻停止層的側壁。在一實施例中,過渡金屬為釕。在一實施例中,過渡金屬的層具有介於1Å至6Å的厚度。在一實施例中,阻障層的底部與第一導電部件的頂部垂直分離。
以上概述數個實施例之部件,以便在本發明所屬技術領域中具有通常知識者可更加理解本發明實施例的觀點。在本發明所屬技術領域中具有通常知識者應理解,他們能輕易地以本發明實施例為基礎,設計或修改其他製程及結構,以達到與在此介紹的實施例相同之目的及/或優勢。在本發明所屬技術領域中具有通常知識者也應理解,此類等效的結構並無悖離本發明的精神與範圍,且他們能在不悖離本發明之精神及範圍下,做各式各樣的改變、取代及替代。
20:半導體基板
22:整合電路裝置
24:介電層
26:擴散阻障層
28:導電填充材料
30:導電部件
32:蝕刻停止層
34:介電層
37:金屬硬遮罩
38:開口
40:光阻
42:導孔開口
44:溝槽
48:犧牲層
50:阻障層
51A:子層
51B:子層
51C:子層
52:沉積後處理
56:導電材料
58:導孔
60:金屬線
62:介電蝕刻停止層
100:封裝元件
T0:厚度
T1:厚度
T1' :厚度
T2:厚度
TB:厚度
D1:前驅物
P1:前驅物
P2:前驅物
G1:氣體
本揭露的各面向從以下詳細描述中配合附圖可最好地被理解。應強調的是,依據業界的標準做法,各種部件並未按照比例繪製且僅用於說明的目的。事實上,為了清楚討論,各種部件的尺寸可任意放大或縮小。
第1圖、第2圖、第3圖及第4圖係根據一些實施例,繪示出在形成金屬線及導孔的中間階段的剖面圖。
第5圖係根據一些實施例,繪示出在形成犧牲材料的中間階段的剖面圖。
第6A圖及第6B圖係根據一些實施例,繪示出在形成阻障層的中間階段的剖面圖。
第7A圖及第7B圖係根據一些實施例,繪示出在形成阻障層期間使用的沉積循環。
第8圖、第9圖及第10圖係根據一些實施例,繪示出形成金屬線及導孔的中間階段的剖面圖。
20:半導體基板
22:整合電路裝置
24:介電層
26:擴散阻障層
28:導電填充材料
30:導電部件
32:蝕刻停止層
34:介電層
37:金屬硬遮罩
42:導孔開口
44:溝槽
50:阻障層
56:導電材料
100:封裝元件
T1':厚度
Claims (13)
- 一種半導體裝置的形成方法,包括:形成一導電部件於一第一介電層中;形成一第二介電層於該導電部件上方;蝕刻一開口穿過該第二介電層,該蝕刻露出該導電部件的一表面;沉積一犧牲層於該開口中,其中該犧牲層選擇性地形成在該導電部件的該露出表面上,多於形成在該第二介電層的表面上;沉積一阻障層於該開口中,其中選擇性地形成該阻障層於該犧牲層上方之該第二介電層的表面上,其中沉積該阻障層的步驟包括:由一個或多個第一前驅物沉積一導電阻障材料;及在沉積該導電阻障材料之後,由一個或多個第二前驅物沉積一摻雜金屬;移除該犧牲層;及沉積一導電材料,以填充該開口,該導電材料接觸該導電部件,其中該阻障層的一底部與該導電部件的一頂部垂直分離。
- 如請求項1所述之半導體裝置的形成方法,其中移除該犧牲層的步驟包括進行一電漿處理製程,且其中該電漿處理製程增加了該阻障層的密度。
- 如請求項1所述之半導體裝置的形成方法,其中沉積該阻障層的步驟包括一原子層沉積(Atomic Layer Deposition,ALD)製程、或一原子層沉積製程及一化學氣相沉積(Chemical Vapor Deposition,CVD)製程。
- 如請求項1所述之半導體裝置的形成方法,其中藉由塗敷苯並三唑(benzotriazole,BTA)於該導電部件的該露出表面上來形成該犧牲層。
- 如請求項1所述之半導體裝置的形成方法,其中該摻雜金屬為釕,且其中該導電阻障材料為氮化鉭。
- 如請求項1至5中任一項所述之半導體裝置的形成方法,其中沉積該導電阻障材料的步驟包括沉積該導電阻障材料的一第一層,其中沉積該摻雜金屬的步驟包括沉積一層該摻雜金屬,並且更包括沉積該導電阻障材料的一第二層於該層摻雜金屬上。
- 一種半導體裝置的形成方法,包括:形成一絕緣層於一導電部件上方;蝕刻該絕緣層,以露出該導電部件的一第一表面;用一犧牲材料覆蓋該導電部件的該第一表面,其中該絕緣層的側壁沒有該犧牲材料;用一阻障材料覆蓋該絕緣層的側壁,其中該導電部件的該第一表面沒有該阻障材料,其中該阻障材料包括摻雜一過渡金屬的氮化鉭(tantalum nitride,TaN);移除該犧牲材料;及用一導電材料覆蓋該阻障材料及該導電部件的該第一表面,其中該阻障材料的一底部與該導電部件的一頂部垂直分離。
- 如請求項7所述之半導體裝置的形成方法,更包括形成一蝕刻停止層於該導電部件上方。
- 如請求項7所述之半導體裝置的形成方法,其中該阻障層具有介於5%至30%原子百分比之該過渡金屬。
- 如請求項7至9中任一項所述之半導體裝置的形成方法,其中移除該犧牲材料的步驟包括使用氫氣(hydrogen,H2)作為處理氣體的一熱處理。
- 一種半導體裝置,包括:一第一導電部件,位於一第一介電層中;一蝕刻停止層,位於該第一導電部件上方;一第二介電層,位於該蝕刻停止層上方;及一第二導電部件,延伸穿過該第二介電層及該蝕刻停止層,以實體接觸該第一導電部件,其中該第二導電部件包括:一阻障層,連續延伸於該第二介電層的側壁上及該蝕刻停止層的側壁上,其中該阻障層包括一層過渡金屬,位於一金屬氮化物的一第一層及該金屬氮化物的一第二層之間;及一導電填充材料,位於該阻障層上方,其中該導電填充材料延伸於該阻障層及該第一導電部件之間,其中該阻障層的一底部與該第一導電部件的一頂部垂直分離。
- 如請求項11所述之半導體裝置,其中該阻障層部分地覆蓋該蝕刻停止層的側壁,且其中該導電填充材料實體接觸該蝕刻停止層的側壁。
- 如請求項11所述之半導體裝置,其中該過渡金屬為釕,且其中該過渡金屬的該層具有介於1Å至6Å的厚度。
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- 2020-07-21 DE DE102020119184.7A patent/DE102020119184A1/de active Pending
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-
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Also Published As
Publication number | Publication date |
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TW202147519A (zh) | 2021-12-16 |
US20220367376A1 (en) | 2022-11-17 |
KR20210154687A (ko) | 2021-12-21 |
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