TWI793548B - Circuit structure and method for automatically adjusting pcie channel configuration - Google Patents

Abstract

A circuit structure and method for automatically adjusting PCIe channel configuration. The circuit structure includes a plurality of PCIe riser cards and a motherboard. The plurality of PCIe riser cards include at least two channel specifications of PCIe riser cards, and each channel specification of PCIe riser cards has a PCIe specification identification code. The motherboard includes a plurality of PCIe ports, a CPLD module, a storage unit, a BMC module, and a BIOS unit. The PCIe ports are respectively electrically connected to the PCIe riser card through PCIe transmission lines. The CPLD module is electrically connected to the PCIe port for reading the PCIe specification identification code and the in-position signal to compare the current configuration information. The storage unit stores a PCIe default configuration information. The BMC module sends out a matching signal when the current configuration information matches the PCIe default configuration information, so that the BIOS unit can be booted and operated accordingly.

Description

Circuit structure and method for automatically adjusting PCIe channel configuration

The present invention relates to a circuit structure and method for automatically adjusting configuration settings, in particular to a circuit structure and method for automatically adjusting PCIe channel configuration.

In the existing server system, there are usually multiple PCIe slots on the motherboard to allow users to install PCIe devices, and the EEPROM on the motherboard will also pre-store the configuration information of the PCIe slots for the operating system to use. The configuration information of the PCIe slot is used to allocate the PCIe slot and the PCIe channel of the CPU, so that there will be no problem that the PCIe device cannot be recognized. However, due to the vigorous development of the network industry in recent years, the demand for processing power of the server is also increasing. In order to improve the performance of the server, the manufacturer of the server system uses multiple A Slimline X8 connector is used as a PCIe port to replace the original PCIe slot, so that more Slimline X8 connectors or other components can be set by removing the space saved by the PCIe slot.

As shown in the first figure, the first figure shows a system block diagram of a prior art server motherboard connected to an adapter card through a PCIe port. As shown in the figure, a motherboard PA100 includes a CPLD module PA1, an X4 connection port PA2, an X8 connection port PA3 and an X16 connection port PA4. Among them, the X4 connection port PA2 is used for inserting the PCIe transmission line, and then electrically connected to an adapter card with an X4 PCIe slot; the X8 connection port PA3 is used for inserting the PCIe transmission line, and then electrically connected to a riser card with an X4 PCIe slot; A riser card with an X8 PCIe slot; the X16 port PA4 is used for inserting a PCIe transmission line, and then electrically connected to a riser card with an X16 PCIe slot.

Based on the above, X4 port PA2, X8 port PA3, and X16 port PA4 are all Slimline X8 connectors, so that X4 port PA2, X8 port PA3, and X16 port PA4 can be respectively connected to The X4 PCIe slot PA201 of the riser card PA200, the X8 PCIe slot PA301 of the riser card PA300, and the X16 PCIe slot PA401 of the riser card PA400; among them, the X16 port PA4 uses two Slimline X8 connectors and two An X8-channel PCIe transmission cable is used to connect to the two Slimline X8 connectors on the riser card, so that the X16 PCIe slot can be electrically connected to the CPLD module PA1 through the X16 channel.

However, in the prior art, the CPLD module PA1 still reads the PCIe slot configuration information pre-stored in the EEPROM to determine the number of channels of the X4 connection port PA2, the X8 connection port PA3 and the X16 connection port PA4, so the X4 connection port PA2 It can only be connected to the riser card with the corresponding channel through the PCIe transmission cable, the X8 port PA3 can only be connected to the riser card with the corresponding channel through the PCIe transmission cable, and the X16 port PA4 can only be connected to the corresponding channel through the PCIe transmission cable riser card. It can be seen that when any of the X4 port PA2, X8 port PA3, and X16 port PA4 is not connected to a riser card that matches the channel, it will cause the motherboard PA100 to fail to operate normally. It is especially easy to happen when the number of ports is large, and it is easy for users to plug in the wrong riser card because the PCIe transmission lines connecting the PCIe ports are all the same.

In view of the prior art, in order to reduce the space occupied by the PCIe slots, the motherboard used in the existing server mainly uses the Slimline X8 connector as the PCIe connection port, and cooperates with the PCIe transmission line to connect the PCIe riser card. When the number of PCIe ports is large, the number of PCIe transmission lines that are compatible with them is also large. At this time, it is easy for users to mistakenly connect to a riser card with inconsistent specifications because the specifications of the PCIe transmission lines are all the same, which will cause the server host to fail. normal operation; for this reason, the main purpose of the present invention is to provide a circuit structure for automatically adjusting PCIe channel configuration, without limiting the channel specification of each PCIe connection port, but after the PCIe transmission line is connected to the PCIe adapter card and then assigning each channel for each PCIe port.

In order to solve the problems of the prior art, the necessary technical means adopted by the present invention is to provide a circuit structure for automatically adjusting the configuration of PCIe channels, including a plurality of PCIe riser cards (risers) and a motherboard.

The plurality of PCIe riser cards include PCIe riser cards of at least two channel specifications, and each PCIe riser card of a channel specification has a PCIe specification identification code.

The motherboard includes a plurality of PCIe ports, a CPLD module, a storage unit, a BMC module and a BIOS unit. A plurality of PCIe connection ports are respectively electrically connected to the PCIe riser card through a plurality of PCIe transmission lines, and each PCIe connection port has a positioning pin. The CPLD module is electrically connected to the PCIe port, and is used to read the PCIe specification identification code corresponding to the PCIe riser card transmitted through the PCIe port, and to read the PCIe specification identification code transmitted through the in-position pin of the PCIe port. A plurality of present signals (Present) are compared to a current configuration information corresponding to the PCIe riser card according to a PCIe specification comparison table.

The storage unit stores a piece of PCIe default configuration information. The BMC module is electrically connected to the CPLD module and the storage unit, and is used to compare whether the current configuration information matches the PCIe default configuration information, and sends a pairing when the current configuration information matches the PCIe default configuration information match signal. The BIOS unit is electrically connected to the BMC module, and is used to adjust the configuration of the PCIe channel according to the current configuration information to start the operation when receiving the matching signal.

In one of the auxiliary technical means derived from the above necessary technical means, the BMC module analyzes the total number of PCIe riser cards and the total number of PCIe channels from the current configuration information, and compares the total number of PCIe riser cards and the total number of PCIe channels with the total number of When the total number of a default supported riser card matches the total number of a supported channel, a match signal is sent.

In one of the auxiliary technical means derived from the above-mentioned necessary technical means, the PCIe transmission lines are all Slimline SAS (SFF-8654) 8-Lane transmission lines.

In an auxiliary technical means derived from the above-mentioned necessary technical means, the PCIe riser card uses the ID codes transmitted by the three existing pins as the PCIe specification identification codes.

Another necessary technical means adopted by the present invention is to provide a method for automatically adjusting PCIe channel configuration, including the following steps ( A ) to ( E ). Step (A) is to use a plurality of PCIe transmission lines to electrically connect a plurality of PCIe riser cards (Risers) to a plurality of PCIe ports. Step ( B ) The PCIe riser card transmits a PCIe specification identification code to the PCIe connection port respectively through the PCIe transmission line. Step ( C ) is that the PCIe port transmits the PCIe specification identification code of the PCIe riser card and a present signal (Present) provided by the PCIe port to a CPLD module. Step ( D ) is that the CPLD module generates a current configuration information corresponding to the PCIe riser card by comparing the PCIe specification identification code of the PCIe riser card and the presence signal of the PCIe port according to a PCIe specification comparison table, and sends the current The configuration information is sent to a BMC module. Step ( E ) is that the BMC module compares whether the current configuration information is consistent with a PCIe default configuration information, and sends a matching signal to a BIOS unit when the current configuration information matches the PCIe default configuration information, so that the BIOS The unit adjusts the configuration of the PCIe channel according to the current configuration information and starts to operate.

In an auxiliary technical means derived from the above-mentioned necessary technical means, the PCIe riser card transmits an ID code through three in-position pins after receiving the in-position signal transmitted by the PCIe device.

As mentioned above, because the present invention uses the CPLD module to read the PCIe specification identification code corresponding to the PCIe riser card and the in-position signal transmitted by the PCIe connection port, and then compares a current configuration information, and further judges the current configuration Whether the information is consistent with the PCIe default configuration information drives the BIOS unit to adjust the configuration of the PCIe channel according to the current configuration information to start operation.

The specific embodiments adopted by the present invention will be further described by the following embodiments and drawings.

Please refer to the second figure and the third figure, the second figure shows the system block diagram of the circuit structure for automatically adjusting the PCIe channel configuration provided by the preferred embodiment of the present invention, and the third figure shows the system block diagram provided by the preferred embodiment of the present invention The circuit schematic diagram of the circuit structure for automatically adjusting the PCIe channel configuration. As shown in the second and third figures, a circuit structure 100 for automatically adjusting PCIe channel configuration includes a plurality of PCIe riser cards (Riser) 1, 2 and 3 (only three examples are used in this embodiment) and a motherboard4. Wherein, although in this embodiment, only three PCIe riser cards 1 , 2 and 3 are used for illustration, it is not limited to this in fact. In addition, in this embodiment, the PCIe riser cards 1, 2 and 3 respectively correspond to a channel specification and have a PCIe specification identification code respectively, and the PCIe specification identification code is used to identify that the PCIe riser card 1, 2 or 3 has PCIe lanes such as X4, X8 or X16.

Motherboard 4 includes a plurality of PCIe ports (only one PCIe port 41 is indicated in the second figure), a CPLD module 42 (only CPLD is indicated in the figure), a storage unit 43, and a BMC module 44 (indicated in the figure). Only the BMC is marked in the figure) and a PCH module 45 (only the PCH is marked in the figure).

As shown in the second figure, a plurality of PCIe ports 41 are respectively electrically connected to PCIe riser cards 1, 2 and 3 through a plurality of PCIe transmission lines C1, C2 and C3 (only three are marked in the figure), and The PCIe riser cards 1 , 2 and 3 are respectively used to connect the PCIe devices 200 , 300 and 400 . In this embodiment, the PCIe transmission lines C1 , C2 and C3 are transmission lines of the Slimline SAS 8-Lane specification (conforming to the SFF-8654 standard).

The CPLD module 42 is electrically connected to a plurality of PCIe ports 41 for reading the PCIe specification identification code corresponding to the PCIe riser card 1, 2 or 3 transmitted through the PCIe port 41, and reading the The plurality of present signals (Present) transmitted by the connection port 41 are compared to a current configuration information corresponding to the PCIe riser cards 1, 2 and 3 according to a PCIe specification comparison table.

Based on the above, the PCIe specification comparison table of this embodiment is, for example, the following table 1: PCIe specification ID0 ID1 ID2 X4 0 0 1 X8 0 1 0 X16 1 0 0 X4+X8 0 1 1 X4+X16 1 0 1 X8+X16 1 1 0

The storage unit 43 stores a PCIe default configuration information 431 . The BMC module 44 is electrically connected to the CPLD module 42 and the storage unit 43, and is used to analyze the total number of a PCIe riser card and the total number of a PCIe channel from the current configuration information, and calculate the total number of PCIe riser cards and the total number of PCIe channels When matching with one of the total number of supported riser cards and one of the total number of supported channels preset by the PCIe default configuration information 431 , a pair matching signal is sent. The PCH module 45 is electrically connected to the BMC module 44, and has a built-in BIOS unit 451 (only the BIOS is marked in the figure), and the BIOS unit 451 is used for matching according to the current The configuration information adjusts the configuration of the PCIe channel for boot operation.

Please continue to refer to the fourth figure. The fourth figure is a schematic plan view showing the circuit structure for automatically adjusting the PCIe channel configuration provided by the preferred embodiment of the present invention. As shown in the second figure to the fourth figure, the PCIe connection port 41 is illustrated by taking three PCIe connection ports 41a, 41b and 41c as an example in the schematic circuit diagram of the third figure, and in this embodiment, the PCIe transfer The card 1 has an X8 PCIe slot 11 , the PCIe riser card 2 has an X8 PCIe slot 21 , and the PCIe riser card 3 has an X4 PCIe slot 31 and an X16 PCIe slot 32 .

As mentioned above, in practice, since the PCIe riser card 1 has an X8 PCIe slot 11 , the PCIe riser card 1 is built with a PCIe specification identification code corresponding to the X8 PCIe slot 11 . In this embodiment, the PCIe specification identification code of the PCIe riser card 1 is used as the PCIe specification identification code through three ID codes such as ID0, ID1, and ID2, and the three ID codes of the PCIe riser card 1 are passed through PCIe. The present pin (X8 Present) of the X8 PCIe slot 11 of the connection card 1 receives the present signal transmitted by the PCIe device 200, and then transmits the ID code through three present pins (Present) of ID0, ID1 and ID2, And the three ID codes of the PCIe riser card 1 are 010 in this embodiment. According to the above-mentioned PCIe specification comparison table, it can be known that when the PCIe specification identification code of the PCIe riser card 1 is 010, it corresponds to the X8 channel. Specification.

As above, the PCIe riser card 2 has an X8 PCIe slot 21 , so the PCIe riser card 2 also has a built-in PCIe specification identification code corresponding to the X8 PCIe slot 21 . In this embodiment, the PCIe specification identification code of the PCIe riser card 2 is also used as the PCIe specification identification code through three ID codes such as ID0, ID1 and ID2, and the three ID codes of the PCIe riser card 2 are passed through PCIe The present pin (X8 Present) of the X8 PCIe slot 21 of the riser card 2 receives the present signal transmitted by the PCIe device 300, and then transmits the ID code through the three present pins of ID0, ID1 and ID2, and the PCIe The three ID codes of the riser card 2 are also 010 in this embodiment. According to the above-mentioned PCIe specification comparison table, it can be known that when the PCIe specification identification code of the PCIe riser card 2 is 010, it corresponds to the specification of the X8 channel .

In addition, the PCIe riser card 3 has an X4 PCIe slot 31 and an X16 PCIe slot 32 , so the PCIe riser card 3 has built-in PCIe specification identification codes corresponding to the X4 PCIe slot 31 and the X16 PCIe slot 32 . In this embodiment, the PCIe specification identification code of the PCIe riser card 3 is used as the PCIe specification identification code through three ID codes such as ID0, ID1, and ID2, and the three ID codes of the PCIe riser card 3 are passed through PCIe. The presence pin (X4 Present) of the X4 PCIe slot 31 of the connection card 3 and the presence pin (X16 Present) of the X16 PCIe slot 32 receive the presence signal transmitted by the PCIe device 400, and then use ID0, ID1 The ID codes are transmitted from the three in-position pins of ID2, and the three ID codes of the PCIe riser card 3 are 101 in this embodiment. According to the above-mentioned PCIe specification comparison table, it can be known that the PCIe riser card 3 When the PCIe specification identification code is 101, it corresponds to the specification of X4 channel + X16 channel. Wherein, since the PCIe riser card 3 has an X4 PCIe slot 31 and an X16 PCIe slot 32, the PCIe device 400 is actually a PCIe device with an X4 channel specification (not shown in the figure) and a PCIe device with an X16 channel specification (shown in the figure). not shown). In fact, since the connection between the PCIe riser card 3 and the PCIe port 41c is through the PCIe transmission line C3 for signal transmission, and the PCIe transmission line C3 is the transmission specification of the X8 channel in this embodiment, so three PCIe transmission lines C3 are required To connect the PCIe riser card 3 to the three PCIe ports 41c (one PCIe transmission line C3 corresponds to the PCIe device with X4 channel specification, and the other two PCIe transmission lines C3 correspond to the PCIe device with X16 channel specification).

Based on the above, in this embodiment, the three PCIe riser cards 1, 2 and 3, therefore the PCIe ports 41a, 41b and 41c can be identified by the voltage difference of the present signal (Present) of the PCIe transmission line C1, C2 and C3, for example, the voltage value of the present signal of the PCIe transmission line C1 is 0.3v, the voltage value of the in-position signal of PCIe transmission line C2 is 0.42v, the voltage value of the in-position signal of PCIe transmission line C3 is 0.67v, and then there will be three 0.67v in-position signals, it can be judged that there are three Set PCIe transmission line C3.

Please continue to refer to the second figure to the fourth figure. As shown in the second figure to the fourth figure, the CPLD module 42 receives the PCIe riser card 1, 2 through the PCIe connection port 41 (including 41a, 41b and 41c). After the ID code corresponding to the PCIe specification identification code and the in-position signals of the PCIe transmission lines C1, C2 and C3 transmitted by 3, the CPLD module 42 compares the corresponding PCIe riser cards 1, 2 and C3 according to the PCIe specification comparison table. 3. The current configuration information is two sets of X8 channels, one set of X4 channels and one set of X16 channels. At this time, the CPLD module 42 will send the current configuration information to the BMC module 44, and then the BMC module 44 will compare the current configuration information Whether (the total number of PCIe riser cards and the total number of PCIe channels) and the PCIe default configuration information 431 (the total number of supported riser cards and the total number of supported channels) are the same, and when the comparison is the same, send a match signal 44s to the PCH module 45, so that The BIOS unit 451 operates accordingly.

Generally speaking, on the basis of the above-mentioned circuit structure 100 for automatically adjusting PCIe channel configuration, the method for automatically adjusting PCIe channel configuration in the present invention is mainly to use a plurality of PCIe transmission lines C1, C2 and C3 to connect a plurality of PCIe adapter cards 1, 2, and 3 are respectively electrically connected to a plurality of PCIe ports 41a, 41b, and 41c; then, the PCIe riser cards 1, 2, and 3 transmit the PCIe specification identification code to PCIe respectively through PCIe transmission lines C1, C2, and C3 Connecting ports 41a, 41b and 41c; then, PCIe connecting ports 41a, 41b and 41c will then connect the PCIe specification identification codes of PCIe riser cards 1, 2 and 3 with the presence signals provided by PCIe connecting ports 41a, 41b and 41c Send it to the CPLD module 42; after that, the CPLD module 42 will compare the PCIe specification identification codes of the PCIe riser cards 1, 2 and 3 and the in-position signals of the PCIe connection ports 41a, 41b and 41c according to the PCIe specification comparison table to generate Corresponding to the current configuration information of the PCIe riser cards 1, 2 and 3, and sending the current configuration information to the BMC module 44; finally, the BMC module 44 will compare whether the current configuration information is consistent with the PCIe default configuration information 431, And when the current configuration information is consistent with the PCIe default configuration information 431, send a match signal 44s to the BIOS unit 451, so that the BIOS unit 451 adjusts the configuration of the PCIe channel according to the current configuration information and starts to operate.

To sum up, compared with the prior art server motherboards, when using the Slimline X8 connector and the PCIe transmission cable to connect the PCIe riser card, it is easy to mistakenly connect to the riser card with different specifications because the specifications of the PCIe transmission cables are all the same. , causing the server host to fail to operate normally; the present invention uses the CPLD module to read the PCIe specification identification code corresponding to the PCIe riser card and the in-position signal transmitted by the PCIe connection port, and compares a PCIe specification comparison table to obtain a The current configuration information, and further judge whether it matches by comparing the current configuration information with the PCIe default configuration information, and then drive the BIOS unit to adjust the configuration of the PCIe channel according to the current configuration information and start the operation. It is necessary to limit the docking relationship between the PCIe port and the PCIe riser card, but when the overall number of PCIe channels and riser cards conform to the PCIe default configuration information, the PCIe port and the PCIe riser card can be connected arbitrarily through the PCIe transmission line , Effectively enhance the convenience of use.

Through the above detailed description of the preferred embodiments, it is hoped that the characteristics and spirit of the present invention can be described more clearly, and the scope of the present invention is not limited by the preferred embodiments disclosed above. On the contrary, the intention is to cover various changes and equivalent arrangements within the scope of the patent application for the present invention.

PA100: Motherboard PA1: CPLD module PA2:X4 port PA3:X8 port PA4: X16 port PA200, PA300, PA400: riser card PA201:X4 PCIe slot PA301:X8 PCIe slot PA401:X16 PCIe slot 100: Circuit structure for automatic adjustment of PCIe channel configuration 1,2,3:PCIe riser card 11:X8 PCIe slot 21:X8 PCIe slot 31:X4 PCIe slot 32:X16 PCIe slot 4: Motherboard 41, 41a, 41b, 41c: PCIe ports 42: CPLD module 43: storage unit 431: PCIe default configuration information 44: BMC module 45:PCH module 451: BIOS unit 44s: Matching signal 200, 300, 400: PCIe devices C1, C2, C3: PCIe transmission lines

The first figure is a system block diagram showing a prior art server motherboard connected to a riser card through a PCIe port; The second figure shows the system block diagram of the circuit structure for automatically adjusting the PCIe channel configuration provided by the preferred embodiment of the present invention; The third figure is a schematic circuit diagram showing the circuit structure of the automatic adjustment PCIe channel configuration provided by the preferred embodiment of the present invention; and The fourth figure is a schematic plan view showing the circuit structure for automatically adjusting PCIe channel configuration provided by a preferred embodiment of the present invention.

100: Circuit structure for automatic adjustment of PCIe channel configuration

1,2,3:PCIe riser card

4: Motherboard

41:PCIe port

42: CPLD module

43: storage unit

431: PCIe default configuration information

44: BMC module

45:PCH module

451: BIOS unit

44s: Matching signal

200, 300, 400: PCIe devices

C1, C2, C3: PCIe transmission lines

Claims (6)

A circuit structure for automatically adjusting PCIe channel configuration, comprising: A plurality of PCIe riser cards (Riser), these PCIe riser cards include PCIe riser cards of at least two channel specifications, each PCIe riser card of channel specification has a PCIe specification identification code; and A motherboard, including: A plurality of PCIe connection ports are respectively electrically connected to the PCIe riser cards through a plurality of PCIe transmission lines, and each of the PCIe connection ports has an in-position pin; A CPLD module is electrically connected to the PCIe ports for reading the PCIe specification identification code corresponding to the PCIe riser cards passed through the PCIe ports, and reading the A plurality of presence signals (Present) transmitted by the presence pins of the connection port, and compare the current configuration information corresponding to these PCIe riser cards according to a PCIe specification comparison table; A storage unit stores a PCIe default configuration information; A BMC module, which is electrically connected to the CPLD module and the storage unit, is used to compare whether the current configuration information is consistent with the PCIe default configuration information, and compare the current configuration information with the PCIe default configuration When the information matches, send a matching signal; and A BIOS unit is electrically connected to the BMC module, and is used to adjust the configuration of the PCIe channel according to the current configuration information to start operation when receiving the matching signal. The circuit structure for automatically adjusting PCIe channel configuration as described in claim item 1, wherein, the BMC module parses out a total number of PCIe adapter cards and a total number of PCIe channel numbers from the current configuration information, and displays them on the PCIe adapter card When the total number and the total number of PCIe lanes respectively match with a preset total number of supported riser cards and a preset total number of supported channels, the matching matching signal is sent. The circuit structure for automatically adjusting PCIe channel configuration as described in claim 1, wherein the PCIe transmission lines are all Slimline SAS 8-Lane transmission lines. The circuit structure for automatically adjusting PCIe channel configuration as described in Claim 1, wherein the PCIe adapter cards use the ID codes sent by the three pins as the PCIe specification identification codes. A method for automatically adjusting PCIe channel configuration, comprising the following steps: (A) Use a plurality of PCIe transmission lines to electrically connect a plurality of PCIe riser cards (Risers) to a plurality of PCIe ports; (B) The PCIe riser cards respectively transmit a PCIe specification identification code to the PCIe connection ports through the PCIe transmission lines; (C) These PCIe ports transmit the PCIe specification identification code of these PCIe riser cards and a present signal (Present) provided by these PCIe ports to a CPLD module; (D) The CPLD module compares the PCIe specification identification codes of the PCIe riser cards with the presence signals of the PCIe ports according to a PCIe specification comparison table to generate a current configuration corresponding to the PCIe riser cards information, and transmit the current configuration information to a BMC module; and (E) The BMC module compares whether the current configuration information matches a PCIe default configuration information, and sends a matching signal to a BIOS unit when the current configuration information matches the PCIe default configuration information , so that the BIOS unit adjusts the configuration of the PCIe channel according to the current configuration information and starts to operate. The method for automatically adjusting PCIe channel configuration as described in claim item 5, wherein the PCIe riser cards transmit ID codes with three in-position pins after receiving the in-position signals transmitted by the PCIe devices .

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