CN112131163A - PCIE resource automatic splitting circuit and method - Google Patents

PCIE resource automatic splitting circuit and method Download PDF

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Publication number
CN112131163A
CN112131163A CN202010988126.XA CN202010988126A CN112131163A CN 112131163 A CN112131163 A CN 112131163A CN 202010988126 A CN202010988126 A CN 202010988126A CN 112131163 A CN112131163 A CN 112131163A
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slimline connector
slimline
connector
pins
pcie
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王世鹏
李岩
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Inspur Electronic Information Industry Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Information Transfer Systems (AREA)

Abstract

The application discloses a PCIE resource automatic splitting circuit and a method, comprising the following steps: the chip comprises a PEX8724 chip, a BMC, a first SLIMLINE connector and a second SLIMLINE connector, wherein the first SLIMLINE connector and the second SLIMLINE connector correspond to a PCIE X8 channel of the PEX8724 chip respectively; a configuration signal interface of the PEX8724 chip is connected with a BMC, and the BMC is connected with ID pins of the first SLIMLINE connector and the second SLIMLINE connector; the ID pins of the first SLIMLINE connector and the second SLIMLINE connector are used for being connected with the ID pins of the corresponding SLIMLINE connectors on the corresponding board cards respectively. This application sets up ID pin for SLIMLINE connector, and BMC can learn the required PCIE resource condition of current integrated circuit board according to the ID pin on the SLIMLINE connector of the integrated circuit board that inserts the mainboard to according to ID pin and the signal mapping relation that sets up in advance, set up the PCIE resource partition mode of PEX8724 chip, thereby accomplish automatic PCIE resource partition.

Description

PCIE resource automatic splitting circuit and method
Technical Field
The invention relates to the field, in particular to a PCIE resource automatic splitting circuit and a method.
Background
Broadcom is a leading wire and wireless communication semiconductor company in the world, the product of the Broadcom realizes the transmission of voice, data and multimedia to and in the home, office and mobile environments, the developed PCIE packet switch supports X8 PCIE to one X16 PCIE, two X8 pciees or 4X4PCIE lanes, the PCIE supports PCIE3.0 protocol, and the pin CFG0 is configured through the strap on the chip, and the CFG1 can configure the split mode of two downstream X8 pciees, thereby realizing the function of PCIE resource expansion. In the previous design, the split configuration of the PCIE resources is realized in a mode of pulling up and down resistors, but the pulling up and down resistors can only realize fixed PCIE splitting and cannot meet the requirements of diversification and flexibility in practical application, if various requirements are met, a plurality of PEX8724 packet switch chips need to be placed to meet the requirements, and the design and manufacturing cost is increased.
To this end, a more flexible method for automatically splitting PEX8724 PCIE resources is proposed herein.
Disclosure of Invention
In view of this, the present invention is directed to provide a circuit and a method for automatically splitting PCIE resources, which can more flexibly and automatically split the PCIE resources of PEX 8724. The specific scheme is as follows:
a PCIE resource automatic splitting circuit comprises: the system comprises a PEX8724 chip, a BMC, a first SLIMLINE connector and a second SLIMLINE connector, wherein the first SLIMLINE connector and the second SLIMLINE connector correspond to a PCIE X8 channel of the PEX8724 chip respectively;
the configuration signal interface of the PEX8724 chip is connected with the BMC, and the BMC is connected with the ID pins of the first SLIMLINE connector and the second SLIMLINE connector;
and the ID pins of the first SLIMLINE connector and the second SLIMLINE connector are respectively used for being connected with the ID pins of the corresponding SLIMLINE connectors on the corresponding board cards.
Optionally, the configuration signal interface of the PEX8724 chip is connected to the BMC through a level conversion chip.
Optionally, the system further includes a pull-up resistor connected to the ID pins of the first SLIMLINE connector and the second SLIMLINE connector, respectively.
Optionally, also include X16 Riser card;
the X16 Riser card comprises a third SLIMLINE connector and a fourth SLIMLINE connector, wherein ID pins of the third SLIMLINE connector and the fourth SLIMLINE connector are respectively connected with ID pins of the first SLIMLINE connector and the second SLIMLINE connector.
Optionally, the card also comprises an X8X8 Riser card;
the X8X8 Riser card includes a fifth SLIMLINE connector and a sixth SLIMLINE connector, whose ID pins are respectively connected with the ID pins of the first SLIMLINE connector and the second SLIMLINE connector.
Optionally, the NVME-based network component further comprises an NVME backplane;
the NVME backplane comprises a seventh SLIMLINE connector, ID pins of which are connected with the ID pins of the first SLIMLINE connector and the second SLIMLINE connector, respectively.
The invention also discloses a PCIE resource automatic splitting method, which is applied to the BMC and comprises the following steps:
receiving ID signals transmitted by ID pins of a first SLIMLINE connector and a second SLIMLINE connector;
assigning a value to a configuration signal interface of a PEX8724 chip according to a preset signal mapping relation and an ID signal, so that the PEX8724 chip splits PCIE resources according to the assignment of the configuration signal interface;
the signal mapping relationship is a mapping relationship between the ID signal and the assignment of the configuration signal interface which is established in advance.
In the present invention, a PCIE resource automatic splitting circuit includes: the chip comprises a PEX8724 chip, a BMC, a first SLIMLINE connector and a second SLIMLINE connector, wherein the first SLIMLINE connector and the second SLIMLINE connector correspond to a PCIE X8 channel of the PEX8724 chip respectively; a configuration signal interface of the PEX8724 chip is connected with a BMC, and the BMC is connected with ID pins of the first SLIMLINE connector and the second SLIMLINE connector; the ID pins of the first SLIMLINE connector and the second SLIMLINE connector are used for being connected with the ID pins of the corresponding SLIMLINE connectors on the corresponding board cards respectively.
According to the method, the ID pin is set for the SLIMLINE connector, the BMC can know the PCIE resource condition required by the current board card according to the ID pin on the SLIMLINE connector of the board card inserted into the mainboard, and the PCIE resource division mode of the PEX8724 chip is set according to the ID pin and the preset signal mapping relation, so that automatic PCIE resource division is completed.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a circuit diagram of an automatic PCIE resource splitting circuit disclosed in the embodiment of the present invention;
fig. 2 is a flowchart of a method for automatically splitting PCIE resources according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention discloses a PCIE resource automatic splitting circuit, which is shown in figure 1 and comprises: a PEX8724 chip, a BMC (Baseboard Management Controller), a first SLIMLINE connector and a second SLIMLINE connector corresponding to PCIE X8 channels of the PEX8724 chip, respectively;
a configuration signal interface of the PEX8724 chip is connected with a BMC, and the BMC is connected with ID pins of the first SLIMLINE connector and the second SLIMLINE connector;
the ID pins of the first SLIMLINE connector and the second SLIMLINE connector are used for being connected with the ID pins of the corresponding SLIMLINE connectors on the corresponding board cards respectively.
Specifically, a PCIE X8 channel of the PEX8724 chip is connected to the first SLIMLINE connector and the second SLIMLINE connector, so that the first SLIMLINE connector and the second SLIMLINE connector are connected to the corresponding board card, and a PCIE X8 channel is output.
Specifically, a first SLIMLINE connector and a second SLIMLINE connector set ID pins and are used for being connected with the ID pins on the SLIMLINE connectors of the corresponding board cards, so that the board cards can transmit the ID pins of the board cards to the BMC through the ID pins of the first SLIMLINE connector and the ID pins of the second SLIMLINE connector. At this time, the PCIE resource division requirement of the board card may be combined with the ID pin, and a corresponding signal mapping relationship is established, so that the BMC controls PCIE resource division of the PEX8724 chip through the configuration signal interface of the PEX8724 chip according to the ID pin.
Specifically, for example, first SLIMLINE connector SLIMLINE0 and second SLIMLINE connector SLIMLINE1 may set two ID pins, respectively: s0_ ID0, S0_ ID1 and S1_ ID0, S1_ ID 1.
Specifically, the corresponding board card may include an X16 Riser card, an X8X8 Riser card, and an NVME backplane; wherein,
specifically, the X16 Riser card may include a third SLIMLINE connector and a fourth SLIMLINE connector whose ID pins are connected to the ID pins of the first SLIMLINE connector and the second SLIMLINE connector, respectively.
For example, the third SLIMLINE connector SLIMLINE2 and the fourth SLIMLINE connector SIMLINE3 also set two ID pins: ID0 and ID 1.
Specifically, the X8X8 Riser card may include a fifth SLIMLINE connector and a sixth SLIMLINE connector whose ID pins are connected to the ID pins of the first SLIMLINE connector and the second SLIMLINE connector, respectively.
For example, the fifth SLIMLINE connector SLIMLINE4 and the sixth SLIMLINE connector SIMLINE5 also set two ID pins: ID0 and ID1
Specifically, the NVME backplane may include a seventh SLIMLINE connector whose ID pins are connected to the ID pins of the first SLIMLINE connector and the second SLIMLINE connector, respectively.
For example, the seventh SLIMLINE connector SLIMLINE6 also sets two ID pins: ID0 and ID 1.
Specifically, after the STBY is powered on the main board 1 where the PEX8724 is located, and the BMC ready, the BMC may determine which board is according to the states of S0_ ID1, S0_ ID0, S1_ ID1, and S1_ ID0, for example, S0_ ID1, S0_ ID0, S1_ ID1, and S1_ ID0 are all 00X 16 Riser cards, 01X 8X8 Riser cards, and 10 is an NVME backplane.
For example, the BMC assigns values to CFG1 and CFG0 according to states of S0_ ID1, S0_ ID0, S1_ ID1, and S1_ ID0, respectively, S0_ ID1, S0_ ID0 are 10, S1_ ID1, and S1_ ID0 are 10, identifies as NVME backplane, assigns CFG1 and CFG0 to ZZ, PEX8724 identifies that the states of the two CFGs are ZZ when powering on, and then the split mode of PCIE is four X4PCIE, so that the board card inserted is automatically identified, and PCIE division is automatically performed.
For another example, the BMC assigns values to CFG1 and CFG0 according to the states of S0_ ID1, S0_ ID0, S1_ ID1, and S1_ ID0, for example, if it is recognized that S0_ ID1 and S0_ ID0 are 01 and S1_ ID1 and S1_ ID0 are 10, then the CFG1 and CFG0 (configuration signals) are assigned as Z0 (where Z represents a high impedance state), and when power is turned on, PEX8724 recognizes that the states of the two CFGs are Z0, and then the split mode of PCIE is X8X4 PCIE.
Specifically, the correspondence between the ID pin and the configuration signal and the PCIE split mode can be referred to in table 1.
Watch 1
S0_ID1、S0_ID0 S1_ID1、S1_ID0 CFG1、CFG0 PCIE splitting mode
00 00 0Z X16
01 01 01 X8X8
01 10 Z0 X8X4X4
10 10 ZZ X4X4X4X4
Specifically, the specific PCIE split mode of PEX8724 can be referred to in the table PEX8724 PCIE split mode table.
Watch two
Figure BDA0002689934420000051
Specifically, according to the corresponding configuration of the PCIE split mode introduced in table one, after different board cards preset respective ID pins and count in the first SLIMLINE connector and the second SLIMLINE connector of the PEX8724 chip on the motherboard 1, the BMC reads the ID pins, and configures assignment of signal interfaces (CFG1, CFG0) according to the signal mapping relationship recorded in table one, thereby implementing multiple automatic PCIE divisions on the PEX8724 chip.
Therefore, in the embodiment of the present invention, the ID pin is set for the SLIMLINE connector, the BMC can know the PCIE resource condition required by the current board card according to the ID pin on the SLIMLINE connector of the board card inserted into the motherboard 1, and set the PCIE resource division mode of the PEX8724 chip according to the ID pin and the preset signal mapping relationship, thereby completing automatic PCIE resource division.
Further, since the PEX8724 uses the 1.8V level and the BMC uses the P3V3_ STBY level, the configuration signal interface of the PEX8724 chip is connected to the BMC after level conversion by the level conversion chip, so that the configuration signal interface of the PEX8724 chip is compatible with the BMC level.
Specifically, the ID pins of the first SLIMLINE connector and the second SLIMLINE connector are further connected with a pull-up resistor, which includes external resistors R0, R1, R2, and R3, and is pulled up to the P3V3_ STBY power supply, where the resistors R0, R1, R2, and R3 may be set to 4.7K Ω, that is, the main board terminal, that is, the PEX8724 chip terminal, and default S0_ ID1, S0_ ID0, S1_ ID1, and S1_ ID0 are logic 11.
Specifically, the X16 Riser card, with the additional resistors R4, R5, R6 and R7 respectively pulled down to GND, here the resistors R4, R5, R6 and R7 can be set to 0 Ω, i.e. the default IDs 1 and ID0 of the X16 Riser card end are logic 00, and correspond to the main board ends S0_ ID1, S0_ ID0 or S1_ ID1 and S1_ ID0 through cable connection.
Specifically, the X8X8 Riser card, with the additional resistors R8 and R10 respectively pulled up to P3V3_ STBY and the resistors R9 and R11 pulled down to GND, may have resistors R8 and R10 set to 4.7K Ω and R9 and R11 set to 0 Ω, i.e. the default ID1 and ID0 of the X8X8 Riser card are logic 01, and is connected to the main board terminals S0_ ID1, S0_ ID0 or S1_ ID1 and S1_ ID0 through cables.
Specifically, the NVME backplane is respectively pulled down to GND by an additional resistor R12 and pulled up to P3V3_ STBY by a resistor R13, where the resistor R12 may be set to 0 Ω, and the resistor R13 may be set to 4.7K Ω, that is, the default IDs 1 and ID0 of the NVME backplane ends are logic 10, and are connected to the motherboard ends S0_ ID1, S0_ ID0, or S1_ ID1, S1_ ID0 through cables.
In addition, the level conversion chip in the figure can use PAC9617, can also use MOS tube or triode as level shift, and can also be connected to CPLD to use CPLD as level conversion.
Correspondingly, the embodiment of the present invention further discloses an automatic splitting method of PCIE resources, as shown in fig. 2, which is applied to the BMC described above, and includes:
s11: receiving ID signals transmitted by ID pins of a first SLIMLINE connector and a second SLIMLINE connector;
s12: assigning a value to a configuration signal interface of the PEX8724 chip according to a preset signal mapping relation and an ID signal, so that the PEX8724 chip splits PCIE resources according to the assignment of the configuration signal interface;
the signal mapping relationship is a mapping relationship between the pre-established ID signal and the assignment of the configuration signal interface.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The technical content provided by the present invention is described in detail above, and the principle and the implementation of the present invention are explained in this document by applying specific examples, and the above description of the examples is only used to help understanding the method of the present invention and the core idea thereof; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims (7)

1. A PCIE resource automatic splitting circuit is characterized by comprising: the system comprises a PEX8724 chip, a BMC, a first SLIMLINE connector and a second SLIMLINE connector, wherein the first SLIMLINE connector and the second SLIMLINE connector correspond to a PCIE X8 channel of the PEX8724 chip respectively;
the configuration signal interface of the PEX8724 chip is connected with the BMC, and the BMC is connected with the ID pins of the first SLIMLINE connector and the second SLIMLINE connector;
and the ID pins of the first SLIMLINE connector and the second SLIMLINE connector are respectively used for being connected with the ID pins of the corresponding SLIMLINE connectors on the corresponding board cards.
2. The automatic splitting circuit of PCIE resources of claim 1, wherein a configuration signal interface of the PEX8724 chip is connected to the BMC through a level shifting chip.
3. The PCIE resource automatic splitting circuit of claim 2, further comprising pull-up resistors connected to ID pins of the first SLIMLINE connector and the second SLIMLINE connector, respectively.
4. The PCIE resource automatic splitting circuit of any one of claims 1 to 3, further comprising an X16 Riser card;
the X16 Riser card comprises a third SLIMLINE connector and a fourth SLIMLINE connector, wherein ID pins of the third SLIMLINE connector and the fourth SLIMLINE connector are respectively connected with ID pins of the first SLIMLINE connector and the second SLIMLINE connector.
5. The PCIE resource automatic splitting circuit of any one of claims 1 to 3, further comprising an X8X8 Riser card;
the X8X8 Riser card includes a fifth SLIMLINE connector and a sixth SLIMLINE connector, whose ID pins are respectively connected with the ID pins of the first SLIMLINE connector and the second SLIMLINE connector.
6. The PCIE resource automatic splitting circuit of any one of claims 1 to 3, further comprising an NVME backplane;
the NVME backplane comprises a seventh SLIMLINE connector, ID pins of which are connected with the ID pins of the first SLIMLINE connector and the second SLIMLINE connector, respectively.
7. An automatic splitting method of PCIE resources, applied to the BMC according to any one of claims 1 to 6, includes:
receiving ID signals transmitted by ID pins of a first SLIMLINE connector and a second SLIMLINE connector;
assigning a value to a configuration signal interface of a PEX8724 chip according to a preset signal mapping relation and an ID signal, so that the PEX8724 chip splits PCIE resources according to the assignment of the configuration signal interface;
the signal mapping relationship is a mapping relationship between the ID signal and the assignment of the configuration signal interface which is established in advance.
CN202010988126.XA 2020-09-18 2020-09-18 PCIE resource automatic splitting circuit and method Withdrawn CN112131163A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114911740A (en) * 2022-06-02 2022-08-16 中国长城科技集团股份有限公司 PCIe splitting method and device, electronic equipment and readable storage medium
TWI793548B (en) * 2021-03-16 2023-02-21 英業達股份有限公司 Circuit structure and method for automatically adjusting pcie channel configuration

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CN106959932A (en) * 2017-04-14 2017-07-18 广东浪潮大数据研究有限公司 A kind of Riser card methods for designing of automatic switchover PCIe signals
CN108763124A (en) * 2018-05-23 2018-11-06 郑州云海信息技术有限公司 A kind of PCIE Riser cards
CN110162496A (en) * 2019-04-15 2019-08-23 深圳市同泰怡信息技术有限公司 A method of realizing that the port PCIE automatically configures based on central processing unit

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Publication number Priority date Publication date Assignee Title
US20090222609A1 (en) * 2008-02-29 2009-09-03 Inventec Corporation Apparatus for automatically regulating system id of motherboard of server and server having the same
CN106959932A (en) * 2017-04-14 2017-07-18 广东浪潮大数据研究有限公司 A kind of Riser card methods for designing of automatic switchover PCIe signals
CN108763124A (en) * 2018-05-23 2018-11-06 郑州云海信息技术有限公司 A kind of PCIE Riser cards
CN110162496A (en) * 2019-04-15 2019-08-23 深圳市同泰怡信息技术有限公司 A method of realizing that the port PCIE automatically configures based on central processing unit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI793548B (en) * 2021-03-16 2023-02-21 英業達股份有限公司 Circuit structure and method for automatically adjusting pcie channel configuration
CN114911740A (en) * 2022-06-02 2022-08-16 中国长城科技集团股份有限公司 PCIe splitting method and device, electronic equipment and readable storage medium
CN114911740B (en) * 2022-06-02 2024-06-28 中国长城科技集团股份有限公司 PCIe splitting method and device, electronic equipment and readable storage medium

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Application publication date: 20201225