TWI792807B - Time-to-digital converting apparatus and method thereof - Google Patents

Abstract

A time-to-digital converting apparatus and a method thereof are provided. A clock generation circuit generates n clock signals having different phases. A time-to-digital converter starts to count rising or falling edges of the n clock signals after a predetermined period of time has elapsed since the clock generating circuit starts to generate the n clock signals, so as to generate a digital signal.

Description

Time-to-digital conversion device and method for time-to-digital conversion thereof

The present invention relates to a conversion device, and in particular to a time-to-digital conversion device and a time-to-digital conversion method thereof.

With the development of integrated circuits, converting the sensing information obtained by sensors into digital codes can be used more widely. Wherein, for the time measurement system, the time-to-digital converter can express the sensing information by the time width, and count the time width through the oscillator, so as to convert the sensing information into a digital output.

In the prior art, the time-to-digital converter generally converts the time information into a digital signal by counting the clock signal provided by the oscillator. However, since the pulse width of the clock signal provided by the oscillator is not stable at the initial stage of startup, this will The digital signal cannot correctly reflect the time information.

The invention provides a time-to-digital conversion device and a time-to-digital conversion method thereof, which can ensure that the digital signal output by the time-to-digital conversion device provides correct time information.

The time-to-digital conversion device of the present invention includes a clock generation circuit and a time-to-digital converter. The clock generating circuit generates n clock signals with different phases, where n is a positive integer. The time-to-digital converter is coupled to the clock generating circuit, and starts to count the rising or falling edges of the n clock signals after a preset period of time after the clock generating circuit starts generating n clock signals to generate digital signals.

The present invention also provides a time-to-digital conversion method of the time-to-digital conversion device, which includes the following steps. The enabling clock generating circuit generates n clock signals, wherein n is a positive integer. After a predetermined period of time has elapsed since the clock generating circuit starts to generate n clock signals, start counting the rising or falling edges of the n clock signals to generate digital signals.

Based on the above, the time-to-digital converter of the embodiment of the present invention can start counting the rising or falling edges of the clock signal to generate a digital signal after a predetermined period of time has elapsed since the clock generating circuit starts to generate the clock signal. Waiting for the clock signal output by the clock generating circuit to be stable in this way, and then counting the rising edge or falling edge, it can ensure that the correctness of the digital signal generated by the time-to-digital conversion device will not be affected by the unstable clock signal of the clock generating circuit. affected.

In order to make the content of the present invention more comprehensible, the following specific examples are given as examples in which the present invention can indeed be implemented. In addition, wherever possible, elements/components/steps using the same reference numerals in the drawings and embodiments represent the same or similar parts.

Please refer to FIG. 1 below. FIG. 1 is a schematic block diagram of a time-to-digital conversion device according to an embodiment of the present invention. The time-to-digital conversion device includes a clock generation circuit 102 and a time-to-digital converter 104 , and the clock generation circuit 102 is coupled to the time-to-digital converter 104 . The clock generating circuit 102 can generate n clock signals CK0 ˜CKn−1 with different phases, wherein n is a positive integer, and the clock generating circuit 102 can be implemented by, for example, a ring oscillator, but not limited thereto. The time-to-digital converter 104 can start counting the rising or falling edges of the clock signals CK0-CKn-1 after a predetermined period of time has elapsed since the clock generating circuit 102 starts to generate the clock signals CK0-CKn-1 to generate Digital signal D1. Waiting for the clock signals CK0~CKn-1 output by the clock generating circuit 102 to stabilize in this way, and then counting the rising or falling edges of the clock signals CK0~CKn-1, it can ensure that the digital signal D1 generated by the time-to-digital conversion device The correctness of is not affected by the instability of the clock signals CK0 - CKn-1 of the clock generating circuit 102 .

For example, as shown in FIG. 2 , the clock generating circuit 102 is enabled by the received enable signal EN1 and starts to generate the clock signals CK0 - CK3 . The time-to-digital converter 104 can start counting the rising edges of the clock signals CK0 - CK3 according to the received enable signal EN2 after a preset time T1 has elapsed since the clock generating circuit 102 starts to generate the clock signal. As shown in FIG. 2 , at the initial stage when the clock generator circuit 102 generates the clock signals CK0 ~ CK3 , the clock signals CK0 ~ CK3 are not yet stable and have a relatively large pulse width. The signals CK0 - CK3 become stable and have a small and fixed pulse width, so counting the clock signals CK0 - CK3 at this time can accurately reflect the time information.

The time-to-digital converter 104 can determine the signal value of the output digital signal D1 according to the received stop signal SP1, for example. For example, in FIG. 2, the stop signal SP1 is a pulse signal, and the time-to-digital converter 104 can determine the signal value of the output digital signal D1 according to the rising edge of the stop signal SP1 (in the embodiment of FIG. 2, the rising edge of the stop signal SP1 The corresponding signal value is 8).

It should be noted that the number of clock signals generated by the clock generating circuit 102 is not limited to the embodiment shown in FIG. 2 . In other embodiments, the clock generating circuit 102 can also generate more or fewer clock signals. Signal. In addition, the preset time T1 can be determined, for example, according to the time required for the change of the pulse width of the clock signal to be smaller than the preset value within a period of observation time, that is, it is determined by the stabilization of the clock signal generated by the clock generating circuit 102 The time required is determined. In other embodiments, the time-to-digital converter 104 can also count according to the falling edges of the clock signals CK0-CK3 instead of the rising edges. Similarly, the time-to-digital converter 104 can also count according to the falling edges of the stop signal SP1, for example. To determine the signal value of the output digital signal D1.

The enable signals EN1 , EN2 and the stop signal SP1 can be provided, for example, by a control circuit (not shown) coupled to the clock generating circuit 102 and the time-to-digital converter 104 . In other embodiments, it is also possible to use the control circuit to detect whether the change in the pulse width of the clock signal generated by the clock generating circuit 102 is less than a preset value in the latest observation period, and determine whether the clock signal When the pulse width of the signal changes less than a preset value, the enable signal EN2 is generated to enable the time-to-digital converter 104 to start counting the rising edge or falling edge of the stop signal SP1, so as to ensure that the time-to-digital converter 104 can generate the correct digital signal D1 .

The time-to-digital conversion device may, for example, be applied to a distance sensing device, such as a time-of-flight distance sensor or an ultrasonic sensor, but is not limited thereto. For example, the time point when the time-to-digital converter 104 starts counting the rising edge of the stop signal SP1 according to the enable signal EN2 may be the time point when the time-of-flight distance sensor emits light beams or the time point when the ultrasonic sensor emits sound waves, and The time point when the stop signal SP1 generates a rising edge can be, for example, the time point when the time-of-flight distance sensor receives the reflected light beam or the time point when the ultrasonic sensor receives the reflected sound wave, so the digital signal D1 generated by the time-to-digital conversion device Obtaining accurate time information can also make the calculated distance sensing results correct.

In addition, in some embodiments, the signal value of the digital signal D1 can also be determined by, for example, two count values. For example, as shown in FIG. 3, different from the embodiment in FIG. 2, in the embodiment in FIG. Count value 2) in FIG. 3, and determine a second count value (such as count value 8 in FIG. 3) according to the rising edge of the received stop signal SP1, and generate a digital signal D1 according to the first count value and the second count value. For example, the difference (6) obtained by subtracting the first count value (2) from the second count value (8) can be used as a digital signal D1, which represents the rise from the rising edge of the start signal ST1 to the rising edge of the stop signal SP1 During the period of appearance, the time of 6 accumulated count values has elapsed.

The digital signal D1 can be sent to the subsequent signal processing circuit for application processing of the signal. For example, when the time-to-digital conversion device is applied to a distance sensing device, such as a time-of-flight distance sensor or an ultrasonic sensor, the signal processing circuit can perform application processing related to distance estimation. The time when the rising edge of the start signal ST1 occurs can be the time point when the time-of-flight distance sensor emits light beams or the time point when the ultrasonic sensor emits sound waves, and the time point when the stop signal SP1 generates a rising edge can be, for example, the time-of-flight distance The time point when the sensor receives the reflected light beam or the time point when the ultrasonic sensor receives the reflected sound wave. In addition, the time-to-digital converter 104 can also count according to the falling edges of the counting clock signals CK0 - CK3 , and determine the first count value and the second count value according to the falling edges of the start signal ST1 and the stop signal SP1 .

FIG. 4 is a flowchart of a time-to-digital conversion method of the time-to-digital conversion device according to an embodiment of the present invention. It can be known from the above embodiments that the time-to-digital conversion method of the time-to-digital conversion device may at least include the following steps. First, enable the clock generating circuit to generate n clock signals (step S402), where n is a positive integer, for example, a first enable signal can be provided to the clock generating circuit to enable the clock generating circuit to generate n clock signals . Then, after a predetermined period of time has elapsed since the clock generating circuit starts to generate n clock signals, start counting the rising or falling edges of the n clock signals to generate digital signals (step S404), for example, according to the second The enabling signal starts to count the rising or falling edges of the n clock signals after the preset time elapses since the clock generating circuit starts to generate the n clock signals, so as to generate the digital signal. The preset time can be determined, for example, according to the time required for the change of the pulse width of the n clock signals to be smaller than the preset value within a period of observation. Waiting for the clock signal output by the clock generating circuit to be stable in this way, and then counting the rising edge or falling edge, it can ensure that the correctness of the digital signal generated by the time-to-digital conversion device will not be affected by the unstable clock signal of the clock generating circuit. affected.

FIG. 5 is a flowchart of a time-to-digital conversion method of a time-to-digital conversion device according to another embodiment of the present invention. Compared with the embodiment in FIG. 4 , the time-to-digital conversion method of this embodiment is to generate a digital signal representing time information based on two count values. As shown in Figure 5, the corresponding first count value and second count value can be determined according to the time of the start signal and stop signal received in sequence (step S502), and then according to the first count value and the second count value Generate a digital signal (step S504 ). For example, a digital signal can be generated according to the difference between the first count value and the second count value. The start signal and the stop signal may be, for example, pulse signals, and the first count value and the second count value may be determined according to the count values corresponding to the rising or falling edge generation times of the start signal and the stop signal.

To sum up, the time-to-digital converter of the embodiment of the present invention can start counting the rising or falling edges of the clock signal to generate a digital signal after a predetermined period of time has elapsed since the clock generating circuit starts to generate the clock signal. Waiting for the clock signal output by the clock generating circuit to be stable in this way, and then counting the rising edge or falling edge, it can ensure that the correctness of the digital signal generated by the time-to-digital conversion device will not be affected by the unstable clock signal of the clock generating circuit. affected.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

102: Clock generator circuit 104: Time to digital converter CK0~CKn-1: clock signal D1: digital signal EN1, EN2: enable signal SP1: stop signal ST1: start signal T1: preset time S402~S405, S502~S504: the steps of the time digital conversion method

FIG. 1 is a schematic block diagram of a time-to-digital conversion device according to an embodiment of the present invention. FIG. 2 is a schematic diagram of an operation sequence of a time-to-digital conversion device according to an embodiment of the present invention. FIG. 3 is a schematic diagram of an operation sequence of a time-to-digital conversion device according to another embodiment of the present invention. FIG. 4 is a flowchart of a time-to-digital conversion method of the time-to-digital conversion device according to an embodiment of the present invention. FIG. 5 is a flowchart of a time-to-digital conversion method of a time-to-digital conversion device according to another embodiment of the present invention.

102: Clock generator circuit

104: Time to digital converter

CK0~CKn-1: clock signal

D1: digital signal

EN1, EN2: enable signal

SP1: stop signal

Claims (12)

A time-to-digital conversion device, comprising: A clock generating circuit that generates n clock signals with different phases, where n is a positive integer; and A time-to-digital converter, coupled to the clock generating circuit, starts counting the rising or falling edges of the n clock signals after a predetermined period of time has elapsed since the clock generating circuit starts generating the n clock signals , to generate a digital signal. The time-to-digital conversion device as described in claim 1, wherein the time-to-digital converter determines a first count value and a second count value according to a start signal and a stop signal, and determines a first count value and a second count value according to the first count value and the second The count value generates the digital signal. The time-to-digital conversion device as claimed in claim 2, wherein the time-to-digital converter generates the digital signal according to the difference between the first count value and the second count value. The time-to-digital conversion device as described in claim 2, wherein the start signal and the stop signal are pulse signals, and the time-to-digital converter determines the correspondence according to the generation time of the rising edge or falling edge of the start signal and the stop signal The first count value and the second count value of . The time-to-digital conversion device as claimed in claim 1, wherein the preset time is determined according to the time required for the change of the pulse width of the n clock signals to be less than a preset value within a period of observation time. The time-to-digital conversion device as described in claim 1, wherein the clock generation circuit generates the n clock signals according to a first enable signal, and the time-to-digital converter generates the n clock signals according to a second enable signal After the preset time has elapsed since the circuit starts to generate the n clock signals, it starts counting the rising or falling edges of the n clock signals to generate the digital signal. A time-to-digital conversion method of a time-to-digital conversion device, comprising: enabling a clock generating circuit to generate n clock signals, where n is a positive integer; and After a predetermined period of time has elapsed since the clock generating circuit starts to generate the n clock signals, it starts counting the rising or falling edges of the n clock signals to generate a digital signal. The time-to-digital conversion method of the time-to-digital conversion device as described in claim item 7, comprising: determining a corresponding first count value and a second count value according to the timing of a start signal and a stop signal received sequentially; and The digital signal is generated according to the first count value and the second count value. The time-to-digital conversion method of the time-to-digital conversion device as described in claim item 8, comprising: The digital signal is generated according to the difference between the first count value and the second count value. The time-to-digital conversion method of the time-to-digital conversion device according to claim 8, wherein the start signal and the stop signal are pulse signals, and the first count value and the second count value are based on the start signal and the stop signal The count value corresponding to the generation time of the rising edge or falling edge of the signal is determined. The time-to-digital conversion method of the time-to-digital conversion device as described in claim item 8, wherein the preset time is the time required for the change of the pulse width of the n clock signals to be less than a preset value within a period of observation time Decide. The time-to-digital conversion method of the time-to-digital conversion device as described in claim item 7, comprising: providing a first enabling signal to enable the clock generating circuit to generate n clock signals; and After the preset time elapses after the clock generation circuit starts to generate the n clock signals according to a second enabling signal, start counting the rising or falling edges of the n clock signals to generate the digital signal.

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