TWM625317U - Time-to-digital converting apparatus - Google Patents

Time-to-digital converting apparatus Download PDF

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TWM625317U
TWM625317U TW110215510U TW110215510U TWM625317U TW M625317 U TWM625317 U TW M625317U TW 110215510 U TW110215510 U TW 110215510U TW 110215510 U TW110215510 U TW 110215510U TW M625317 U TWM625317 U TW M625317U
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time
signal
clock
digital
count value
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TW110215510U
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程韋盛
白順尹
孫伯偉
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神盾股份有限公司
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    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom

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  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Measurement Of Unknown Time Intervals (AREA)
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Abstract

A time-to-digital converting apparatus is provided. A clock generation circuit generates n clock signals having different phases. A time-to-digital converter starts to count rising or falling edges of the n clock signals after a predetermined period of time has elapsed since the clock generating circuit starts to generate the n clock signals, so as to generate a digital signal to a signal processing circuit.

Description

時間數位轉換裝置time-to-digital conversion device

本新型創作是有關於一種轉換裝置，且特別是有關於一種時間數位轉換裝置。The present invention relates to a conversion device, and in particular, to a time-to-digital conversion device.

隨著積體電路的發展，將感測器所獲得的感測資訊轉換為數位碼的形式，可以實現更加廣泛的運用。其中，對於時間量測系統而言，時間數位轉換器可藉由時間寬度來表示感測資訊，並透過振盪器對時間寬度進行計數，從而將感測資訊轉換為數位形式的輸出。With the development of integrated circuits, the sensing information obtained by the sensor is converted into the form of digital code, which can be widely used. Among them, for the time measurement system, the time-to-digital converter can represent the sensing information by the time width, and count the time width through the oscillator, so as to convert the sensing information into digital output.

在現有技術中，時間數位轉換器一般透過計數振盪器提供的時脈信號來將時間信息轉換為數位信號，然由於振盪器啟動初期所提供的時脈信號的脈波寬度並不穩定，如此將使數位信號無法正確地反映出時間信息。In the prior art, the time-to-digital converter generally converts time information into digital signals by counting the clock signal provided by the oscillator. However, since the pulse width of the clock signal provided by the oscillator is not stable at the initial stage of the oscillator, so the So that the digital signal cannot correctly reflect the time information.

本新型創作提供一種時間數位轉換裝置，可確保時間數位轉換裝置輸出的數位信號提供正確的時間信息。The novel creation provides a time-to-digital conversion device, which can ensure that the digital signal output by the time-to-digital conversion device provides correct time information.

本新型創作的時間數位轉換裝置包括時脈產生電路以及時間數位轉換器。時脈產生電路產生具有不同相位的n個時脈信號，其中n為正整數。時間數位轉換器耦接時脈產生電路，於時脈產生電路開始產生n個時脈信號起經過一段預設時間後，開始計數n個時脈信號的上升緣或下降緣，以產生數位信號給信號處理電路。The time-to-digital conversion device of the novel creation includes a clock generating circuit and a time-to-digital converter. The clock generating circuit generates n clock signals with different phases, wherein n is a positive integer. The time-to-digital converter is coupled to the clock generation circuit, and starts to count the rising edges or falling edges of the n clock signals after the clock generation circuit starts to generate the n clock signals, so as to generate a digital signal to the clock signal. signal processing circuit.

基于上述，本新型創作實施例的時間數位轉換器可於時脈產生電路開始產生時脈信號起經過一段預設時間後，開始計數時脈信號的上升緣或下降緣，以產生數位信號。如此等待時脈產生電路輸出的時脈信號穩定後，再進行上升緣或下降緣的計數，可確保時間數位轉換裝置產生的數位信號的正確性不因時脈產生電路的時脈信號不穩定而受到影響。Based on the above, the time-to-digital converter of the present invention can start counting the rising edge or falling edge of the clock signal to generate the digital signal after a predetermined period of time has elapsed since the clock generating circuit started to generate the clock signal. Waiting for the clock signal output by the clock generating circuit to stabilize in this way, and then counting the rising edge or falling edge, can ensure that the correctness of the digital signal generated by the time-to-digital conversion device is not affected by the instability of the clock signal of the clock generating circuit. affected.

為了使本新型創作之內容可以被更容易明瞭，以下特舉實施例做為本新型創作確實能夠據以實施的範例。另外，凡可能之處，在圖式及實施方式中使用相同標號的元件/構件/步驟，係代表相同或類似部件。In order to make the content of the novel creation easier to understand, the following specific embodiments are used as examples by which the novel creation can indeed be implemented. Additionally, where possible, elements/components/steps using the same reference numerals in the drawings and embodiments represent the same or similar parts.

以下請參照圖1，圖1是依照本新型創作一實施例所繪示的時間數位轉換裝置的方塊示意圖。時間數位轉換裝置包括時脈產生電路102以及時間數位轉換器104，時脈產生電路102耦接時間數位轉換器104。時脈產生電路102可產生具有不同相位的n個時脈信號CK0~CKn-1，其中n為正整數，時脈產生電路102可例如以環型振盪器來實施，然不以此為限。時間數位轉換器104則可於時脈產生電路102開始產生時脈信號CK0~CKn-1起經過一段預設時間後，開始計數時脈信號CK0~CKn-1的上升緣或下降緣，以產生數位信號D1。如此等待時脈產生電路102輸出的時脈信號CK0~CKn-1穩定後，再進行時脈信號CK0~CKn-1的上升緣或下降緣的計數，可確保時間數位轉換裝置產生的數位信號D1的正確性不因時脈產生電路102的時脈信號CK0~CKn-1不穩定而受到影響。Please refer to FIG. 1 below. FIG. 1 is a schematic block diagram of a time-to-digital conversion device according to an embodiment of the present invention. The time-to-digital conversion device includes a clock generating circuit 102 and a time-to-digital converter 104 . The clock generating circuit 102 is coupled to the time-to-digital converter 104 . The clock generating circuit 102 can generate n clock signals CK0 ˜CKn-1 with different phases, where n is a positive integer. The clock generating circuit 102 can be implemented by, for example, a ring oscillator, but not limited thereto. The time-to-digital converter 104 can start to count the rising edge or the falling edge of the clock signals CK0 ˜CKn-1 after a predetermined period of time after the clock generating circuit 102 starts to generate the clock signals CK0 ˜CKn-1 to generate digital signal D1. After waiting for the clock signals CK0 to CKn-1 output by the clock generation circuit 102 to be stable in this way, the rising edge or the falling edge of the clock signals CK0 to CKn-1 is counted to ensure the digital signal D1 generated by the time-to-digital conversion device. The accuracy is not affected by the instability of the clock signals CK0 to CKn-1 of the clock generation circuit 102 .

舉例來說，如圖2所示，時脈產生電路102被所接收到的致能信號EN1致能，而開始產生時脈信號CK0~CK3。時間數位轉換器104可在時脈產生電路102開始產生時脈信號起經過一段預設時間T1後，依據接收到的致能信號EN2開始計數時脈信號CK0~CK3的上升緣。如圖2所示，在時脈產生電路102產生時脈信號CK0~CK3的初期，時脈信號CK0~CK3尚未穩定而具有較大的脈波寬度，而在經過預設時間T1後，時脈信號CK0~CK3變得穩定而具有較小且固定的脈波寬度，因此此時對時脈信號CK0~CK3進行計數可較正確地反映出時間信息。For example, as shown in FIG. 2 , the clock generation circuit 102 is enabled by the received enable signal EN1 and starts to generate clock signals CK0 - CK3 . The time-to-digital converter 104 can start counting the rising edges of the clock signals CK0 ˜ CK3 according to the received enable signal EN2 after a predetermined period of time T1 after the clock generation circuit 102 starts to generate the clock signal. As shown in FIG. 2 , at the initial stage of generating the clock signals CK0 ˜ CK3 by the clock generating circuit 102 , the clock signals CK0 ˜ CK3 are not stable yet and have larger pulse widths, and after the preset time T1 , the clock signals CK0 ˜CK3 The signals CK0 ˜ CK3 become stable and have a small and fixed pulse width. Therefore, counting the clock signals CK0 ˜ CK3 at this time can reflect the time information more accurately.

時間數位轉換器104可例如依據接收到的停止信號SP1來決定輸出的數位信號D1的信號值。例如在圖2中，停止信號SP1為脈衝信號，時間數位轉換器104可依據停止信號SP1的上升緣來決定輸出的數位信號D1的信號值(在圖2實施例中，停止信號SP1的上升緣所對應的信號值為8)。The time-to-digital converter 104 may, for example, determine the signal value of the output digital signal D1 according to the received stop signal SP1. For example, in FIG. 2 , the stop signal SP1 is a pulse signal, and the time-to-digital converter 104 can determine the signal value of the output digital signal D1 according to the rising edge of the stop signal SP1 (in the embodiment of FIG. 2 , the rising edge of the stop signal SP1 The corresponding signal value is 8).

值得注意的是，時脈產生電路102所產生的時脈信號的數量並不以圖2實施例為限，在其它實施例中，時脈產生電路102也可產生更多或更少的時脈信號。此外，預設時間T1可例如為依據時脈信號的脈波寬度的變化在一段觀察時間內小於預設值所需的時間決定，亦即由時脈產生電路102所產生的時脈信號穩定所需的時間決定。在其它實施例中，時間數位轉換器104也可例如依據時脈信號CK0~CK3的下降緣進行計數而非依據上升緣，類似地，時間數位轉換器104也可例如依據停止信號SP1的下降緣來決定輸出的數位信號D1的信號值。It should be noted that the number of clock signals generated by the clock generation circuit 102 is not limited to the embodiment shown in FIG. 2 , and in other embodiments, the clock generation circuit 102 can also generate more or less clock signals Signal. In addition, the preset time T1 can be determined, for example, according to the time required for the variation of the pulse width of the clock signal to be less than the preset value within a period of observation time, that is, the time required for the stability of the clock signal generated by the clock generating circuit 102 required time to decide. In other embodiments, the time-to-digital converter 104 can also count according to the falling edges of the clock signals CK0-CK3 instead of the rising edges. Similarly, the time-to-digital converter 104 can also count according to the falling edges of the stop signal SP1. to determine the signal value of the output digital signal D1.

致能信號EN1、EN2以及停止信號SP1可例如由與時脈產生電路102以及時間數位轉換器104耦接的控制電路(未繪示)提供。在其它實施例中，也可藉由控制電路偵測時脈產生電路102所產生的時脈信號的脈波寬度的變化在最近的一段觀察時間內是否小於預設值，並在判斷出時脈信號的脈波寬度的變化小於預設值時產生致能信號EN2致能時間數位轉換器104開始計數停止信號SP1的上升緣或下降緣，以確保時間數位轉換器104可產生正確的數位信號D1。The enable signals EN1 , EN2 and the stop signal SP1 can be provided by, for example, a control circuit (not shown) coupled to the clock generation circuit 102 and the time-to-digital converter 104 . In other embodiments, the control circuit can also detect whether the change in the pulse width of the clock signal generated by the clock generating circuit 102 is smaller than a preset value during the most recent observation period, and determine whether the clock pulse is When the change of the pulse width of the signal is less than the preset value, the enable signal EN2 is generated to enable the TDC 104 to start counting the rising edge or the falling edge of the stop signal SP1 to ensure that the TDC 104 can generate the correct digital signal D1 .

時間數位轉換裝置可例如應用於距離感測裝置，例如飛行時間距離感測器或超聲波感測器，然不以此為限。舉例來說，時間數位轉換器104依據致能信號EN2開始計數停止信號SP1的上升緣的時間點可為飛行時間距離感測器發射光束的時間點或超聲波感測器發射聲波的時間點，而停止信號SP1產生上升緣的時間點可例如為飛行時間距離感測器接收到反射光束的時間點或超聲波感測器接收到反射聲波的時間點，如此藉由時間數位轉換裝置產生的數位信號D1獲得精確的時間信息，也可使計算出的距離感測結果正確。The time-to-digital conversion device can be applied to, for example, a distance sensing device, such as a time-of-flight distance sensor or an ultrasonic sensor, but is not limited thereto. For example, the time point when the time-to-digital converter 104 starts counting the rising edge of the stop signal SP1 according to the enable signal EN2 can be the time point when the time-of-flight distance sensor emits a light beam or the time point when the ultrasonic sensor emits a sound wave, and The time point when the stop signal SP1 generates a rising edge can be, for example, the time point when the time-of-flight distance sensor receives the reflected light beam or the time point when the ultrasonic sensor receives the reflected sound wave, so that the digital signal D1 is generated by the time-to-digital conversion device. Obtaining accurate time information can also make the calculated distance sensing results correct.

此外，在部份實施例中，數位信號D1的信號值也可例如由兩個計數值來決定。舉例來說，如圖3所示，與圖2實施例不同的是，在圖3實施例中，時間數位轉換器104可依據接收的起始信號ST1的上升緣來決定第一計數值(例如圖3的計數值2)，並依據接收的停止信號SP1的上升緣決定第二計數值(例如圖3的計數值8)，並依據第一計數值與第二計數值來產生數位信號D1。例如可將第二計數值(8)減去第一計數值(2)所得到的差值(6)作為數位信號D1，其代表從起始信號ST1的上升緣出現至停止信號SP1的上升緣出現的期間，經過了6次累積計數值的時間。In addition, in some embodiments, the signal value of the digital signal D1 can also be determined by, for example, two count values. For example, as shown in FIG. 3 , different from the embodiment of FIG. 2 , in the embodiment of FIG. 3 , the time-to-digital converter 104 can determine the first count value according to the rising edge of the received start signal ST1 (eg, Count value 2 in FIG. 3 ), and determine the second count value (eg, count value 8 in FIG. 3 ) according to the rising edge of the received stop signal SP1 , and generate the digital signal D1 according to the first count value and the second count value. For example, the difference (6) obtained by subtracting the first count value (2) from the second count value (8) can be used as the digital signal D1, which represents the occurrence from the rising edge of the start signal ST1 to the rising edge of the stop signal SP1 During the period of occurrence, the time for the accumulated count value has elapsed 6 times.

數位信號D1可被傳送給後級的信號處理電路進行信號的應用處理。舉例來說，當時間數位轉換裝置應用於距離感測裝置時，例如飛行時間距離感測器或超聲波感測器，信號處理電路可進行與距離估算相關的應用處理。起始信號ST1的上升緣出現的時間可為飛行時間距離感測器發射光束的時間點或超聲波感測器發射聲波的時間點，而停止信號SP1產生上升緣的時間點可例如為飛行時間距離感測器接收到反射光束的時間點或超聲波感測器接收到反射聲波的時間點。此外，時間數位轉換器104也可例如依據計數時脈信號CK0~CK3的下降緣進行計數，並依據起始信號ST1與停止信號SP1的下降緣來決定第一計數值與第二計數值。The digital signal D1 can be transmitted to the signal processing circuit of the subsequent stage for signal application processing. For example, when the time-to-digital conversion device is applied to a distance sensing device, such as a time-of-flight distance sensor or an ultrasonic sensor, the signal processing circuit can perform application processing related to distance estimation. The time when the rising edge of the start signal ST1 appears can be the time when the time-of-flight distance sensor emits a light beam or the time when the ultrasonic sensor emits a sound wave, and the time when the stop signal SP1 generates a rising edge can be, for example, the time-of-flight distance The time point when the sensor receives the reflected light beam or the time point when the ultrasonic sensor receives the reflected sound wave. In addition, the time-to-digital converter 104 can also count according to the falling edges of the counting clock signals CK0-CK3, and determine the first count value and the second count value according to the falling edges of the start signal ST1 and the stop signal SP1.

圖4是依照本新型創作一實施例所繪示的時間數位轉換裝置的時間數位轉換方法流程圖。由上述實施例可知，時間數位轉換裝置的時間數位轉換方法可至少包括下列步驟。首先，致能時脈產生電路產生n個時脈信號(步驟S402)，其中n為正整數，例如可提供第一致能信號給時脈產生電路以致能時脈產生電路產生n個時脈信號。然後，於時脈產生電路開始產生n個時脈信號起經過一段預設時間後，開始計數n個時脈信號的上升緣或下降緣，以產生數位信號(步驟S404)，例如可依據第二致能信號於時脈產生電路開始產生n個時脈信號起經過預設時間後，開始計數n個時脈信號的上升緣或下降緣，以產生數位信號。其中預設時間可例如為依據n個時脈信號的脈波寬度的變化在一段觀察時間內小於預設值所需的時間決定。如此等待時脈產生電路輸出的時脈信號穩定後，再進行上升緣或下降緣的計數，可確保時間數位轉換裝置產生的數位信號的正確性不因時脈產生電路的時脈信號不穩定而受到影響。FIG. 4 is a flowchart of a time-to-digital conversion method of the time-to-digital conversion device according to an embodiment of the present invention. It can be known from the above embodiments that the time-to-digital conversion method of the time-to-digital conversion device may include at least the following steps. First, enable the clock generation circuit to generate n clock signals (step S402 ), where n is a positive integer. For example, a first enable signal can be provided to the clock generation circuit to enable the clock generation circuit to generate n clock signals . Then, after a predetermined period of time has elapsed since the clock generating circuit starts to generate n clock signals, it starts to count the rising edges or falling edges of the n clock signals to generate digital signals (step S404 ). For example, according to the second The enabling signal starts counting the rising edges or falling edges of the n clock signals after a preset time elapses after the clock generating circuit starts to generate the n clock signals to generate the digital signal. The preset time may be determined, for example, according to the time required for the variation of the pulse width of the n clock signals to be less than the preset value within a period of observation time. Waiting for the clock signal output by the clock generating circuit to stabilize in this way, and then counting the rising edge or falling edge, can ensure that the correctness of the digital signal generated by the time-to-digital conversion device is not affected by the instability of the clock signal of the clock generating circuit. affected.

圖5是依照本新型創作另一實施例所繪示的時間數位轉換裝置的時間數位轉換方法流程圖。相較於圖4實施例，本實施例的時間數位轉換方法為依據兩個計數值來產生代表時間信息的數位信號。如圖5所示，可依據依序接收到的起始信號與停止信號的時間決定對應的第一計數值與第二計數值(步驟S502)，然後再依據第一計數值與第二計數值產生數位信號(步驟S504)，舉例來說，可依據第一計數值與第二計數值的差值產生數位信號。其中起始信號與停止信號可例如為脈衝信號，第一計數值與第二計數值可為依據起始信號與停止信號的上升緣或下降緣的產生時間所對應的計數值決定。FIG. 5 is a flowchart of a time-to-digital conversion method of a time-to-digital conversion device according to another embodiment of the present invention. Compared with the embodiment of FIG. 4 , the time-to-digital conversion method of the present embodiment generates a digital signal representing time information according to two count values. As shown in FIG. 5 , the corresponding first count value and the second count value can be determined according to the times of the start signal and the stop signal received in sequence (step S502 ), and then according to the first count value and the second count value The digital signal is generated (step S504 ). For example, the digital signal can be generated according to the difference between the first count value and the second count value. The start signal and the stop signal can be, for example, pulse signals, and the first count value and the second count value can be determined according to the count values corresponding to the generation time of the rising edge or the falling edge of the start signal and the stop signal.

綜上所述，本新型創作實施例的時間數位轉換器可於時脈產生電路開始產生時脈信號起經過一段預設時間後，開始計數時脈信號的上升緣或下降緣，以產生數位信號。如此等待時脈產生電路輸出的時脈信號穩定後，再進行上升緣或下降緣的計數，可確保時間數位轉換裝置產生的數位信號的正確性不因時脈產生電路的時脈信號不穩定而受到影響。To sum up, the time-to-digital converter of the new inventive embodiment can start to count the rising edge or the falling edge of the clock signal after a predetermined period of time after the clock generation circuit starts to generate the clock signal to generate the digital signal . Waiting for the clock signal output by the clock generating circuit to stabilize in this way, and then counting the rising edge or falling edge, can ensure that the correctness of the digital signal generated by the time-to-digital conversion device is not affected by the instability of the clock signal of the clock generating circuit. affected.

雖然本新型創作已以實施例揭露如上，然其並非用以限定本新型創作，任何所屬技術領域中具有通常知識者，在不脫離本新型創作的精神和範圍內，當可作些許的更動與潤飾，故本新型創作的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed above with examples, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the new creation should be determined by the scope of the appended patent application.

102:時脈產生電路 104:時間數位轉換器 CK0~CKn-1:時脈信號 D1:數位信號 EN1、EN2:致能信號 SP1:停止信號 ST1:起始信號 T1:預設時間 S402~S405、S502~S504:時間數位轉換方法的步驟 102: Clock generation circuit 104: Time to Digitizer CK0~CKn-1: Clock signal D1: digital signal EN1, EN2: enable signal SP1: stop signal ST1: start signal T1: Preset time S402~S405, S502~S504: the steps of the time-to-digital conversion method

圖1是依照本新型創作一實施例所繪示的時間數位轉換裝置的方塊示意圖。 圖2是依照本新型創作一實施例所繪示的時間數位轉換裝置的運作時序示意圖。 圖3是依照本新型創作另一實施例所繪示的時間數位轉換裝置的運作時序示意圖。 圖4是依照本新型創作一實施例所繪示的時間數位轉換裝置的時間數位轉換方法流程圖。 圖5是依照本新型創作另一實施例所繪示的時間數位轉換裝置的時間數位轉換方法流程圖。 FIG. 1 is a schematic block diagram of a time-to-digital conversion device according to an embodiment of the present invention. FIG. 2 is a schematic diagram illustrating an operation sequence of a time-to-digital conversion device according to an embodiment of the present invention. FIG. 3 is a schematic diagram illustrating the operation sequence of the time-to-digital conversion device according to another embodiment of the present invention. FIG. 4 is a flowchart of a time-to-digital conversion method of the time-to-digital conversion device according to an embodiment of the present invention. FIG. 5 is a flowchart of a time-to-digital conversion method of a time-to-digital conversion device according to another embodiment of the present invention.

102:時脈產生電路 102: Clock generation circuit

104:時間數位轉換器 104: Time to Digitizer

CK0~CKn-1:時脈信號 CK0~CKn-1: Clock signal

D1:數位信號 D1: digital signal

EN1、EN2:致能信號 EN1, EN2: enable signal

SP1:停止信號 SP1: stop signal

Claims (6)

一種時間數位轉換裝置，包括： 一時脈產生電路，產生具有不同相位的n個時脈信號，其中n為正整數；以及 一時間數位轉換器，耦接該時脈產生電路，於該時脈產生電路開始產生該n個時脈信號起經過一段預設時間後，開始計數該n個時脈信號的上升緣或下降緣，以產生一數位信號給信號處理電路。 A time-to-digital conversion device, comprising: a clock pulse generating circuit that generates n clock signals with different phases, wherein n is a positive integer; and A time-to-digital converter, coupled to the clock generation circuit, starts to count the rising edge or the falling edge of the n clock signals after a predetermined period of time after the clock generation circuit starts to generate the n clock signals , to generate a digital signal to the signal processing circuit. 如請求項1所述的時間數位轉換裝置，其中該時間數位轉換器依據一起始信號與一停止信號決定一第一計數值與一第二計數值，並依據該第一計數值與該第二計數值產生該數位信號。The time-to-digital conversion device of claim 1, wherein the time-to-digital converter determines a first count value and a second count value according to a start signal and a stop signal, and according to the first count value and the second count value The count value generates this digital signal. 如請求項2所述的時間數位轉換裝置，其中該時間數位轉換器依據該第一計數值與該第二計數值的差值產生該數位信號。The time-to-digital conversion device of claim 2, wherein the time-to-digital converter generates the digital signal according to the difference between the first count value and the second count value. 如請求項2所述的時間數位轉換裝置，其中該起始信號與該停止信號為脈衝信號，該時間數位轉換器依據該起始信號與該停止信號的上升緣或下降緣的產生時間決定對應的該第一計數值與該第二計數值。The time-to-digital conversion device according to claim 2, wherein the start signal and the stop signal are pulse signals, and the time-to-digital converter determines the correspondence according to the generation time of the rising edge or the falling edge of the start signal and the stop signal The first count value and the second count value of . 如請求項1所述的時間數位轉換裝置，其中該預設時間為依據該n個時脈信號的脈波寬度的變化在一段觀察時間內小於一預設值所需的時間決定。The time-to-digital conversion device according to claim 1, wherein the predetermined time is determined according to the time required for the pulse width variation of the n clock signals to be less than a predetermined value within a period of observation time. 如請求項1所述的時間數位轉換裝置，其中該時脈產生電路依據一第一致能信號產生該n個時脈信號，該時間數位轉換器依據一第二致能信號於該時脈產生電路開始產生該n個時脈信號起經過該預設時間後，開始計數該n個時脈信號的上升緣或下降緣，以產生該數位信號。The time-to-digital conversion device of claim 1, wherein the clock generating circuit generates the n clock signals according to a first enable signal, and the time-to-digital converter generates the clock according to a second enable signal After the preset time elapses since the circuit starts to generate the n clock signals, the circuit starts to count the rising edge or the falling edge of the n clock signals to generate the digital signal.
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