TWI788971B - Display - Google Patents

Abstract

A display includes a pixel circuit and multiple shift registers. One of the shift registers includes an emission controlling circuit, a slope wave output circuit and a square wave output circuit. The emission controlling circuit generates an emission controlling signal at a first node, and controls the pixel circuit by the emission controlling signal. The slope wave output circuit outputs a first slope wave signal according to a voltage level of the first node. The square wave output circuit includes a first switch, a capacitor and a second switch. The first switch turns on according to the voltage level of the first node. A first terminal of the first switch outputs a first square wave signal. A first terminal of the capacitor is coupled to the first terminal of the first switch. A second terminal of the capacitor is coupled to a control terminal of the first switch. The second switch is turned off when the first switch is turned on. A first terminal of the second switch is coupled to the first terminal of the first switch.

Description

monitor

The present invention relates to a display technology, in particular to a display.

When driving the LED panel, the display device operates according to a pulse-width modulation (PWM) square-wave signal, a square-wave signal, and a light-emitting control signal. However, the operations of the square wave output circuit, the ramp wave output circuit and the lighting control circuit cannot bring gain to each other. In addition, the circuit cannot be detected when there is a short circuit in the active area. Therefore, how to develop related technologies that can overcome the above problems is an important issue in this field.

Embodiments of the invention include a display. The display includes at least one pixel circuit and multiple shift registers. A shift register among the plurality of shift registers includes a lighting control circuit, a ramp wave output circuit and a square wave output circuit. The lighting control circuit is used to generate a lighting control signal at the first node, and control at least one pixel circuit by the lighting control signal. The ramp output circuit is used for outputting a first ramp signal according to the voltage level of the first node. The square wave output circuit includes a first switch, a capacitor and a second switch. The first switch is used for conducting according to the voltage level of the first node, and the first terminal of the first switch is used for outputting a first square wave signal. The first terminal of the capacitor is coupled to the first terminal of the first switch, and the second terminal of the capacitor is coupled to the control terminal of the first switch. The second switch is used for turning on when the first switch is turned off, and the first terminal of the second switch is coupled to the first terminal of the first switch.

Herein, when an element is referred to as "connected" or "coupled", it may mean "electrically connected" or "electrically coupled". "Connected" or "coupled" may also be used to indicate that two or more elements cooperate or interact with each other. In addition, although terms such as “first”, “second”, . Unless clearly indicated by the context, the terms do not imply any particular order or sequence, nor are they intended to be limiting of the invention.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted to have meanings consistent with their meanings in the context of the relevant art and the present invention, and will not be interpreted as idealized or excessive formal meaning, unless expressly so defined herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include plural forms including "at least one" unless the content clearly dictates otherwise. "Or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It should also be understood that when used in this specification, the terms "comprising" and/or "comprising" designate the stated features, regions, integers, steps, operations, the presence of elements and/or parts, but do not exclude one or more Existence or addition of other features, regions as a whole, steps, operations, elements, parts and/or combinations thereof.

The following will disclose multiple implementation modes of this case with diagrams. For the sake of clarity, many practical details will be described together in the following description. It should be understood, however, that these practical details should not be used to limit the present case. That is, in some embodiments of the present disclosure, these practical details are unnecessary. In addition, for the sake of simplifying the drawings, some well-known structures and components will be shown in a simple and schematic manner in the drawings.

FIG. 1 is a schematic diagram of a display 100 according to an embodiment of the present application. Please refer to FIG. 1 , the display 100 includes a display device 110 , a scanning device 120 , a data input device 130 and a light emission control device 140 . In some embodiments, the display 100 may be made of a glass substrate or a plastic substrate, but is not limited thereto.

In some embodiments, the scanning device 120 provides a plurality of scanning signals to the display device 110 through the scanning lines SL( 1 )˜SL(n). The data input device 130 provides a plurality of data signals to the display device 110 through the data lines DL( 1 )˜DL(m). Where n and m are both positive integers. The light emission control device 140 provides light emission control signals through the light emission lines EL(1)~EL(n), such as the light emission control signal EM(n), the square wave signal SQ(n) and the ramp wave signal SW(n) shown in the second figure. ), to the display device 110.

As shown in FIG. 1 , the display device 110 includes a plurality of pixel driving circuits connected in series, including a pixel driving circuit 112 . The pixel driving circuit 112 includes a light emitting element L1. In some embodiments, the pixel driving circuit 112 in the display device 110 performs light emitting operation according to the signals provided by the scanning device 120 , the data input device 130 and the light emitting control device 140 . In some embodiments, the pixel driving circuit 112 is used to generate the current I1 according to the light-emitting control signal, so that the light-emitting element L1 emits light according to the current I1. In some embodiments, the current I1 flows through the light emitting element L1. In different embodiments, the light emitting element L1 may be a micro light emitting diode (mLED) or other different types of light emitting elements.

As shown in FIG. 1 , the light emission control device 140 includes a plurality of shift registers SR( 1 )˜SR(n). The shift registers SR( 1 )˜SR(n) are respectively coupled to the light emitting lines EL( 1 )˜EL(n). In some embodiments, the shift register SR(n) is used to generate the light-emitting control signal and provide the light-emitting control signal to the pixel driving circuit 112 .

FIG. 2 is a circuit diagram of a shift register 200 according to an embodiment of the present application. The shift register 200 is an embodiment of the shift register SR(n) shown in FIG. 1 . As shown in FIG. 2 , the shift register 200 includes a lighting control circuit 210 , a square wave output circuit 220 and a ramp wave output circuit 230 .

As shown in FIG. 2 , the light emission control circuit 210 is used to generate the light emission control signal EM(n) at the node N24 according to the start signal STV, the clock signals CLK1 and CLK2 and the voltage signals GH and GL.

As shown in FIG. 2 , the square wave output circuit 220 is used to generate a square wave signal SQ(n) at the node N27 according to the square wave signal SQIN(K) and the voltage regulator signal SQH, wherein K is a positive integer. In some embodiments, n is an integer multiple of K, and n/K shift registers in the shift registers SR(1)~SR(n) shown in Figure 1 are used for the receiver wave signal SQIN(K). In some embodiments, the square wave signal SQIN(K) is a simulated square wave single-stage signal source.

As shown in FIG. 2 , the ramp output circuit 230 is used to generate the ramp signal SW(n) at the node N28 according to the ramp signal SWIN(K) and the voltage regulator signal SWH. In some embodiments, n/n shift registers among the shift registers SR( 1 )˜SR(n) shown in FIG. 1 are used to receive the ramp signal SWIN(K). In some embodiments, the square wave signal SWIN(K) is a simulated ramp single stage signal source.

As shown in FIG. 2 , the light emission control circuit 210 includes switches T1 ˜ T3 , T6 ˜ T10 and capacitors C1 , C3 . One end of the switch T1 is used to receive the start signal STV at the node N21 , one end of the switch T1 is coupled to the node N22 , and the control end of the switch T1 is used to receive the clock signal CLK1 . One end of the switch T2 is used to receive the voltage signal GH, the other end of the switch T2 is coupled to the node N23 , and the control end of the switch T2 is coupled to the node N21 . One terminal of the switch T3 is used to receive the voltage signal GL, the other terminal of the switch T3 is coupled to the node N24 , and the control terminal of the switch T3 is coupled to the node N22 . One terminal of the switch T6 is used to receive the voltage signal GL, the other terminal of the switch T6 is coupled to the node N25 , and the control terminal of the switch T6 is coupled to the node N23 . One end of the switch T7 is used to receive the voltage signal GH, the other end of the switch T7 is coupled to the node N25 , and the control end of the switch T7 is coupled to the node N22 . One terminal of the switch T8 is used to receive the voltage signal GH, the other terminal of the switch T8 is coupled to the node N22 , and the control terminal of the switch T8 is coupled to the node N25 . One terminal of the switch T9 is used to receive the voltage signal GH, the other terminal of the switch T9 is coupled to the node N24, and the control terminal of the switch T9 is coupled to the node N25. One terminal of the switch T10 is used to receive the voltage signal GH, the other terminal of the switch T10 is coupled to the node N26 , and the control terminal of the switch T10 is coupled to the node N25 . One end of the capacitor C1 is used to receive the clock signal CLK2 , and the other end of the capacitor C1 is coupled to the node N22 . One end of the capacitor C3 is used to receive the clock signal CLK1, and the other end of the capacitor C3 is coupled to the node N23.

In different embodiments, the lighting control circuit 210 can also receive the clock signal in different ways. For example, the capacitor C1 can also be used to receive the clock signal CLK1, and the capacitor C3 and the switch T1 can also be used to receive the clock signal CLK2.

As shown in FIG. 2, the square wave output circuit 220 includes switches T4, T5Q, T11Q and a capacitor C2. One terminal and the control terminal of the switch T4 are coupled to the node N24, and the other terminal of the switch T4 is coupled to the node N26. One terminal of the switch T5Q is used to receive the square wave signal SQIN(K), the other terminal of the switch T5Q is coupled to the node N27 , and the control terminal of the switch T5Q is coupled to the node N26 . One end of the switch T11Q is used to receive the voltage regulator signal SQH, the other end of the switch T11Q is coupled to the node N27 , and the control end of the switch T11Q is coupled to the node N25 . One end of the capacitor C2 is coupled to the node N27, and the other end of the capacitor C2 is coupled to the node N26.

As shown in FIG. 2 , the ramp output circuit 230 includes switches T5W and T11W. One terminal of the switch T5W is used to receive the ramp signal SWIN(K), the other terminal of the switch T5W is coupled to the node N28 , and the control terminal of the switch T5W is coupled to the node N26 . One terminal of the switch T11W is used to receive the voltage regulator signal SWH, the other terminal of the switch T11W is coupled to the node N28 , and the control terminal of the switch T11W is coupled to the node N25 .

In different embodiments, the switches T1~T4, T5Q, T5W, T6~T10, T11Q, and T11W may be P-type metal oxide semiconductor field effect transistors (PMOS), N-type metal oxide semiconductor field effect transistors ( NMOS), Thin Film Transistor (TFT) or other different types of switching elements.

FIG. 3 is a circuit diagram of a shift register 300 according to an embodiment of the present application. The shift register 300 is an embodiment of the shift register SR(n) shown in FIG. 1 . The shift register 300 is a modified example of the shift register 200 shown in FIG. 2 .

Please refer to FIG. 3 and FIG. 2 , the configuration of the shift register 300 is similar to that of the shift register 200 , so some details will not be repeated. Compared with the shift register 200 , the shift register 300 further includes switches TAT1 and TAT2 . In various embodiments, the shift register 300 may also include one of the switches TAT1 and TAT2 .

As shown in FIG. 3 , one end of the switch TAT1 is coupled to the node N21 , the other end of the switch TAT1 is coupled to the node N22 , and the control end of the switch TAT1 is used to receive the detection signal AT. One end of the switch TAT2 is coupled to the node N24 , and the other end and the control end of the switch TAT1 are used for receiving the detection signal AT. In some embodiments, the switches TAT1 and TAT2 are used to perform a detection operation to detect whether the shift register 300 is operating normally. The details of the detection operation are further described below in relation to the embodiment of FIG. 6 .

FIG. 4 is a timing diagram 400 illustrating the operation of the shift register 300 according to an embodiment of the present invention. In other embodiments, the operations shown in the timing diagram 400 can also be applied to the shift register 200 shown in FIG. 2 . As shown in FIG. 4 , the timing diagram 400 sequentially includes time points M1 - M6 . In some embodiments, the timing diagram 400 corresponds to different signals shown in FIG. 3, such as the start signal STV, the clock signals CLK1, CLK2, the square wave signals SQIN(K), SQ(n), the light emission control signal EM( n) and ramp signal SWIN (K), SW (n) operation.

FIG. 5A to FIG. 5F are circuit operation diagrams illustrating the operation of the shift register 300 according to the timing diagram 400 according to an embodiment of the present invention. FIG. 5A to FIG. 5F correspond to the operations of the shift register 300 at times M1 to M6 respectively. In the embodiment corresponding to FIG. 5A to FIG. 5F , the switches TAT1 and TAT2 are kept closed.

Please refer to FIG. 5A and FIG. 4 , at time M1 , the clock signal CLK1 has the disable voltage level VGH, so that the switch T1 is turned off. The clock signal CLK2 has a disable voltage level VGH, so that the capacitor C1 pulls the node N22 to the disable voltage level VGH through capacitive coupling, so that the switches T3 and T7 are turned off.

At time M1, the start signal STV has the enable voltage level VGL, so that the switch T2 is turned on. At this moment, the switch T2 provides the voltage signal GH having the disabled voltage level VGH to the node N23, so that the switch T6 is turned off. At this time, the node N25 has the enabling voltage level VGL, so that the switches T8˜T10, T11Q, and T11W are turned on. The switch T8 provides the voltage signal GH to the node N22 to stabilize the voltage of the node N22. The switch T9 provides the voltage signal GH to the node N24, so that the switch T4 is turned off, and the light emission control signal EM(n) has a disabled voltage level VGH.

At time M1, the switch T10 provides the voltage signal GH to the node N26, so that the switches T5Q and T5W are turned off. The switch T11Q provides the regulated signal SQH with the voltage level VQH to the node N27, so that the square wave signal SQ(n) at the node N27 has the voltage level VQH. The switch T11W provides the regulated signal SWH having the voltage level VWH to the node N28 such that the ramp signal SW(n) at the node N28 has the voltage level VWH.

Please refer to FIG. 5B and FIG. 4 , at time M2 , the clock signal CLK1 has the enabling voltage level VGL, so that the switch T1 is turned on. The switch T1 pulls the node N22 to the enable voltage level (VGL+|V _TH |) according to the start signal STV having the enable voltage level VGL, so that the switches T3 and T7 are turned on. The threshold voltage level V _TH is the threshold voltage level of the switch T1 .

At time M2, the start signal STV has the enabling voltage level VGL, so that the switch T2 is turned on. At this time, the switch T2 provides the voltage signal GH to the node N23, so that the switch T6 is turned off. The switch T7 provides the voltage signal GH to the node N25, so that the switches T8˜T10, T11Q, T11W are turned off. The switch T3 pulls the node N24 to the enable voltage level (VGL+|V _TH |) according to the enable voltage level (VGL+|V _TH |) of the node N22 and the voltage signal GL, so that the switch T4 is turned on, and the light emission control signal EM(n) has an enable voltage level (VGL+|V _TH |).

At time M2, the switch T4 pulls the node N26 to the enable voltage level according to the enable voltage level (VGL+|V _TH |) of the node N24, so that the switches T5Q and T5W are turned on. The switch T5Q provides the square wave signal SQIN(K) to the node N27. At this moment, the square wave signal SQIN(K) has the voltage level VQH, so that the square wave signal SQ(n) at the node N27 has the voltage level VQH. The switch T5W provides the ramp signal SWIN(K) to the node N28. At this moment, the ramp signal SWIN(K) has the voltage level VWH, so that the ramp signal SW(n) at the node N28 has the voltage level VWH.

Please refer to FIG. 5C and FIG. 4 , at time M3 , the clock signal CLK1 has the disable voltage level VGH, so that the switch T1 is turned off. The clock signal CLK2 has an enabling voltage level VGL, so that the capacitor C1 pulls the voltage of the node N22 to the enabling voltage level VLL through capacitive coupling, and turns on the switches T3 and T7. In some embodiments, the enable voltage level VLL is lower than the enable voltage level VGL.

At time M3, the start signal STV has the enabling voltage level VGL, so that the switch T2 is turned on. At this time, the switch T2 provides the voltage signal GH to the node N23, so that the switch T6 is turned off. The switch T7 provides the voltage signal GH to the node N25, so that the switches T8˜T10, T11Q, T11W are turned off. The switch T3 pulls the node N24 to the enable voltage level VGL according to the enable voltage level VLL of the node N22 and the voltage signal GL, so that the switch T4 is turned on, and the light emission control signal EM(n) has the enable voltage level VGL.

At time M3, the switch T4 pulls the node N26 to the enabling voltage level according to the enabling voltage level VGL of the node N24, so that the switches T5Q and T5W are turned on. The switch T5Q provides the square wave signal SQIN(K) to the node N27. At this moment, the square wave signal SQIN(K) has the voltage level VQH, so that the square wave signal SQ(n) at the node N27 has the voltage level VQH. The switch T5W provides the ramp signal SWIN(K) to the node N28. At this time, the ramp signal SWIN(K) is gradually pulled from the voltage level VWH to the voltage level VWL, so that the ramp signal SW(n) at the node N28 is gradually pulled from the voltage level VWH to the voltage level VWL.

Please refer to FIG. 1, FIG. 4 and FIG. 5C, at time M3, the pixel driving circuit 112 is used to change the The current I1 flowing through the light emitting element L1 is adjusted from the current level AL to the current level AH, so that the light emitting element L1 emits light. In some embodiments, the light emitting element L1 emits light when the current I1 has a current level AH. In some embodiments, the current level AL is a zero current level.

Please refer to FIG. 5D and FIG. 4 , at time M4 , the clock signal CLK1 has the disable voltage level VGH, so that the switch T1 is turned off. The clock signal CLK2 has an enabling voltage level VGL, so that the capacitor C1 pulls the voltage of the node N22 to the enabling voltage level VLL through capacitive coupling, and turns on the switches T3 and T7.

At time M4, the start signal STV has the enable voltage level VGL, so that the switch T2 is turned on. At this time, the switch T2 provides the voltage signal GH to the node N23, so that the switch T6 is turned off. The switch T7 provides the voltage signal GH to the node N25, so that the switches T8˜T10, T11Q, T11W are turned off. The switch T3 pulls the node N24 to the enable voltage level VGL according to the enable voltage level VLL of the node N22 and the voltage signal GL, so that the switch T4 is turned on, and the light emission control signal EM(n) has the enable voltage level VGL.

At time M4, the switch T4 pulls the node N26 to the enabling voltage level according to the enabling voltage level VGL of the node N24, so that the switches T5Q and T5W are turned on. The switch T5Q provides the square wave signal SQIN(K) to the node N27. At this time, the square wave signal SQIN(K) has the voltage level VQL, so that the square wave signal SQ(n) has the voltage level VQL. The capacitor C2 pulls the node N26 to the enabling voltage level VM according to the current level VQL of the node N27 through capacitive coupling, so as to further turn on the switches T5Q and T5W. In some embodiments, the voltage level VQL is lower than the voltage level VQH, so that the node N26 is pulled to the enable voltage level VM lower than the enable voltage level VGL to stabilize the node N26.

At time M4, the switch T5W provides the ramp signal SWIN(K) to the node N27. At this time, the ramp signal SWIN(K) is gradually pulled from the voltage level VWH to the voltage level VWL, so that the ramp signal SW(n) at the node N28 is gradually pulled from the voltage level VWH to the voltage level VWL. In some embodiments, the pixel driving circuit 112 shown in FIG. 1 maintains the current I1 at the current level AH according to the ramp signal SW(n). In various embodiments, the voltage levels VWH, VQH and VGH may be the same as or different from each other.

Please refer to FIG. 5E and FIG. 4 , at time M5 , the clock signal CLK1 enables the voltage level VGL to turn on the switch T1 . The start signal STV has an enable voltage level VGL, so that the switch T2 is turned on. At this time, the switch T1 provides the start signal STV to the node N22 , so that the switches T3 and T7 are turned on.

At time M5, the switch T2 provides the voltage signal GH to the node N23, so that the switch T6 is turned off. The switch T7 provides the voltage signal GH to the node N25, so that the switches T8˜T10, T11Q, T11W are turned off. The switch T3 pulls the node N24 to the enable voltage level VGL according to the enable voltage level of the node N22 and the voltage signal GL, so that the switch T4 is turned on, and the light emission control signal EM(n) has the enable voltage level VGL. In some embodiments, the capacitor C1 is used to maintain the node N22 at the enable voltage level at the moment M5.

At time M5, the switch T4 pulls the node N26 to the enabling voltage level according to the enabling voltage level VGL of the node N24, so that the switches T5Q and T5W are turned on. The switch T5Q provides the square wave signal SQIN(K) to the node N27. At this time, the square wave signal SQIN(K) has the voltage level VQL, so that the square wave signal SQ(n) has the voltage level VQL. The capacitor C2 maintains the node N26 at the enabling voltage level VM according to the current level VQL of the node N27 through capacitive coupling.

At time M5, the switch T5W provides the ramp signal SWIN(K) to the node N28. At this time, the ramp signal SWIN(K) is gradually pulled from the voltage level VWH to the voltage level VWL, so that the ramp signal SW(n) at the node N28 is gradually pulled from the voltage level VWH to the voltage level VWL. In some embodiments, the pixel driving circuit 112 shown in FIG. 1 maintains the current I1 at the current level AH according to the ramp signal SW(n).

Please refer to FIG. 5F and FIG. 4 , at time M6 , the clock signal CLK1 has the enabling voltage level VGL, so that the switch T1 is turned on. At this time, the start signal STV has the disable voltage level VGH, and the start signal STV of the switch T1 is provided to the node N22, so that the switches T3 and T7 are turned off. At this time, the capacitor C3 pulls the node N22 to the enable voltage level VGL through capacitive coupling, so that the switch T6 is turned on.

At time M6, the start signal STV has the disable voltage level VGH, so that the switch T2 is turned off. At this time, the switch T6 provides the voltage signal GL having the enabling voltage level VGL to the node N25 , so that the switches T8 ˜ T10 , T11Q, and T11W are turned on. The switch T8 provides a voltage signal GH having a disabled voltage level VGH to the node N22 to stabilize the voltage of the node N22. The switch T9 provides the voltage signal GH to the node N24, so that the switch T4 is turned off, and the light emission control signal EM(n) has a disabled voltage level VGH.

At time M6, the switch T10 provides the voltage signal GH to the node N26, so that the switches T5Q and T5W are turned off. The switch T11Q provides the regulated signal SQH with the voltage level VQH to the node N27, so that the square wave signal SQ(n) at the node N27 has the voltage level VQH. The switch T11W provides the regulated signal SWH having the voltage level VWH to the node N28 such that the ramp signal SW(n) at the node N28 has the voltage level VWH.

Please refer to FIG. 1 and FIG. 4, in some embodiments, before time M6, the pixel driving circuit 112 is further used to pull the current I1 to the current level AL according to the pinch off signal, so that the pixel The driving circuit 112 does not emit light.

Please refer to FIG. 5E, FIG. 5D and FIG. 4, at time M4 and M5, the square wave output circuit 220 can use the capacitor C2 and the square wave signal SQIN(K) to stabilize the node N26, so that the switches T5Q and T5W can be stabilized The ground outputs square wave signal SQ(n) and ramp wave signal SW(n) respectively.

Please refer to FIG. 5A , FIG. 5F and FIG. 4 , at time M1 and M6 , switches T9 , T11Q and T11W are used to stabilize voltage nodes N24 , N27 and N28 respectively. The voltage signals GH, SQH, and SWH used for voltage stabilization are different voltage signals, so that the light emission control signal EM(n) at the node N24, the square wave signal SQ(n) at the node N27, and the ramp signal SW at the node N28 (n) are respectively regulated at corresponding voltage levels VGH, VQH and VWH.

In some previous approaches, the lighting control circuit, the square wave output circuit and the ramp wave output circuit in the display are independent of each other, and cannot bring gains to each other's operations. In addition, in the above method, the lighting control circuit, the square wave output circuit and the ramp wave output circuit are not stabilized by their respective voltage signals, which may easily cause the problem of poor circuit output.

Compared with the above method, in the embodiment of the present invention, the light emission control circuit 210 adjusts the voltage of the node N26 according to the voltage of the node N24, and the square wave output circuit 220 further gains the voltage of the node N26 through the capacitor C2, so as to gain simultaneously The wave output circuit 220 itself and the ramp output circuit 230. In addition, the light emission control circuit 210 , the square wave output circuit 220 and the ramp wave output circuit 230 can be respectively regulated at corresponding voltage levels VGH, VQH and VWH.

FIG. 6 is a circuit diagram illustrating the detection operation of the shift register 300 according to an embodiment of the present invention.

As shown in FIG. 6 , when the detection operation is performed, the detection signal AT has the enable voltage level VGL, so that the switches TAT1 and TAT2 are turned on. The switch TAT1 is used to provide the start signal STV having the enabling voltage level VGL to the node N22 to turn on the switches T7 and T3 .

When performing the detection operation, the start signal STV has the enable voltage level VGL, so that the switch T2 is turned on. At this time, the switch T2 provides the voltage signal GH to the node N23, so that the switch T6 is turned off. The switch T7 provides the voltage signal GH to the node N25, so that the switches T8˜T10, T11Q, T11W are turned off. The switch T3 provides the voltage signal GL to the node N24, and the switch TAT2 provides the detection signal AT to the node N24, so that the switch T4 is turned on.

When performing the detection operation, the switch T4 pulls the node N26 to the enable voltage level according to the enable voltage level of the node N24, so that the switches T5Q and T5W are turned on. At this moment, the switch T5Q provides the square wave signal SQIN(K) to the node N27 , and the switch T5W provides the ramp signal SWIN(K) to the node N28 .

In some embodiments, the user can detect whether each element in the shift register 300 operates normally by measuring the voltage levels of the nodes N27 and N28 . For example, when the switch T5Q cannot be turned on normally or the switch T11Q cannot be turned off normally, it can be measured that the voltage level of the node N27 is abnormal.

In some embodiments, when performing the detection operation, the clock signal CLK1 has the disabled voltage level VGH, or the control terminal of the switch T1 is used to receive the voltage signal with the disabled voltage level VGH, so that the switch T1 is turned off.

In some previous approaches, the shift register in the display does not have a switch for detection, making it impossible to detect when the circuit is abnormal.

Compared with the above method, in the embodiment of the present invention, whether the internal components of the shift register 300 are abnormal can be detected through the detection signal AT, the switches TAT1 and TAT2.

The various signal generating methods and detection operation methods mentioned above in this case are used for illustration, and other various signal generation methods and detection operation methods are within the scope of this case.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

100: display

110: display device

120: Scanning device

130: data input device

140: Luminous control device

112:Pixel drive circuit

SL(1)~SL(n): scan line

DL(1)~DL(m): data line

EL(1)~EL(n): luminescent line

L1: light emitting element

I1: Current

SR(1)~SR(n), 200, 300: shift register

210: Lighting control circuit

220: Square wave output circuit

230: Ramp wave output circuit

STV: start signal

CLK1, CLK2: clock signal

GH, GL: voltage signal

EM(n): Light emission control signal

SQIN(K), SQ(n): square wave signal

SQH, SWH: steady voltage signal

SWIN(K), SW(n): ramp signal

T1~T4, T6~T10, T5Q, T11Q, T5W, T11W, TAT1, TAT2: switch

C1~C3: capacitance

N21~N28: nodes

AT: detection signal

400: Timing diagram

M1~M6: time

VGH: disabled voltage level

VGL: enable voltage level

VQH, VWH, VQL, VWL: voltage level

V _TH : Threshold voltage level

AL, AH: current level

Fig. 1 is a schematic diagram of a display according to an embodiment of the present application. FIG. 2 is a circuit diagram of a shift register according to an embodiment of the present invention. FIG. 3 is a circuit diagram of a shift register according to an embodiment of the present invention. FIG. 4 is a timing diagram illustrating the operation of the shift register according to an embodiment of the present invention. FIG. 5A to FIG. 5F are circuit operation diagrams showing that the shift register operates according to the timing diagram according to an embodiment of the present invention. FIG. 6 is a circuit diagram illustrating the detection operation of the shift register according to an embodiment of the present invention.

Domestic deposit information (please note in order of depositor, date, and number) none Overseas storage information (please note in order of storage country, institution, date, and number) none

300: shift register

STV: start signal

CLK1, CLK2: clock signal

GH, GL: voltage signal

EM(n): Light emission control signal

SQIN(K), SQ(n): square wave signal

SQH, SWH: steady voltage signal

SWIN(K), SW(n): ramp signal

T1~T4, T6~T10, T5Q, T11Q, T5W, T11W, TAT1, TAT2: switch

C1~C3: capacitance

N21~N28: nodes

AT: detection signal

Claims (10)

A display comprising at least one pixel circuit and a plurality of shift registers, one of the shift registers includes: a light emitting control circuit for generating a light emitting control signal in a first a node, and the at least one pixel circuit is controlled by the light-emitting control signal; a ramp wave output circuit is used to output a first ramp wave signal according to a voltage level of the first node; and a square wave output circuit, Including: a first switch, used to conduct according to the voltage level of the first node, a first terminal of the first switch is used to output a first square wave signal; a capacitor, a first terminal of the capacitor coupled to the first terminal of the first switch, a second terminal of the capacitor coupled to a control terminal of the first switch; and a second switch, used for conducting when the first switch is turned off, the second A first end of the switch is coupled to the first end of the first switch, wherein the ramp output circuit includes a third switch, a first end of the third switch is used to output the first ramp signal, the A control terminal of the third switch is coupled to a control terminal of the second switch. The display device as described in claim 1, wherein a second end of the third switch is used to receive a first regulated signal, and a second end of the second switch is used to receive a signal different from the first regulated signal A second regulated signal. The display device according to claim 2, wherein when the first switch is turned off, the second switch is used to pull the first square wave signal to a first voltage level, and the third switch is used to pull the first A ramp signal is pulled to a second voltage level different from the first voltage level. The display as described in claim 1, wherein the ramp output circuit further includes: a fourth switch, a first end of the fourth switch is used to output the first ramp signal, a second end of the fourth switch The terminal is used to receive a second ramp signal, and a control terminal of the fourth switch is coupled to the control terminal of the first switch. The display as described in claim 4, wherein the ramp output circuit further includes: a fifth switch, a first terminal of the fifth switch is used to output the first ramp signal, a second of the fifth switch terminal is used to receive a first regulated voltage signal, a control terminal of the fifth switch is coupled to a control terminal of the second switch, wherein a second terminal of the second switch is used to receive a signal different from the first regulated voltage A second regulated signal of the signal. The display as described in claim 1, wherein the square wave output circuit further includes: a fourth switch, a first terminal of the fourth switch and a control terminal of the fourth switch are coupled to the first node, the first terminal A second terminal of the four switches is coupled to the control terminal of the first switch. The display as described in claim 6, wherein a second end of the first switch is used to receive a second square wave signal, and the capacitor is further used to pull the second square wave signal according to the second square wave signal when the fourth switch is closed A voltage level of the second terminal of the fourth switch is lowered. The display as described in claim 1, wherein the shift register further includes: a fourth switch, a first terminal of the fourth switch and a control terminal of the fourth switch are used to receive a detection signal, the A second end of the fourth switch is coupled to the first node. The display as described in claim 1, wherein the light emission control circuit further includes: a fourth switch, a first end of the fourth switch is used to receive a voltage signal having a disabled voltage level, and the fourth switch A second end is coupled to a control end of the second switch; a fifth switch, a first end of the fifth switch is used to receive a voltage signal having an enable voltage level, a first end of the fifth switch Two terminals are coupled to the first node, wherein the shift register further includes a sixth switch, a first terminal of the sixth switch is coupled to a control terminal of the fourth switch and a control terminal of the fifth switch terminal, a control terminal of the sixth switch is used for receiving a detection signal. The display as described in claim 9, wherein the shift register further includes: a seventh switch, a first terminal of the seventh switch and a control terminal of the seventh switch are used to receive the detection signal, the A second end of the seventh switch is coupled to the first node.

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