TWI787795B - Pattern detection method and pattern detection system for semiconductor manufacturing process - Google Patents

Abstract

A pattern detection method for a semiconductor manufacturing process, which includes the following steps in sequence: the selection step is to select the process pattern unit and the corresponding data pattern unit formed on the substrate after the patterning process according to the pattern design data; the positioning step is from the process The pattern and data pattern units respectively select at least two corresponding patterns as the positioning process pattern and the positioning data pattern, and respectively obtain the connecting lines of the center points of these patterns, and overlap the endpoints of the aforementioned two connecting lines to obtain multiple alignment patterns ; The error calculation step is to calculate the difference between the process pattern in the alignment pattern and the corresponding data pattern to obtain the detection result. The data pattern unit can be compensated and corrected by using the detection result, and the edge error of the mask pattern can be corrected to improve the correction accuracy. In addition, the invention also provides a pattern detection system.

Description

Pattern detection method and pattern detection system for semiconductor manufacturing process

The invention relates to a pattern detection method and a pattern detection system, in particular to a pattern detection method and a pattern detection system suitable for semiconductor lithography process.

In the semiconductor industry, lithography is mainly used to make the circuit pattern to be formed on a wafer. Generally speaking, a mask data pattern is designed in advance, and a mask is obtained by drawing it, and according to the optical The imaging principle projects the pattern on the mask to the wafer, and then forms the circuit pattern on the wafer through patterning processes such as exposure, development or etching, wherein the circuit formed on the wafer after the process is The fineness of pattern lines and the accuracy of line width have a key influence on the electrical stability and miniaturization degree of subsequent semiconductor devices.

In the lithography process, the circuit patterns produced on the wafer are often different from the pre-designed GDS patterns or mask data patterns based on factors such as edge placement error, light diffraction effect, and focus deformation. difference, therefore, the industry often uses optical proximity correction (optical proximity Correction, OPC) method to correct the circuit pattern, which is mainly to compare and calculate the difference between the circuit pattern generated after the manufacturing process and the pre-designed mask data pattern or GDS patterns, and then correct the optical pattern accordingly. The mask data pattern is used to obtain a new photomask for subsequent corrective lithography processes. However, most of the current optical proximity corrections only use the one-dimensional distance difference between the patterns for correction, and there is no way to know the actual relative positional relationship between the patterns. meet predetermined needs.

Therefore, the object of the present invention is to provide a pattern detection method for semiconductor manufacturing process, which is used for pattern detection in semiconductor manufacturing process, and can be used for subsequent pattern correction to improve the accuracy of the process pattern.

Therefore, the pattern detection method of the semiconductor manufacturing process of the present invention includes a selection step, a positioning step, and an error calculation step.

The selection step is to select a process pattern unit based on a pattern design data, which is formed in a predetermined area of a substrate after a patterning process and has a plurality of process patterns, and is obtained from the pattern design data, having the same The process pattern unit in the predetermined area corresponds to the data pattern unit, and the data pattern unit has a plurality of data patterns corresponding to the process patterns.

The positioning step is performed by selecting at least two of the process patterns To locate the process pattern, to generate at least one process pattern connection line obtained by connecting the center points of the at least two positioning process patterns, and to obtain at least one data corresponding to the at least one process pattern connection line in the data patterns Pattern connection, overlapping the process pattern unit and the data pattern unit, and adjusting at least one of the process pattern unit and the data pattern unit to make the at least one process pattern connection and the at least one data pattern corresponding to each other The two ends of the connecting line are overlapped with each other to obtain a plurality of alignment patterns, wherein each alignment pattern is composed of a process pattern and a data pattern corresponding to each other.

The error calculation step is to calculate the difference between the process pattern and the corresponding data pattern in the alignment patterns, so as to obtain a detection result.

Another object of the present invention is to provide a pattern inspection method for semiconductor manufacturing process, which is used for the mask pattern inspection of semiconductor manufacturing process.

Therefore, the pattern detection method of the semiconductor manufacturing process of the present invention includes a selection step, a positioning step, and an error calculation step.

The selecting step is to select at least one mark pattern unit that is generated on different substrates and corresponding to each other, wherein the substrate is used to generate a mask pattern, and the at least one mark pattern unit has a plurality of marks that can be used for alignment detection. Marking patterns, and these marking patterns are selected from isolated patterns, low-density patterns, high-density line patterns with the same pitch, full mirror-symmetrical patterns, horizontally-symmetrical patterns or vertically-symmetrical patterns.

The positioning step is by selecting the at least one marker pattern on each substrate At least two of the marking patterns of the case unit are used as positioning marking patterns, and the positioning marking patterns on different substrates correspond to each other, so as to generate at least one center point of the at least two positioning marking patterns on the substrates respectively. The marking patterns obtained by the connecting lines are connected, the marking pattern units of the two substrates are overlapped, and at least one of the two marking pattern units is adjusted to the two ends of the corresponding at least one marking pattern connecting line overlap each other to obtain a plurality of alignment patterns, wherein each alignment pattern is composed of marking patterns formed on different substrates but correspondingly aligned with each other.

The error calculation step is to calculate the difference between the corresponding mark patterns in the alignment patterns to obtain a detection result.

Another object of the present invention is to provide a pattern detection system for semiconductor manufacturing process.

Therefore, the pattern detection system of the present invention includes a data selection unit, a positioning unit, and a calculation unit.

The data selection unit is used to select a process pattern unit based on a pattern design data, which is formed in a predetermined area of a substrate after a patterning process and has a plurality of process patterns, and obtained from the pattern design data, has A data pattern unit corresponding to the process pattern unit of the predetermined area, and the data pattern unit has a plurality of data patterns corresponding to the process patterns.

The positioning unit is used to select at least two of the process patterns as the positioning process patterns to generate at least one line from the center of the at least two positioning process patterns. The process pattern connection obtained by connecting the points, and at least one data pattern connection corresponding to the process pattern connection obtained from the data patterns, overlapping the process pattern unit and the data pattern unit, and adjusting the process At least one of the pattern unit and the data pattern unit is to make the two ends of the corresponding at least one process pattern connection line and the at least one data pattern connection line coincide with each other to obtain a plurality of alignment patterns, wherein each The alignment pattern is composed of a process pattern and a data pattern corresponding to each other.

The calculation unit is used for calculating the difference between two corresponding patterns in any one of the alignment patterns to generate a detection result.

The effect of the present invention lies in that the original data pattern unit and the process pattern unit actually formed on the base material are aligned pattern-to-pattern and then the difference between the two is compared to obtain the corrected optical pattern. The detection result of the two-dimensional correction data of the mask pattern can be used to correct the edge placement error (EPE) and position of the mask pattern, so as to further improve the accuracy of the process pattern.

200, 201: pattern detection system

21: Data selection unit

22: Positioning unit

23: Calculation unit

24:Warning unit

25: Correction unit

26: Image data generating unit

27: Mask drawing unit

31: Selection steps

32: Positioning step

33: Error calculation steps

34: Warning steps

35: Pattern correction steps

36: Mask drawing steps

40: Reservation area

4: Process pattern unit

41: Process pattern

411: The first positioning process pattern

412: The second positioning process pattern

5: Data pattern unit

51: Data pattern

511: The first positioning data pattern

512: Second positioning data pattern

6: Alignment pattern unit

61: Alignment pattern

8: Mark pattern unit

81:mark pattern

811: alignment mark pattern 811

100: Mask substrate

101: protective layer

L1, L2, L3: process pattern connection

d: distance

E: edge offset value

X: first direction

Y: the second direction

Other features and effects of the present invention will be clearly presented in the implementation manner with reference to the drawings, wherein: FIG. 1 is a schematic diagram illustrating a pattern detection system used in an embodiment of the pattern detection method of the present invention; Fig. 2 is a text flow chart, illustrating a first embodiment of the pattern detection method of the present invention; Fig. 3 is a schematic diagram, illustrating the process pattern unit, data pattern unit, and alignment pattern unit after the alignment of the present invention; Fig. 4 is A schematic diagram illustrating the data pattern unit of the present invention; FIG. 5 is a schematic diagram illustrating different implementations of the process pattern wiring used for alignment in the present invention; FIG. 6 is a schematic diagram illustrating the relationship between a process pattern and a data pattern Fig. 7 is a schematic diagram illustrating the pattern detection system used in the second embodiment of the pattern detection method of the present invention; Fig. 8 is a text flow chart illustrating the second embodiment of the pattern detection method of the present invention; and Fig. 9 It is a schematic diagram illustrating a structural schematic diagram of a plurality of marking pattern units on a mask substrate.

Before the present invention is described in detail, it should be noted that in the following description, similar elements are denoted by the same numerals.

The pattern detection method of the present invention is used in semiconductor manufacturing processes, for example, it can be used for pattern detection generated by patterning processes such as mask drawing, lithography or etching, so as to generate a detection method. Therefore, the original pattern can be corrected based on the detection result, and a correction pattern that can be used in the subsequent patterning process is generated to improve the accuracy of the process pattern.

Referring to FIG. 1 , a first embodiment of the pattern inspection method of the present invention is implemented by using a pattern generation system 200 for semiconductor manufacturing process. The pattern generation system 200 includes a data selection unit 21 , a positioning unit 22 , a calculation unit 23 , and a warning unit 24 .

The data selection unit 21 is used to select a process pattern unit formed in a predetermined area of a substrate after a patterning process and has a plurality of process patterns, and can obtain a process corresponding to the predetermined area from a pattern design data The data pattern unit corresponds to the pattern unit, and the data pattern unit has a plurality of data patterns corresponding to the process patterns.

Specifically, the substrate may be a semiconductor substrate or a glass substrate for forming a mask pattern, and the patterning process may be a lithography or etching process. The pattern design data is stored in the mask pattern generation system 200 for the mask drawing system to generate the pattern format of the process pattern unit, such as GDS, GDSII, OASIS, MEBES. The data pattern unit may be a preset data pattern stored in the pattern design data, or a mask pattern formed on the glass substrate through a patterning process according to the preset data pattern stored in the pattern design data. The data selection unit 21 can be an optical imaging device such as a stepper, a scanner, an electron microscope or an optical microscope, and the process pattern unit can be obtained from the substrate by the data selection unit 21. An optical image or an electron microscope (SEM) image obtained directly within the predetermined area.

In this embodiment, the substrate is a semiconductor substrate (wafer) as an example, the process pattern unit is formed on the semiconductor substrate after a patterning process, and the pattern design data is a mask pattern suitable for the GDS system format, and the data pattern unit is a preset data pattern stored in the pattern design data as an example for illustration, but not limited thereto. For example, when the substrate is a semiconductor substrate, the data pattern unit may be a preset data pattern stored in the pattern design data as mentioned above, or may be based on a preset pattern stored in the pattern design data. The data pattern is formed on the mask pattern of the glass substrate after a patterning process; in addition, when the substrate is a glass substrate for forming a mask pattern, the process pattern unit can be based on the pattern design data stored in the pattern The preset data pattern is formed on the mask pattern of the glass substrate through a patterning process, and the data pattern unit is the preset data pattern stored in the pattern design data.

The positioning unit 22 is used to select at least two of the process patterns as the positioning process pattern, so as to generate at least one process pattern connection line obtained by connecting the center points of the at least two positioning process patterns, and between these The data pattern obtains at least one data pattern connection corresponding to the process pattern connection, overlaps the process pattern unit and the data pattern unit, and adjusts at least one of the process pattern unit and the data pattern unit to make each Two ends of the corresponding at least one process pattern connection line and the at least one data pattern connection line coincide with each other to obtain a plurality of alignment patterns, which , each alignment pattern is composed of a process pattern and a data pattern corresponding to each other.

The calculation unit 23 is used for calculating the difference between the process pattern and the data pattern corresponding to any one of the alignment patterns.

The warning unit 24 can be used to send a warning signal to the outside when the detection result exceeds an allowable preset value.

The first embodiment of implementing the mask pattern calibration method of the present invention using the aforementioned pattern generation system 200 will be described as follows.

Referring to FIGS. 1-4 , a first embodiment of the pattern detection method includes a selection step 31 , a positioning step 32 , an error calculation step 33 , and a warning step 34 .

The selection step 31 is to select a process pattern unit 4 (shown by a solid line) formed in a predetermined area 40 of a substrate (not shown) and having a plurality of process patterns 41 after the patterning process, and selected from a The pattern design data obtains a data pattern unit 5 (indicated by dotted lines) corresponding to the process pattern unit 4 of the predetermined area 40 , and the data pattern unit 5 has a plurality of data patterns 51 corresponding to the process patterns 41 .

In detail, taking the base material as a semiconductor base material, the process pattern unit 4 is illustrated as an example of a pattern formed on the semiconductor base material during the same patterning process. The selection step 31 is to use the data selection unit 21 to select the The process patterns 41 are two of the process patterns separated along a first direction X and a second direction Y of the semiconductor substrate respectively 41, as a first positioning process pattern 411 and a second positioning process pattern 412. A data pattern unit 5 corresponding to the data pattern unit 4 is obtained from the pattern design data, and the data pattern unit 5 has the first positioning process patterns 411 and the second positioning process patterns 412 respectively. A positioning data pattern 511 and a second positioning data pattern 512 .

Wherein, the first direction X and the second direction Y may be parallel to each other or intersect at an angle. The process patterns 41 can be formed on the semiconductor substrate by the same or different processes, and the process patterns 41 can be isolated or low-density (Isolate) patterns, high-density circuit patterns or low-density circuit patterns with the same pitch, all Mirror symmetrical pattern, horizontal symmetrical pattern or vertical symmetrical pattern. The pattern design data is the data pattern unit 5 originally used to draw the mask to generate the process pattern unit 4 .

In some embodiments, the first direction X and the second direction Y are orthogonal to each other, and the intersection point is a common pattern. Through the simultaneous positioning of the first direction X and the second direction Y, which are orthogonal to each other, the best two-dimensional pattern alignment effect can be obtained. In this embodiment, the selecting step 31 is to select the process pattern 41 located at the outermost periphery of the process pattern unit 4, and share one of the process patterns as the first positioning process patterns 411 and the second positioning process patterns 412 , and the first positioning process patterns 411 and the second positioning process patterns 412 each include an isolated pattern as an example for illustration, but it is not limited to this in actual implementation.

The positioning step 32 is to generate at least two lines by the process patterns 41 The process pattern connection obtained by connecting the central points of any two process patterns 41, and the data pattern connection corresponding to the process pattern connection obtained in the data patterns 51, and the process pattern unit 4 and the process pattern unit 4 The data pattern units 5 are overlapped and adjusted to make the two ends of the corresponding process pattern lines and the data pattern lines coincide with each other, so as to obtain an alignment pattern unit 6 with a plurality of alignment patterns 61, wherein , each alignment pattern 61 is composed of process patterns 41 and data patterns 51 correspondingly aligned with each other.

In detail, the positioning step 32 uses the positioning unit 22 to respectively obtain the first positioning process patterns 411, the second positioning process patterns 412, the first positioning data patterns 511, and the second positioning data The connection lines of the center points of the pattern 512 are respectively obtained a first process pattern connection line, a second process pattern connection line, a first data pattern connection line, and a second data pattern connection line. Then the process pattern unit 4 and the data pattern unit 5 are overlapped, and the ratio of any one of the process pattern unit 4 and the data pattern unit 5 is adjusted with equal magnification to make the corresponding first process The two ends of the pattern connection line and the first data pattern connection line, and the corresponding second process pattern connection line and the second data pattern connection line overlap each other, so as to obtain the alignment pattern unit 6 as shown in FIG. 3 . Wherein, the alignment pattern unit 6 has a plurality of alignment patterns 61 formed by aligning the process patterns 41 in the process pattern unit 4 and the data patterns 51 in the data pattern unit 5 .

It should be noted that the first positioning process pattern 411 and the second process pattern 412 can be located at the outermost periphery of the process pattern unit 4, which is beneficial to the subsequent formation of the pair of process patterns. When the bit pattern unit 6 is used, the range of the bit pattern unit 6 can cover most of the process patterns 41 . In this embodiment of the present invention, the first positioning process pattern bits 411 are located at the outermost periphery of the process pattern unit 4 for illustration.

With reference to FIG. 5 , in some embodiments, the positioning step 32 can be as mentioned above, through the process patterns 41 to generate at least two process pattern connection lines obtained by connecting the center points of any two process patterns 41, It is also possible to generate a process pattern connection line with an acute angle between the center points of any two process patterns 41 and a horizontal line through the process patterns 41 (L1 in Figure 5), that is, the process pattern When the connection line L1 is a non-parallel or vertical straight line, a single process pattern connection line can be used for positioning.

Continuing to refer to FIG. 5, when the first process patterns 411 and the second process patterns 412 are respectively located on opposite sides and are composed of a plurality of lines with the same pitch (line), A plurality of process pattern connection lines L2 as shown in FIG. 5 can be obtained by selecting the center position of at least one line among the circuit patterns corresponding to each other for connection. Alternatively, a plurality of process pattern lines L3 can also be obtained by extending from the center points of one or more lines of the first process patterns 411 and the second process patterns 412 respectively.

In addition, in some embodiments, when the first positioning process patterns 411 and the second positioning process patterns 412 are isolated (isolated or low-density) patterns, the distance d between the adjacent process patterns 41 is not less than 250nm.

The error calculation step 33 can calculate any one of the alignment pattern units 6 The difference between the process pattern 41 of the alignment pattern 61 and the corresponding data pattern 51 is used to obtain a detection result.

Specifically, the error calculation step 33 is to use the calculation unit 23 to select at least any one of the alignment patterns 61, and calculate the process pattern 41 and the corresponding data pattern 51 of the at least any alignment pattern 61. difference and produce a test result.

Finally, the warning step 34 is executed, and when the detection result exceeds an allowable preset value, a warning signal is sent.

The allowable default value can be the allowable value of the process error, or a allowable range value defined by the user. The warning signal can be sound, video, text, etc., which can be used to remind the user. There is no special limit. It should be noted that the warning step 34 may not be executed according to requirements.

Referring to FIG. 6, it should be noted that, compared with the conventional method of comparing the process pattern with the data pattern alone, and then performing the correction of the data pattern of the pattern design data, although this method can compare the process pattern 41 The critical dimension (CD, critical dimension) error between the data pattern 51, however, cannot know the exact relative positional relationship between the process pattern 41 and the data pattern 51 (as shown in dotted line and imaginary line in Figure 6), that is The edge placement error (EPE) cannot be confirmed. Therefore, although the conventional correction method can improve the critical dimension (CD, critical dimension) error of the process pattern, it cannot improve the edge placement error of the process pattern at the same time. The difference is the offset error of the edge position. Therefore, the correction method in this case can not only correct the edge error of the pattern, but also can further adjust and correct the edge position of the pattern, so as to further improve the accuracy of the correction, and the corrected manufacturing process through the mask pattern correction method of the present invention The pattern can be more precise, so the alignment accuracy between each laminated layer can also be improved to effectively reduce the overlay error between the laminated layers.

In addition, it should be further explained that after the adjustment of the edge position between the graphics obtained after the alignment, the edge offset picture along a predetermined direction (as shown in FIG. 6 along the first direction X) can be obtained first through the alignment. Prime value E. At this time, the unit can be obtained through the preset spacing value between two positioning data patterns 511 adjacent to the data pattern unit 5 along the predetermined direction (first direction X) and the pixel value of the data pattern unit. Pixel size preset value, and then multiply the edge offset pixel value E by the unit pixel size value, the edge offset error size of the two corresponding patterns in the alignment pattern 61 can be correspondingly obtained value, and size correction can be performed on the data pattern unit 5 . The aforementioned calculation of the size value of the edge offset error is not limited to a single direction, and can be adjusted and calculated according to the alignment of the alignment pattern 61 in different directions.

Because the process pattern unit 4 is a photomask pattern drawn on the photomask selected in the current patterning process according to the pattern design data, and then a lithographic pattern formed on the semiconductor substrate through the patterning process. In the patterning process, based on the optical proximity effect (Optical Proximity effect), the produced process patterns 41 are prone to appear such as corner rounding, shortened line length, or Changes in the spacing between the patterns, etc., cause differences in shape and distance between the process patterns 41 and the data patterns 51 . Therefore, the present invention adjusts the magnification of any one of the data pattern unit 5 and the process pattern unit 4 by expanding or shrinking at an equal magnification, so that the lines connecting their isocenter points coincide with each other, and the gap between the two patterns can be penetrated. alignment, so that the corresponding process patterns 41 and data patterns 51 in each alignment pattern 61 can have a two-dimensional alignment effect, so as to obtain more accurate detection results. Therefore, the original pattern (that is, the data pattern unit 5 ) can be calibrated subsequently through the detection result to generate a corrected data pattern that can be used in the subsequent patterning process to improve the accuracy of the process pattern.

7 and 8, a second embodiment of the pattern detection method of the semiconductor manufacturing process of the present invention is to further correct the data pattern unit 5 after the error detection of the first embodiment to generate the corrected data pattern unit , resulting in a mask.

The pattern detection method of the second embodiment is performed using a pattern generation system 201 as shown in FIG. It includes a correction unit 25 , an image data generation unit 26 , and a mask drawing unit 27 .

Wherein, the correction unit 25 is used for performing back correction on the data pattern unit 5 through the detection result, and the image data generation unit 26 can generate a mask pattern for drawing according to the back correction data pattern unit 5 The correction data pattern unit of . The mask rendering unit 27 can perform mask rendering according to the correction data pattern unit to generate a mask.

When the aforementioned pattern generation system 201 is to be used to perform mask drawing according to the correction data pattern unit to generate a mask, after performing the aforementioned selecting step 31, the positioning step 32, and the error calculating step 33, then A pattern correction step 35 and a mask drawing step 36 are performed.

The pattern correction step 35 is to carry out back correction on the data pattern unit 5 through the detection result of the error calculation step 33 to generate a corrected data pattern unit for correcting the mask pattern.

The mask rendering step 36 is to perform mask rendering according to the correction data pattern unit to generate a mask.

Referring to Figures 3 and 4, in this embodiment, the data pattern unit 5 is the mask pattern drawn on the mask selected in the current patterning process according to the pattern design data, and the process pattern unit 4 is The lithography pattern formed on the semiconductor substrate by the patterning process of the mask pattern is used as an example for illustration. The pattern correction step 35 is to use the correction unit 25 to select at least any one of the alignment patterns 61, calculate the difference between the process pattern 41 and the corresponding data pattern 51 of the at least any alignment pattern 61, and then According to the calculation result, the data pattern unit 5 is compensated and corrected by means of optical proximity correction, and then the image data generation unit 26 is used to generate a new mask pattern for drawing according to the compensated and corrected data pattern unit. Correcting the data pattern unit, the mask drawing step 35 uses the mask drawing unit 27 to perform mask drawing according to the correction data pattern unit to generate a mask.

Using the two-dimensional alignment of the data pattern unit 5 and the process pattern unit 4 actually formed on the semiconductor substrate, and then calculating the difference between the aligned data patterns 51 and the process patterns 41 , and then use the calculation results to correct the data pattern unit 5 stored in the pattern design data, and finally use the corrected correction data pattern unit to perform mask drawing to generate a mask, which can improve the subsequent generation. The accuracy of the process pattern.

In addition, it should be further explained that the pattern detection method of the present invention can use the process pattern unit 4 formed on the semiconductor substrate and the pattern design data stored in the pattern design data as the first embodiment and the second embodiment described above. In addition to comparing and correcting the data pattern unit 5, it is also possible to use the process pattern unit 4 formed on the semiconductor substrate and the preset data pattern stored in the pattern design data to be formed on the semiconductor substrate after a patterning process. The mask pattern of the glass substrate (this is equivalent to the data pattern unit 5) is compared and corrected, or the preset data pattern stored in the pattern design data is formed on the glass substrate after a patterning process The same detection effect can also be obtained by comparing and correcting the mask pattern (which corresponds to the process pattern unit 4 ) with the preset data pattern unit 5 stored in the pattern design data.

Furthermore, it is also possible to target masks formed by different batches or provided by different manufacturers but having the same preset pattern (at this time, the preset patterns formed on different masks can be regarded as the process pattern unit 4 and the data respectively. The pattern unit 5) compares or executes the same preset data pattern in different times to form patterns on different semiconductor substrates (At this time, the patterns formed on different semiconductor substrates can be regarded as the process pattern unit 4 and the data pattern unit 5) for comparison, so that by using one of the patterns as a comparison standard, through comparison As a result, the pattern errors formed on different photomasks or different semiconductor substrates can be obtained, which can be used as a basis for subsequent correction.

Referring to FIG. 9 , a third embodiment of the pattern detection method of the semiconductor manufacturing process of the present invention is to detect the patterning process of the photomask through the comparison mark pattern unit 8 . Wherein, the comparison of the marking pattern unit 8 may be comparing the marking pattern units 8 formed on different substrates after the patterning process; or by comparing the preset marking pattern units stored in the pattern design data 8, and the marking pattern unit 8 formed on the substrate after a patterning process.

In detail, the pattern detection system used in the third embodiment of the pattern detection method of the present invention is substantially the same as the pattern detection system 200 described above, the difference is that the data selection unit 21 can also be used to select the data produced on a substrate 100 The predetermined area includes at least one marking pattern unit 8 having a plurality of marking patterns 81 . And use the pattern detection system 200 to perform the same steps as the first embodiment, the difference is that the selection step 31 of the third embodiment is to select at least one mark pattern unit 8 produced on different substrates and corresponding to each other The positioning step 32 is to select at least two of the marking patterns 81 of the marking pattern unit 8 as the alignment marking patterns 811, so as to align the marking pattern units 8 produced on different substrates to generate a plurality of alignment patterns , the error calculation step 33 is to calculate the corresponding marks in the alignment patterns after alignment The difference of the pattern 81 is used to obtain the detection result.

More specifically, the substrates 100 are glass substrates for producing a photomask pattern, and each substrate 100 has a light source located in a photomask protection film (pellicle) 100 for producing a photolithography pattern. A mask pattern (not shown), and a plurality of marking pattern units 8 that can be located inside or outside the photomask protection film. Wherein, each marking pattern unit 8 has a plurality of marking patterns 81, and these marking patterns 81 can be isolated patterns, low-density patterns, high-density line patterns with the same pitch, full mirror symmetrical patterns, horizontal symmetrical patterns or vertical patterns. The symmetrical pattern defines an inner pattern and an outer pattern surrounding the inner pattern. In some embodiments, the inner layer patterns correspond to the patterns within the exposure range of the mask pattern each time.

Taking one of the marking pattern units 81 as an example, the positioning step 32 is to select at least two marking patterns 81 of any marking pattern unit 81 on each substrate 100 as the positioning marking patterns 811, and these marking patterns 811 The positioning mark patterns 811 are selected from the outer pattern and at least include independent patterns or circuit patterns, and the positioning mark patterns 811 on different substrates 100 correspond to each other. In this way, through the same alignment method as the first embodiment, the positioning mark patterns 811 to be selected on different substrates 100 can be used for alignment to obtain a plurality of alignment marks 81 formed on different substrates 100. Afterwards, the alignment pattern formed together after the alignment can be calculated by using the error calculation step 33 to calculate the difference between the corresponding two mark patterns 81 in the alignment patterns to obtain a detection result, and the detection result can be used to monitor The process of the mask pattern to confirm that after the process The accuracy of the generated mask pattern. Preferably, the mark patterns 81 are located outside the mask pattern and are not used to generate lithography patterns, that is, the mark patterns 81 are formed on the substrate 100 outside the protective layer 101 (pellicle) that protects the mask pattern , without producing a corresponding lithographic pattern on the semiconductor substrate after the patterning process.

To sum up, the pattern detection method of the present invention is to align the data pattern unit 5 and the process pattern unit 4 first and then compare the difference, so that the difference between the data pattern unit 5 and the process pattern unit 4 can be measured. The shape and the detection result of the two-dimensional error, and the data pattern unit 5 can be compensated and corrected according to the detection result, so as to obtain the corrected data pattern unit, and the edge error and position of the process pattern can be corrected at the same time, further improving The accuracy of correction, so can really reach the purpose of the present invention.

But the above-mentioned ones are only embodiments of the present invention, and should not limit the scope of the present invention. All simple equivalent changes and modifications made according to the patent scope of the present invention and the content of the patent specification are still within the scope of the present invention. Within the scope covered by the patent of the present invention.

31 Selection steps 32 Positioning steps 33 Error Calculation Steps 34 Warning steps

Claims (15)

A pattern detection method for a semiconductor manufacturing process, comprising: A selection step, selecting a process pattern unit based on a pattern design data and formed in a predetermined area of a substrate after a patterning process and having a plurality of process patterns, and obtaining from the pattern design data, having the same A data pattern unit corresponding to the process pattern unit in the predetermined area, and the data pattern unit has a plurality of data patterns corresponding to the process patterns; A positioning step, selecting at least two of the process patterns as positioning process patterns to generate at least one process pattern connection line obtained by connecting the center points of the at least two positioning process patterns, and in the data patterns Obtain at least one data pattern connection corresponding to the at least one process pattern connection, overlap the process pattern unit and the data pattern unit, and adjust at least one of the process pattern unit and the data pattern unit to make each corresponding The two ends of the at least one process pattern connection line and the at least one data pattern connection line coincide with each other to obtain a plurality of alignment patterns, wherein each alignment pattern is composed of process patterns and data patterns corresponding to each other ;and An error calculation step, calculating the difference between the process pattern of any one of the alignment patterns and the corresponding data pattern, so as to obtain a detection result. The pattern detection method as described in Claim 1, further comprising a pattern correction step implemented after the error calculation step, through which the data pattern unit is compensated and corrected through the detection result to generate a pattern used to correct the mask pattern Calibration data pattern unit. The pattern detection method as described in Claim 1, wherein the positioning process patterns are corresponding to each other and have a line pattern composed of a plurality of lines with the same pitch, and the connecting lines of the center points of the process patterns are corresponding to each other The line connecting the center points of one of the lines in . The pattern detection method according to claim 1, wherein the positioning process patterns are formed in the same patterning process. The pattern detection method as claimed in claim 1, wherein the positioning process patterns are located at the outermost periphery of the process patterns. The pattern detection method according to claim 1, wherein the positioning process patterns can be isolated patterns, low-density patterns, high-density line patterns with the same pitch, full mirror-symmetrical patterns, horizontally symmetrical patterns or vertically symmetrical patterns , and can be the same or different. A pattern detection method for a semiconductor manufacturing process, comprising: A selection step, selecting at least one marking pattern unit produced on different substrates and corresponding to each other, wherein the substrate is used to generate a mask pattern, the at least one marking pattern unit has a plurality of marking patterns, and the The isomark pattern is selected from isolated patterns, low-density patterns, high-density line patterns with the same pitch, fully mirror-symmetrical patterns, horizontally-symmetrical patterns or vertically-symmetrical patterns; A positioning step, selecting at least two marking patterns of the at least one marking pattern unit on each substrate as positioning marking patterns, and the positioning marking patterns on different substrates correspond to each other, so as to be respectively in the The base material generates at least one mark pattern connection line obtained by connecting the center points of the at least two positioning mark patterns, overlapping the mark pattern units of the two base materials, and adjusting at least one of the two mark pattern units Or to make the two ends of the corresponding at least one marking pattern line coincide with each other to obtain a plurality of alignment patterns, wherein each alignment pattern is a marking pattern formed on a different substrate but corresponding to each other constitute; and An error calculation step, calculating the difference between the corresponding mark patterns in the alignment patterns to obtain a detection result. The pattern inspection method as claimed in claim 7, wherein the at least one mark pattern unit is located outside the mask pattern and is not used to generate the lithography pattern. The pattern detection method as claimed in item 7, wherein the at least one mark pattern unit has an inner layer pattern and an outer layer pattern surrounding the inner layer pattern, and the positioning mark patterns are selected from the outer layer pattern and can be isolated from each other patterns, low-density patterns, high-density circuit patterns with the same pitch, fully mirror-symmetrical patterns, horizontally-symmetrical patterns, or vertically-symmetrical patterns, and the inner layer pattern and the mask pattern can be the same or different. The pattern detection method as claimed in claim 1 or 7, further includes a warning step implemented after the error calculation step, and when the detection result exceeds an allowable preset value, a warning signal is issued. The pattern detection method as described in claim 1 or 7, wherein the error calculation step is calculated by the preset distance value between two positioning data patterns separated along a predetermined direction and the pixel value of the data pattern unit The predetermined value of the unit pixel size, and then use the predetermined value of the unit pixel size to obtain the edge offset error size value of two corresponding patterns in the alignment pattern. A pattern detection system for a semiconductor manufacturing process, comprising: a data selection unit, used to select a process pattern unit based on a pattern design data and formed in a predetermined area of a substrate after a patterning process and having a plurality of process patterns, and obtain from the pattern design data, There is a data pattern unit corresponding to the process pattern unit of the predetermined area, and the data pattern unit has a plurality of data patterns corresponding to the process patterns; a positioning unit, for selecting at least two of the process patterns as positioning process patterns to generate at least one process pattern connection line obtained by connecting the center points of the at least two positioning process patterns; The data pattern obtains at least one data pattern connection corresponding to the process pattern connection, overlaps the process pattern unit and the data pattern unit, and adjusts at least one of the process pattern unit and the data pattern unit to make each The two ends of the corresponding at least one process pattern connection line and the at least one data pattern connection line overlap each other to obtain a plurality of alignment patterns, wherein each alignment pattern is composed of a process pattern and a data pattern corresponding to each other. constitute; and A calculation unit is used for calculating the difference between two corresponding patterns in any one of the alignment patterns to generate a detection result. The pattern detection system as described in claim 12, further comprising a correction unit, an image data generation unit, and a mask drawing unit, the correction unit is used to perform back-up correction on the data pattern unit through the detection result, The image data generation unit can generate a correction data pattern unit for drawing a mask pattern according to the back-corrected data pattern unit, and the mask drawing unit can perform mask drawing according to the correction data pattern unit to generate a light cover. The pattern detection system according to claim 12 further includes a warning unit, which can send a warning signal to the outside when the detection result exceeds an allowable preset value. The pattern detection system as claimed in claim 12, wherein the data selection unit is also used to select the predetermined area generated in the substrate, and includes at least one marking pattern unit with a plurality of marking patterns, and the marking patterns An inner layer pattern and an outer layer pattern surrounding the inner layer pattern are defined, and the positioning unit is also used to select at least two marking patterns located on the outer layer pattern as positioning marking patterns for positioning detection, and can use these The central point of the positioning mark pattern generates a mark pattern connection line for positioning, wherein the positioning mark patterns can be isolated patterns, low-density patterns, high-density line patterns with the same pitch, full mirror symmetrical patterns, horizontal symmetrical patterns or vertically symmetrical patterns.

Images