JP2008058428A - Photomask, device and method of making photomask, and method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly accurate photomask, and to provide a highly reliable semiconductor device. <P>SOLUTION: A device of making the photomask for exposing to overlap a first transfer region and a second transfer region to one region of a photoresist film on the principal plane of a substrate is provided with: a covering rate calculation part of an exposure region for generating the result of calculation by calculating the covering rate of a device pattern in the first transfer region; a dummy mask pattern determination part of a shading region for determining a dummy mask pattern formed on the second transfer region based on a calculation result generated by the exposure region covering rate calculation part; a dummy mask making part for making the dummy mask by combining data of the dummy mask pattern formed on the second transfer region and layout data of the first transfer region based on the determination content of the dummy mask pattern determination part of the shading region; and a data output part for outputting the data of the made dummy mask. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

The present invention relates to a photomask used in a semiconductor device manufacturing process, and more particularly to a photomask used in a multiple exposure technique, a photomask manufacturing apparatus and manufacturing method, and a semiconductor device manufacturing method using a photomask.

In a general semiconductor device manufacturing process, a photomask or reticle (hereinafter referred to as “mask”) on which a device pattern of a semiconductor integrated circuit is formed is used on a silicon wafer (hereinafter referred to as “wafer”). The device pattern is transferred to. With recent technological advancement, device patterns have become fine patterns. However, the resolution performance of the exposure equipment (aligner) may not be sufficient to transfer these fine device patterns onto the wafer. is there. In such a case, a method is used in which a plurality of masks are created by dividing the device pattern formation region into certain areas, these masks are transferred onto the wafer, and the divided device patterns are synthesized on the wafer. May be.
JP 2003-209049 A JP 2004-69829 A

In such a multiple exposure technique, it is general to adopt a method of uniformly shielding light except in an area to be exposed. This is because the resist molecular structure is destroyed when light is applied to a photoresist (hereinafter referred to as “resist”), and the resist characteristic is not changed regardless of how many times light is applied thereafter. For this reason, in the mask produced by the multiple exposure technique, there is a significant difference in coverage between the exposure area and the light shielding area. Here, the coverage means the ratio of the area occupied by a region (transmission part) through which exposure light can be transmitted among the entire area of the device pattern formation region.

If there is a significant difference in coverage between the exposure area and the light shielding area, the device pattern intended by the designer was actually formed on the mask at the part where the exposure area and the light shielding area were close when the mask was created. There may be a difference in dimensions with the device pattern. When a dimensional difference occurs in the device pattern on the mask, various fine semiconductor elements and the like incorporated in the semiconductor device are not formed with a desired accuracy, so that the quality of the semiconductor device deteriorates and the yield decreases.

Therefore, the present invention is formed on the mask by forming a dummy pattern in the light shielding area and adjusting the coverage difference between the exposure area and the light shielding area when creating a mask using the multiple exposure technique. It is an object of the present invention to provide a mask that prevents a dimensional difference from occurring in a device pattern to be generated and has an improved dimensional accuracy, and a mask creation apparatus and method that can create such a mask. In addition, the present invention provides a method for manufacturing a semiconductor device that uses such a mask to form a fine semiconductor element or the like with high accuracy to realize a highly reliable and high yield semiconductor collector. With the goal.

According to the mask making apparatus according to one embodiment of the present invention, the first transfer region and the second transfer region are exposed to overlap one region of the photoresist film on the main surface of the substrate. The device for generating a photomask of the first aspect includes an exposure area coverage calculation unit that calculates a device pattern coverage in the first transfer area and generates the result, and the exposure area coverage calculation unit generates the result. Based on the determination result of the light shielding region dummy pattern determining unit for determining the mask dummy pattern formed in the second transfer region based on the calculation result, and the contents determined by the dummy mask pattern determining unit for the light shielding region. A dummy mask creating unit that creates a dummy mask by synthesizing the dummy pattern data formed in the transfer area and the layout data of the first transfer area; and A data output unit for outputting data Masuku, photomask creating apparatus having a are provided.

According to an embodiment of the present invention, it is possible to create a highly accurate mask when creating a mask using a multiple exposure technique. In addition, by manufacturing a semiconductor device using such a high-accuracy mask, a semiconductor device with high reliability and high yield can be realized.

When creating the mask, if the entire device pattern formation region can be formed on a single mask without including a fine device pattern, the coverage should be adjusted so that the entire device pattern formation region is within a certain range. Thus, it is possible to prevent the occurrence of dimensional differences. The adjustment of the coverage is desirably matched to the coverage of the memory cell region having a fine pattern.

However, if there is a significant disparity in coverage locally, such as when there is a significant disparity in coverage between the device pattern formation region and the outer periphery where the device pattern is not formed, the end portion of the device pattern formation region There is a possibility that a difference occurs in the dimensions and the desired dimensional accuracy cannot be obtained. Accordingly, a dummy mask pattern 1200 as shown in FIGS. 18 and 19 is formed on the outer peripheral portion 1300 of the device pattern formation region 1100 to reduce the coverage difference and prevent the dimensional difference at the terminal portion of the device pattern formation region 1100. The technique to do is used (patent document 2). As described above, when the entire device pattern formation region is formed on one mask, a dimensional difference can be prevented by using the above-described technique or the like.

With the advancement of technology in recent years, fine patterns are also included in device patterns, but at the time of development of advanced semiconductor device products, manufacturing apparatuses such as exposure apparatuses are often in the development stage. In many cases, it is difficult to obtain an exposure apparatus having a resolution sufficient to cope with a fine pattern. Therefore, in order to cover the lack of resolution performance of the exposure apparatus, a multiple exposure technique may be used for a semiconductor device including a fine pattern.

In this multiple exposure technology, for example, a device pattern is divided into a memory cell region having fine dimensions and a peripheral circuit region having relatively relaxed dimensions to create a plurality of masks, and these masks are formed on these masks. A general method is to sequentially transfer the divided patterns onto the wafer and synthesize the divided device patterns on the wafer.

The case of so-called double exposure in which the device pattern is divided into two masks for exposure will be described with reference to FIGS. FIG. 20 is an enlarged plan view showing a part of the mask surface when the memory cell region is exposed. FIG. 21 is an enlarged plan view showing a part of the mask surface when the peripheral circuit area is exposed. In FIG. 20, the memory cell region 100 is exposed and the device pattern of the memory cell region 100 is formed on the mask in the device pattern formation region. At this time, the peripheral circuit region 300 is uniformly shielded from light. Yes. In FIG. 21, the peripheral circuit region 300 is exposed and the device pattern of the peripheral circuit region 300 is formed on the mask in the device pattern formation region. At this time, the memory cell region 100 is uniformly shielded from light. Has been. As described above, the reason why the portions other than the exposure region are uniformly shielded from light is because the characteristics of the resist are taken into consideration. Then, the two masks created in this way are sequentially exposed to the wafer, and the divided device patterns are synthesized on the wafer. According to such a multiple exposure technique, the accuracy of a device pattern formed on a mask can be maintained even for a semiconductor device including a fine device pattern. However, the mask created using the multiple exposure technique has a significant difference in coverage between the exposure area and the light-shielding area, so that there is a problem that a dimensional difference is likely to occur in a portion where both areas are close to each other. Recently, the inventors have found.

Therefore, the present inventors have formed a dummy pattern in the light shielding region and adjusted the coverage difference between the exposure region and the light shielding region, thereby allowing the mask created using the multiple exposure technique to have a coverage difference. It has been found that it is possible to prevent the occurrence of dimensional differences.

Hereinafter, a mask creation apparatus and a creation method according to an embodiment of the present invention will be described in detail with reference to the drawings. In the following embodiments, an example of a mask according to an embodiment of the present invention, a mask creation apparatus and creation method, and a method for manufacturing a semiconductor device is shown. Creation of a mask according to an embodiment of the present invention The apparatus and the creation method are not limited to those embodiments.

Further, in the following description, a case where a device pattern is transferred to a wafer by combining two masks (double exposure) in the multiple exposure technique will be described as an example, but the mask according to an embodiment of the present invention will be described. Needless to say, the creation apparatus and the creation method are also effective when a device pattern is transferred to a wafer by combining three or more masks. The present invention is also effective when the resist characteristics change.

(Embodiment 1)
The first embodiment will be described with reference to FIGS. FIG. 1 is a block diagram showing a configuration of a mask creating apparatus 1 according to the first embodiment. FIG. 2 is a flowchart of a mask creation method according to the first embodiment. FIG. 3 is a plan view schematically showing the positional relationship of each region constituting a part of the mask in the plane according to the first embodiment. FIG. 4 is an enlarged plan view showing a part of the mask surface when the peripheral circuit area is exposed. FIG. 5 is an enlarged plan view showing a part of the mask surface when the memory cell region is exposed. Although the device pattern of the light shielding region is not originally formed in the mask surface, in FIG. 4 and FIG. 5, the device pattern is also shown for the light shielding region for convenience of explanation.

A mask creation apparatus 1 according to an embodiment of the present invention shown in FIG. 1 is based on mask layout data 10 created by a designer and exposure area information 20 of layout data 10 determined by the designer. Based on the calculation result by the exposure area coverage calculation unit 30 for calculating the exposure area coverage and the exposure area coverage calculation unit 30, the size, shape, arrangement, etc. of the dummy mask pattern of the light shielding area are determined. Based on the determination contents of the dummy mask pattern determination unit 40 and the light shielding region dummy mask pattern determination unit 40, a dummy mask is created by synthesizing the dummy mask pattern of the light shielding region with the layout data of the exposure region extracted from the layout data 10 And a data output unit 60 that outputs data of the created dummy mask. The configuration and data flow of the mask creating apparatus 1 according to the present invention are not limited to those shown in FIG. For example, in the first embodiment, the designer determines the exposure area and gives the information 20 to the mask creating apparatus 1. Such an operation is performed in the mask creating apparatus 1, and It is also possible to configure that the operation is performed by the exposure area determination unit 20.

Further, a part of the mask surface according to the embodiment of the present invention shown in FIG. 3 includes a memory cell region 100 and a peripheral circuit region 300. The memory cell area 100 includes a memory cell array 200 and a dummy device pattern 500. The peripheral circuit region 300 is composed of a transistor group 400 constituting the peripheral circuit and an open region 600 in which no device pattern is formed.

Next, the operation flow of the mask creating apparatus 1 according to one embodiment of the present invention will be described in detail with reference to the drawings.

As shown in FIG. 2, the designer first creates mask layout data. (Mask layout data 10, step S101). The layout data 10 describes various types of information for forming a device pattern on a mask, specifically, information on the size, shape, arrangement, etc. of the device pattern.

For example, this will be described with reference to FIG. 3. In the first embodiment, as shown in FIG. 3, the designer forms a memory cell region 100 in a part of the mask surface and peripheral circuit formation around the memory cell region 100. The device pattern layout data including the area 300 is created. In the layout data according to the first embodiment, a dummy device pattern 610 is formed in the open region 600 as shown in FIG. Here, the dummy device pattern refers to a pattern that is not used for creating an actual semiconductor device on a substrate among the device patterns formed on the mask.

The dummy device pattern 610 is formed in order to prevent dishing that occurs in a CMP (Chemical Mechanical Polishing) process. This CMP process refers to a process used in semiconductor manufacturing for planarizing a wafer or removing excess material from a wafer surface. In addition, dishing refers to a phenomenon in which a recess is formed during polishing with a pad in a CMP process. The dishing extremely deteriorates the flatness of the wafer and causes a depth of focus problem in the photolithography process.

Next, the designer determines an area in which a device pattern is to be formed on the mask original plate, that is, an exposure area, in the designed layout data 10, and gives this information 20 to the mask creating apparatus 1 (step S102).

For example, in FIG. 4, the designer determines that the peripheral circuit region 300 is an exposure region and the memory cell region 100 is a light shielding region, and provides this data to the mask creating apparatus 1. Similarly, in FIG. 5, the designer also determines that the memory cell region 100 is an exposure region and the peripheral circuit region 300 is a light-shielding region, and gives this data to the mask creating apparatus 1.

Next, the exposure area coverage calculation unit 30 calculates the exposure area coverage based on the exposure area information 20 determined in step S102 (step S103). Here, the coverage of the exposure region refers to the ratio of the area occupied by the region (transmission part) through which the exposure light can be transmitted out of the entire area of the exposure region.

For example, in the case of FIG. 4, since the peripheral circuit region 300 is exposed, the coverage calculation unit 30 of the exposure region has a region (transmission portion) through which the exposure light can be transmitted out of the entire area of the peripheral circuit region 300. Calculate the percentage of area occupied. Specifically, a device pattern transmission portion that can be calculated based on the type and number of figure of the device pattern formed in the peripheral circuit region 300 with respect to the entire area of the peripheral circuit region 300 as an exposure region. It is calculated as a percentage of the area. Similar explanations apply to the case of FIG. In general, the coverage of the memory cell region 100 in which a device pattern with fine dimensions is formed is higher than that in the peripheral circuit region 300 in which a device pattern with relatively relaxed dimensions is formed.

Next, based on the exposure area coverage calculated by the exposure area coverage calculation unit 30, the light shielding area dummy mask pattern determination unit 40 determines that the coverage difference between the exposure area and the light shielding area is within a certain range. Then, the formation area and area of the mask dummy pattern formed in the light shielding area are determined (step S104). That is, when the dummy mask pattern is formed, the coverage of the exposure region remains unchanged, but the coverage of the light shielding region increases in proportion to the area of the dummy mask pattern. Therefore, the dummy mask pattern is formed so that the difference between the coverage of the exposure area and the coverage of the light shielding area is within a certain range. Here, the coverage of the light shielding region refers to the ratio of the area occupied by the exposure light, that is, the area occupied by the dummy mask pattern, out of the total area of the light shielding region.

This dummy mask pattern is formed on the device pattern in the light shielding region. The reason why the dummy mask pattern is formed on the device pattern in this way is to prevent the portion other than the device pattern from being exposed to change the resist and the mask from being created according to the layout data intended by the designer. It is.

Further, in the mask creation apparatus 1 according to the first embodiment, when creating a mask using the double exposure technique, the device pattern in the light shielding region is used regardless of whether it is a device pattern or a dummy device pattern. A certain amount of offset is provided, and the dummy mask pattern is formed inside the device pattern in the light shielding region. As a result, the coverage difference between the exposure area and the light shielding area is reduced, and a portion close to the device pattern in the light shielding area is exposed to change the resist so that the mask is not created according to the layout data intended by the designer. To prevent.

Next, the dummy mask creation unit 50 combines the layout data of the exposure region and the dummy mask pattern formed in the light shielding region based on the content determined by the dummy mask pattern determination unit 40 for the light shielding region, and creates a mask. Layout data is completed (step S105).

For example, in the case of FIG. 4, based on the calculation result of the exposure area coverage calculation unit 30, the light shielding area dummy mask pattern determination unit 40 determines that the coverage difference between the exposure area and the light shielding area is within a certain range. Thus, it is determined to form a dummy mask pattern 710 as shown in FIG. 4 in the memory cell region 100 that is a light shielding region. Specifically, a dummy mask pattern that can be calculated based on the type and number of figures of the dummy mask pattern 710 formed in the memory cell region 100 with respect to the entire area of the memory cell region 100 as the light shielding region. It is calculated as a ratio of the area of the 710 transmission part. Next, the dummy mask pattern creation unit 50 synthesizes the dummy mask pattern 710 in the light shielding area determined by the dummy mask pattern determination unit 40 and the layout data of the peripheral circuit area 300 as the exposure area, thereby completing the mask layout data. . The above description also applies to the case of FIG. In this way, two mask layout data are completed.

Next, the dummy mask creation unit 50 exposes the created two mask layout data to the mask master, respectively, thereby completing two dummy masks (step S106). For example, the layout data is formed on the mask original by the method described below. That is, first, an electron beam resist is applied to the mask original, and a pattern is drawn on the resist on the mask substrate using an electron beam drawing apparatus based on the mask layout data. Next, by developing the resist, a desired mask pattern, that is, a resist pattern is formed. Next, the mask original is etched using the obtained resist pattern as a mask to form a transmission part. Thus, a desired mask pattern composed of the device pattern and the dummy pattern is formed on the mask.

Next, the dummy mask creating unit 50 provides the data output unit 60 with the data of the two completed masks. The data output unit 60 is composed of a display device or a printer, and displays or prints out the completed mask on the display device, and outputs mask data (step S107).

Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described. A method for manufacturing a semiconductor device according to an embodiment of the present invention includes a lithography process for performing pattern transfer using the mask created according to Embodiment 1. As described above, a device pattern with improved dimensional accuracy is formed on the mask according to an embodiment of the present invention. Thereby, a fine device pattern can be transferred with high accuracy. As a result, various fine semiconductor elements incorporated in the semiconductor device can be formed with high accuracy based on the device pattern transferred with high accuracy. Therefore, according to this method for manufacturing a semiconductor device, it is possible to improve the reliability and yield of the semiconductor device by forming fine semiconductor elements and the like with high accuracy.

As described above, according to the mask creation apparatus and creation method according to an embodiment of the present invention, it is possible to create a highly accurate mask when creating a mask using the multiple exposure technique. . In addition, by manufacturing a semiconductor device using such a high-accuracy mask, a semiconductor device with high reliability and high yield can be realized.

(Embodiment 2)
In many cases, dishing by the CMP process occurs in an open region where a device pattern is not formed. On the other hand, when a wide and flat dummy device pattern having a certain area or more is formed in the open region, there is a concern about residues due to the CMP process. This residue causes a short circuit of the wiring and causes a failure of the semiconductor device. Therefore, in the second embodiment, a dummy pattern that does not require accuracy is formed in the light-shielding region on the mask during exposure of the exposure region, thereby preventing the occurrence of a defect due to the CMP process while preventing a difference in size. Also prevent.

The second embodiment will also be described with reference to FIGS. Since the second embodiment and the first embodiment are the same except for the operation in step S104, only the step S104 will be described in the second embodiment.

6 to 9 are enlarged plan views showing a part of the device pattern formation region according to the second embodiment. 6 and 9 are enlarged plan views showing a part of a device pattern formation region when the memory cell region 100 is an exposure region. FIGS. 7 and 8 are enlarged plan views showing a part of a device pattern formation region when the peripheral circuit region 300 is an exposure region. Although the device pattern of the light shielding region is not originally shown in the mask plane, in FIGS. 6 to 9, the device pattern is also shown for the light shielding region for convenience of explanation.

In the second embodiment, a pattern is formed on the wafer by combining any one of FIGS. 6 and 9 and any one of FIGS. 7 and 8. In the layout data according to the second embodiment, unlike the first embodiment, the dummy device pattern 610 is not formed in the open region 600.

Next, a mask and a mask creation method according to the second embodiment will be described. When the designer determines the memory cell region 100 as an exposure region, the dummy mask pattern determination unit 40 in the light shielding region has a dummy mask pattern 730 that does not require accuracy as shown in FIG. 6 in the peripheral circuit region 300 that is the light shielding region. Is determined (step S104). In this manner, by forming the dummy mask pattern 730 that does not require accuracy in the peripheral circuit region 300, a dimensional difference occurs in the device pattern formed on the mask by adjusting the coverage difference between the exposure region and the light shielding region. While preventing this, it is possible to prevent the occurrence of defects due to the CMP process.

On the other hand, in the second embodiment, an example of a mask when the peripheral circuit region 300 is an exposure region is as shown in FIGS.

In the second embodiment, since the dummy mask pattern 730 is formed on the mask when the memory cell region 100 is exposed, it is necessary to form the dummy mask pattern 730 as shown in FIG. 7 when the peripheral circuit region 300 is exposed. There may be no.

On the other hand, FIG. 8 shows a case where the dummy mask pattern 730 is formed so as to overlap the mask when the peripheral circuit region 300 is exposed. As described above, since the mask dummy pattern according to the second embodiment does not require accuracy, the mask dummy pattern can be formed using both a mask for exposing the memory cell region 100 and a mask for exposing the peripheral circuit region 300. It is.

Further, in the mask for exposing the memory cell region 100, the coverage is adjusted by adjusting the number of the dummy mask patterns 730 without using the method of forming all of the dummy mask patterns 730 as shown in FIG. Is also possible. Even when all of the dummy mask patterns 730 are formed, the coverage can be adjusted by adjusting the area of the dummy mask pattern 730. That is, for example, as in the dummy mask pattern 740 shown in FIG. 9, it is possible to adjust the coverage by providing a light shielding portion inside the dummy mask pattern 740.

By manufacturing a semiconductor device using a mask with improved dimensional accuracy in this way, it is possible to realize a semiconductor device with high reliability and high yield. A specific method for manufacturing the semiconductor device is the same as that in the first embodiment, and thus the description thereof is omitted in the second embodiment.

As described above, according to the mask creation apparatus and creation method according to an embodiment of the present invention, it is possible to create a highly accurate mask when creating a mask using the multiple exposure technique. . In addition, by manufacturing a semiconductor device using such a high-accuracy mask, a semiconductor device with high reliability and high yield can be realized.

(Embodiment 3)
In addition to the coverage difference in the entire device pattern formation region, there may be a dimensional difference due to a coverage difference between local regions. In particular, since the memory cell region 100 is required to have fine dimensions not only in the central portion but also in the peripheral portion, the difference in coverage between the central portion and the peripheral portion is within a certain range. It is necessary to adjust the coverage to prevent dimensional differences. Therefore, in the third embodiment, the coverage is adjusted between local regions to prevent the occurrence of a dimensional difference due to the coverage difference.

The third embodiment will also be described with reference to FIGS. Since the third embodiment and the first embodiment are the same except for the operation in step S104, only the step S104 will be described in the third embodiment.

10 to 13 are enlarged plan views showing a part of the memory cell region 100 according to the third embodiment and a region adjacent thereto.

In the third embodiment, the light-shielding region dummy mask pattern determining unit 40 is disposed outside the memory cell region 100 so that the coverage difference between the central portion and the peripheral portion of the memory cell region 100 is within a certain range. The dimensions, shape, arrangement, etc. of the dummy mask pattern 750 to be formed are determined (step S104).

In general, with regard to the resolution performance of an exposure apparatus, a technique for performing exposure while emphasizing parallel or vertical rather than oblique directions is progressing. Therefore, the device pattern may be more controllable when formed so as to be parallel or perpendicular to the device pattern of the memory cell region 100. Therefore, depending on the resolution performance of the exposure apparatus, as shown in FIGS. 10 and 11, a dummy mask pattern is formed in the light shielding region so as to be oriented perpendicularly or parallel to the device pattern of the memory cell region 100 as the exposure region. It may be desirable to form 750.

Here, the mask according to the third embodiment will be described in detail with reference to FIG. In FIG. 10, the width W of one unit of the memory cell array 200 and the width of one unit of the dummy device pattern 500 disposed on the side of the memory cell array 200 have a two-to-one relationship. The dummy mask pattern 750 is formed in the same direction as the wiring corresponding to one minimum line width of the memory cell array 200, and the width and interval (line and space) of the dummy mask pattern 750 are, for example, the memory cell array. It is formed so as to be 1 to 10 times as large as 200 main device patterns. By forming the dummy mask pattern 750 in this way, it becomes possible to improve the controllability of the dimensional accuracy of the device pattern in the memory cell region 100 that is the exposure region.

The coverage in the memory cell region 100 is unchanged, but when the dummy mask pattern 750 is formed, the coverage in the light shielding region increases. Therefore, the difference between the coverage in the range of the area of the predetermined device pattern in the peripheral portion of the memory cell region 100 and the area of the dummy mask pattern 750 and the coverage in the central portion of the memory cell region 100 is constant. A dummy mask pattern 750 is formed so as to be within the range. Specifically, the dummy mask pattern 750 is formed until the coverage of almost all local regions in the peripheral portion of the memory cell region 100 is substantially the same as the coverage of the central portion of the memory cell region 100. That is, the dummy mask pattern 750 is formed so that the coverage of the pattern including the memory cell region 100 and the dummy mask pattern 750 is substantially uniform in the memory cell region 100 that is the exposure region. As described above, it is desirable that the coverage of the memory cell region 100 and the coverage of the dummy mask pattern 750 are substantially the same, but depending on the process conditions, for example, constant values such as 0.95 or more and 1.05 or less. If it is in the range, it is possible to prevent the dimensional difference due to the coverage difference. Further, when forming the dummy mask pattern 750, it is formed at a constant interval, and the width of the dummy mask pattern 750 is set to be equal to or larger than the unit width W of the memory cell array 200, thereby controlling the dimensional accuracy of the device pattern in the memory cell region 100. It is desirable from the viewpoint of improving the performance.

As described above, the dummy mask pattern 750 is formed outside the memory cell region 100, and the coverage between the central portion and the peripheral portion of the memory cell region 100 is adjusted. It becomes possible to prevent the dimensional difference of the device pattern between the two. That is, in the pattern formation region within the exposure region in which the device pattern of the memory cell region 100 and the dummy mask pattern 750 are combined, the pattern dimensions are approximately uniform in any local region. At the same time, the dimensional accuracy of the entire memory cell region 100 is also improved.

Further, in the creation of a mask according to an embodiment of the present invention, it is possible to prevent a dimensional difference if the coverage rate difference between predetermined regions is within a certain range. The dummy mask pattern 750 can obtain the same effect even if the orientation, width, and interval (line and space) with respect to the device pattern of the memory cell region 100 are not regular. Therefore, as shown in FIGS. 12 to 13, even when the dummy mask pattern 750 is formed in an oblique direction with respect to the device pattern direction of the memory cell region 100, the dimensional difference can be prevented.

By manufacturing a semiconductor device using a mask with improved accuracy in this way, it is possible to realize a semiconductor device with high reliability and high yield. A specific method for manufacturing the semiconductor device is the same as that in the first embodiment, and thus the description thereof is omitted in the third embodiment.

As described above, according to the third embodiment, the disparity between the coverage of the region including the pattern where the coverage is constant and the high accuracy is required and the coverage of the memory cell region is within a certain range. By adjusting in this way, it is possible to create a highly accurate mask even for a semiconductor device in which the accuracy of the peripheral portion of the memory cell region is particularly required. Further, by using such a high-accuracy mask, a fine semiconductor element or the like can be formed with high accuracy, and high reliability and high yield of the semiconductor device can be realized.

(Embodiment 4)
In the first to third embodiments, when a dummy mask pattern having a large dimension value is formed at a position where a device pattern is formed with a dimension value equal to or greater than a certain value, depending on the area of the dummy mask pattern, the wafer is transferred. In this exposure, the dummy mask pattern may be transferred larger than a predetermined dimension value, resulting in a difference in dimension. Therefore, it may be necessary to individually correct the dimension value of the dummy mask pattern.

Therefore, in the fourth embodiment, a sub-resolution assist structure (Sub-Resolution Assist Feature, hereinafter referred to as “SRAF”) is used as a dummy pattern. Here, SRAF refers to a pattern that is formed on the mask but not on the wafer. According to the fourth embodiment, since the SRAF is formed with a constant dimension value, the dummy mask pattern can be always formed at a constant distance with respect to the edge of the device pattern in the light shielding region. When the wafer is exposed, the dummy mask pattern is transferred larger than a predetermined dimension value, and it is possible to prevent a difference in dimension. Further, by using SRAF, it is also possible to adjust the coverage ratio and prevent a dimensional difference even in a pattern region where it is difficult to adjust the coverage difference in the first to third embodiments.

The fourth embodiment will also be described with reference to FIGS. 1 and 2. In the fourth embodiment and the first embodiment, the other operations are the same except for the operation in step S104. Therefore, in the third embodiment, only step S104 will be described.

14 and 15 are plan views showing an enlarged part of a device pattern formation region according to the fourth embodiment. FIG. 14 is an enlarged plan view showing a part of a device pattern formation region when the memory cell region 100 is an exposure region. FIG. 15 is an enlarged plan view showing a part of a device pattern formation region when the peripheral circuit region 300 is an exposure region. Although the device pattern of the light shielding region is not originally shown in the mask plane, in FIGS. 14 and 15, the device pattern is also shown for the light shielding region for convenience of explanation.

In the fourth embodiment, the dummy mask pattern determining unit 40 for the light shielding area has a size, a shape, an arrangement, and the like of the dummy mask pattern using SRAF so that the coverage difference between the exposure area and the light shielding area is within a certain range. Is determined (step S104). For example, in FIG. 14, the memory cell region 100 is an exposure region, and a dummy mask pattern 760 using SRAF is formed over the entire device pattern of the peripheral circuit region 300 that is a light shielding region. In FIG. 15, the peripheral circuit region 300 is an exposure region, and a dummy mask pattern 770 using SRAF is formed on the entire device pattern of the memory cell region 100 which is a light shielding region. Thus, unlike the first to third embodiments, the dummy mask patterns 760 and 770 using SRAF are formed over the entire device pattern of the light shielding region, so that the dummy mask can be used even in a portion where the area of the transmissive portion is small. A pattern can be formed.

Then, by manufacturing a semiconductor device using a mask with improved accuracy in this way, it becomes possible to realize a semiconductor device with high reliability and high yield. A specific method for manufacturing a semiconductor device Since is the same as that of the first embodiment, the description thereof is omitted in the fourth embodiment. A device pattern can be formed on the wafer by combining the mask created according to the fourth embodiment and the mask created according to the first to third embodiments.

As described above, according to the mask creation apparatus and creation method according to an embodiment of the present invention, it is possible to create a highly accurate mask when creating a mask using the multiple exposure technique. . In addition, by manufacturing a semiconductor device using such a high-accuracy mask, a semiconductor device with high reliability and high yield can be realized.

(Embodiment 5)
In the fourth embodiment, the dummy mask patterns 760 and 770 using SRAF are formed on the device pattern in the light shielding region. However, in the fifth embodiment, in view of the fact that the SRAF is not transferred, FIG. As shown in FIG. 17, it is possible to form a dummy mask pattern using SRAF over the entire light shielding region on the mask. FIG. 16 shows an enlarged part of the mask surface in the case where the dummy mask pattern 780 using SRAF is formed on the entire peripheral circuit region 300 which is a light shielding region when the memory cell region 100 is exposed. It is a top view. FIG. 17 is an enlarged view of a part of the mask surface in the case where the dummy mask pattern 790 using SRAF is formed in the entire memory cell region 100 which is a light shielding region when the peripheral circuit region 300 is exposed. It is the shown top view. Thus, by forming dummy mask patterns 780 and 790 using SRAF over the entire light shielding region, unlike the first to third embodiments, a dummy mask pattern can be formed even in a portion where the area of the transmissive portion is small. Thus, the coverage can be adjusted. Since the remaining description is the same as that of the fourth embodiment, the description thereof is omitted in the fifth embodiment.

A device pattern can be formed on the wafer by combining the mask created according to the fifth embodiment and the mask created according to the first to third embodiments.

As described above, according to the mask creation apparatus and creation method according to an embodiment of the present invention, it is possible to create a highly accurate mask when creating a mask using the multiple exposure technique. . In addition, by manufacturing a semiconductor device using such a high-accuracy mask, a semiconductor device with high reliability and high yield can be realized.

According to an embodiment of the present invention, the dummy mask pattern formed in the second transfer region is formed on a device pattern or a dummy device pattern in the second transfer region. Is provided.

This makes it possible to create a highly accurate mask when creating a mask using the multiple exposure technique. In addition, by manufacturing a semiconductor device using such a high-accuracy mask, a semiconductor device with high reliability and high yield can be realized.

According to an embodiment of the present invention, the dummy mask pattern formed in the second transfer region includes a dummy mask pattern formation region and a predetermined region around the first transfer region. A photomask producing apparatus is provided in which the difference between the coverage of the combined region and the coverage of the central portion of the first transfer region is within a certain range.

This makes it possible to create a highly accurate mask when creating a mask using the multiple exposure technique. In addition, by manufacturing a semiconductor device using such a high-accuracy mask, a semiconductor device with high reliability and high yield can be realized.

According to an embodiment of the present invention, the dummy mask pattern formed in the second transfer region has a device pattern formed on the photomask, but no device pattern formed on the substrate. There is provided a photomask producing apparatus using a sub-resolution auxiliary structure (SRAF) having properties.

This makes it possible to adjust the coverage ratio and prevent dimensional differences even in pattern areas where it is difficult to adjust the coverage difference. Therefore, when creating a mask using multiple exposure technology, high accuracy is achieved. It is possible to create a mask. In addition, by manufacturing a semiconductor device using such a high-accuracy mask, a semiconductor device with high reliability and high yield can be realized.

According to an embodiment of the present invention, the dummy mask pattern formed in the second transfer region may be configured such that the first transfer region and the second transfer region are selected by arbitrarily selecting a width and an interval. A photomask producing apparatus is provided which is formed so that the difference in coverage is within a certain range.

This makes it possible to create a highly accurate mask when creating a mask using the multiple exposure technique. In addition, by manufacturing a semiconductor device using such a high-accuracy mask, a semiconductor device with high reliability and high yield can be realized.

According to an embodiment of the present invention, the dummy mask pattern formed in the second transfer region has a gap between the coverage in the first transfer region and the coverage in the second transfer region. Is formed so as to be within a certain range, a method for producing a photomask is provided.

This makes it possible to create a highly accurate mask when creating a mask using the multiple exposure technique. In addition, by manufacturing a semiconductor device using such a high-accuracy mask, a semiconductor device with high reliability and high yield can be realized.

According to an embodiment of the present invention, the dummy mask pattern formed in the second transfer region is formed on a device pattern or a dummy device pattern in the second transfer region. A photomask producing method is provided.

This makes it possible to create a highly accurate mask when creating a mask using the multiple exposure technique. In addition, by manufacturing a semiconductor device using such a high-accuracy mask, a semiconductor device with high reliability and high yield can be realized.

According to an embodiment of the present invention, the dummy mask pattern formed in the second transfer region includes a dummy mask pattern formation region and a predetermined region around the first transfer region. A method for producing a photomask is provided, wherein the difference between the coverage of the combined region and the coverage of the central portion of the first transfer region is within a certain range. .

This makes it possible to create a highly accurate mask when creating a mask using the multiple exposure technique. In addition, by manufacturing a semiconductor device using such a high-accuracy mask, a semiconductor device with high reliability and high yield can be realized.

According to an embodiment of the present invention, the dummy mask pattern formed in the second transfer region has a device pattern formed on the photomask, but no device pattern formed on the substrate. There is provided a method for producing a photomask characterized by using a sub-resolution auxiliary structure (SRAF) having properties.

This makes it possible to adjust the coverage ratio and prevent dimensional differences even in pattern areas where it is difficult to adjust the coverage difference. Therefore, when creating a mask using multiple exposure technology, high accuracy is achieved. It is possible to create a mask. In addition, by manufacturing a semiconductor device using such a high-accuracy mask, a semiconductor device with high reliability and high yield can be realized.

According to an embodiment of the present invention, the dummy mask pattern formed in the second transfer region may be configured such that the first transfer region and the second transfer region are selected by arbitrarily selecting a width and an interval. A method for producing a photomask is provided, which is formed so that the difference in coverage is within a certain range.

This makes it possible to create a highly accurate mask when creating a mask using the multiple exposure technique. In addition, by manufacturing a semiconductor device using such a high-accuracy mask, a semiconductor device with high reliability and high yield can be realized.

Moreover, according to one embodiment of the present invention, there is provided a method for manufacturing a semiconductor device comprising a lithography step of performing pattern transfer on a silicon wafer using a photomask created according to the present invention. .

According to this, it is possible to manufacture a semiconductor device using a high-precision mask and realize a semiconductor device with high reliability and high yield.

According to an embodiment of the present invention, the dummy mask pattern formed in the second transfer region includes a dummy mask pattern formation region and a predetermined region around the first transfer region. A photomask is provided in which the difference between the coverage of the combined region and the coverage of the central portion of the first transfer region is within a certain range.

This makes it possible to create a highly accurate mask when creating a mask using the multiple exposure technique. In addition, by manufacturing a semiconductor device using such a high-accuracy mask, a semiconductor device with high reliability and high yield can be realized.

According to an embodiment of the present invention, the dummy mask pattern formed in the second transfer region has a device pattern formed on the photomask, but no device pattern formed on the substrate. There is provided a photomask characterized in that a sub-resolution auxiliary structure (SRAF) having properties is used.

This makes it possible to create a highly accurate mask when creating a mask using the multiple exposure technique. In addition, by manufacturing a semiconductor device using such a high-accuracy mask, a semiconductor device with high reliability and high yield can be realized.

Moreover, according to one embodiment of the present invention, there is provided a method for manufacturing a semiconductor device comprising a lithography step of performing pattern transfer on a silicon wafer using a photomask created according to the present invention. .

According to this, it is possible to manufacture a semiconductor device using a high-precision mask and realize a semiconductor device with high reliability and high yield.

It is a block diagram which shows the structure of the preparation apparatus of the mask which concerns on one Embodiment of this invention. It is a flowchart of the creation method of the mask which concerns on one Embodiment of this invention. It is a top view which shows typically each area | region which comprises a part in plane of the mask which concerns on one Embodiment of this invention. It is a top view which expands and shows a part in mask surface when the peripheral circuit area | region is exposed. It is a top view which expands and shows a part in mask surface when the memory cell area | region is exposed. It is a top view which expands and shows a part in mask surface when the memory cell area | region is exposed. It is a top view which expands and shows a part in mask surface when the peripheral circuit area | region is exposed. It is a top view which expands and shows a part in mask surface when the peripheral circuit area | region is exposed. It is a top view which expands and shows a part in mask surface when the memory cell area | region is exposed. It is a top view which expands and shows a memory cell area | region and a part of area | region adjacent to this. It is a top view which expands and shows a memory cell area | region and a part of area | region adjacent to this. It is a top view which expands and shows a memory cell area | region and a part of area | region adjacent to this. It is a top view which expands and shows a memory cell area | region and a part of area | region adjacent to this. It is a top view which expands and shows a part in mask surface when the memory cell area | region is exposed. It is a top view which expands and shows a part in mask surface when the peripheral circuit area | region is exposed. It is a top view which expands and shows a part in mask surface when the memory cell area | region is exposed. It is a top view which expands and shows a part in mask surface when the peripheral circuit area | region is exposed. It is a top view which shows the mask in which the dummy pattern was formed in the device pattern formation area and its outer side. It is a top view which expands and shows a part (A) of the dummy mask pattern formed in the mask of FIG. It is a top view which expands and shows a part in mask surface when the memory cell area | region is exposed. It is a top view which expands and shows a part in mask surface when the peripheral circuit area | region is exposed.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Mask production apparatus 10 Layout data 20 Information of determined exposure area 30 Exposure area coverage calculation part 40 Dummy mask pattern determination part 50 of light shielding area Dummy mask creation part 60 Data output part 100 Memory cell area 200 Memory cell array 300 Peripheral circuit Region 400 Transistor group 500 Dummy device pattern 600 formed in memory cell region Open region 610 Dummy device pattern 710-790 formed in open region 1200 Dummy mask pattern 1000 Mask outline 1100 Device pattern formation region 1300 Device pattern formation region 1100 outer periphery

Claims (5)

A photomask making apparatus for exposing a first transfer region and a second transfer region to one region of a photoresist film on a main surface of a substrate in an overlapping manner,
Calculating an area coverage in the first transfer area and generating an exposure area area coverage calculation unit;
A light-shielding region dummy mask pattern determining unit that determines a dummy mask pattern formed in the second transfer region based on a calculation result generated by the exposure region coverage rate calculating unit;
Based on the determination content of the dummy mask pattern determination unit for the light shielding region, the mask layout data is synthesized by combining the dummy mask pattern data formed in the second transfer region and the layout data of the first transfer region. Creating a dummy mask based on the layout data of the mask,
And a data output unit that outputs data of the created dummy mask. The dummy mask pattern formed in the second transfer region is formed such that the difference between the coverage in the first transfer region and the coverage in the second transfer region is within a certain range. The photomask making apparatus according to claim 1. A method of manufacturing a semiconductor device, comprising a lithography step of performing pattern transfer on a silicon wafer using the photomask produced according to claim 1. A photomask making method for exposing a first transfer region and a second transfer region to one region of a photoresist film on a main surface of a substrate in an overlapping manner,
Calculating the coverage in the first transfer area and generating the result;
Based on the generated calculation result, determine a dummy mask pattern formed in the second transfer region,
The dummy mask pattern data to be formed in the determined second transfer region and the layout data of the first transfer region are combined to create mask layout data,
A method for creating a photomask, comprising: creating a dummy mask based on the layout data of the mask. A first transfer region and a second transfer region;
A dummy mask pattern on the device pattern or the dummy device pattern of the second transfer region so that the difference between the coverage of the first transfer region and the coverage of the second transfer region falls within a certain range. A photomask characterized by being formed.