TWI784224B - Memory management method, memory storage device and memory control circuit unit - Google Patents

Abstract

A memory management method is provided according to an exemplary embodiment of the invention. The method includes: reading a physical unit and updating a read count of the physical unit; scanning the physical unit if the updated read count is not less than a reading count threshold; and adjusting the reading count threshold according to the read count and an error bit. Therefore, the data unit that needs to be scanned can be determined to reduce unnecessary data scanning.

Description

Memory management method, memory storage device and memory control circuit unit

The present invention relates to a memory management technology, and in particular to a memory management method, a memory storage device and a memory control circuit unit.

Digital cameras, mobile phones, and MP3 players have grown rapidly in recent years, making consumers' demand for storage media also increase rapidly. Since the rewritable non-volatile memory module (for example, flash memory) has the characteristics of non-volatility of data, power saving, small size, and no mechanical structure, it is very suitable for internal It is built in various portable multimedia devices as exemplified above.

In memory management technology, when the host system reads the same data unit in the memory storage device more than a certain number of times, it may cause the data stored in the data unit to be unstable. Therefore, it is necessary to scan and check the data unit to avoid Determine if the data unit needs to be updated. However, if the data units in good condition are scanned frequently, the performance of the memory will be affected. Alternatively, data units in bad condition are not scanned and moved in time, which may result in data loss. Therefore, it is necessary to accurately determine the data unit that needs to be scanned.

The invention provides a memory management method, a memory storage device and a memory control circuit unit, which can determine the data unit that needs data scanning.

An exemplary embodiment of the present invention provides a memory management method for a memory storage device, and the memory management method includes: reading a physical unit, and updating the reading times of the physical unit; in the updated scanning the physical unit when the number of read times is not less than a threshold value of the number of read times; and adjusting the threshold value of the number of read times according to the number of read times and read error bits.

In an exemplary embodiment of the present invention, the step of adjusting the read count threshold according to the read count and the read error bit includes: according to the read error bit threshold and the maximum read error bit of the physical unit Determine the first misread-related factors.

In an exemplary embodiment of the present invention, the step of adjusting the read count threshold according to the read count and the read error bit includes: according to the previous read count threshold, the preset read count threshold and The first read error-related factor determines the read times threshold.

In an exemplary embodiment of the present invention, the memory management method includes: determining the preset reading times threshold according to erasing times of the physical unit.

In an exemplary embodiment of the present invention, the step of reading the physical unit and updating the reading count of the physical unit further includes: obtaining the read error bit of the physical unit.

In an exemplary embodiment of the present invention, when the updated read count is not less than the read count threshold, the step of scanning the physical unit includes: if the read error bit is greater than the read error bit threshold value, then copy the data in the physical unit to another physical unit; and if the read error bit is not greater than the read error bit threshold, record the updated read times.

In an exemplary embodiment of the present invention, the step of obtaining the read error bit of the physical unit further includes: if the read error bit is greater than the maximum read error bit, updating the maximum read error bit according to the read error bit Yuan.

In an exemplary embodiment of the present invention, the method further includes: determining a second read error related factor according to the read error bit threshold of the physical unit and the updated maximum read error bit; value, the preset read times threshold and the second read error-related factors determine the updated read times threshold; and scan all read times when the updated read times threshold is not less than the updated read times threshold the entity unit.

An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is used for coupling to the host system. The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to read the physical unit and update the reading times of the physical unit. The memory control circuit unit is further configured to scan the physical unit when the updated read count is not less than the read count threshold. And the memory control circuit unit is further configured to adjust the read count threshold according to the read count and read error bits.

In an exemplary embodiment of the present invention, the operation of the memory control circuit unit adjusting the read count threshold according to the read count and the read error bit includes: according to the read error bit of the physical unit The threshold and the maximum read error bit determine the first read error related factor.

In an exemplary embodiment of the present invention, the operation of the memory control circuit unit adjusting the read count threshold according to the read count and the read error bit includes: according to the previous read count threshold, preset It is assumed that the read times threshold and the first read error related factor determine the read times threshold.

In an exemplary embodiment of the present invention, the memory control circuit unit determines the preset read count threshold according to the erase count of the physical unit.

In an exemplary embodiment of the present invention, the operation of the memory control circuit unit reading the physical unit and updating the reading count of the physical unit includes: obtaining the read error of the physical unit Yuan.

In an exemplary embodiment of the present invention, the operation of the memory control circuit unit scanning the physical unit when the updated read count is not less than the read count threshold includes: if the read error bit If it is greater than the read error bit threshold, copy the data in the physical unit to another physical unit; and if the read error bit is not greater than the read error bit threshold, record the updated read times.

In an exemplary embodiment of the present invention, the operation of obtaining the read error bit of the physical unit includes: if the read error bit is greater than the maximum read error bit, updating the maximum read error bit according to the read error bit .

In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to determine a second read error related factor according to the read error bit threshold of the physical unit and the updated maximum read error bit, the The memory control circuit unit is further used to determine an updated read count threshold according to the previous read count threshold, the preset read count threshold and the second read error-related factor, and the memory control circuit unit further and scanning the physical unit when the updated reading times is not less than the updated reading times threshold.

Another exemplary embodiment of the present invention provides a memory control circuit unit for controlling a memory storage device including a rewritable non-volatile memory module, and the memory control circuit unit includes a host interface, a memory Body interface and memory management circuit. The host interface is used for coupling to a host system. The memory interface is used for coupling to the rewritable non-volatile memory module. The memory management circuit is coupled to the host interface and the memory interface. The memory control circuit unit is used to read the physical unit and update the reading times of the physical unit. The memory control circuit unit is further configured to scan the physical unit when the updated read count is not less than the read count threshold. And the memory control circuit unit is further used to adjust the threshold value of the read times according to the read times and the dislocation.

In an exemplary embodiment of the present invention, the operation of the memory control circuit unit adjusting the read count threshold according to the read count and the read error bit includes: according to the read error bit of the physical unit The threshold and the maximum read error bit determine the first read error related factor.

In an exemplary embodiment of the present invention, the operation of the memory control circuit unit adjusting the read count threshold according to the read count and the read error bit includes: according to the previous read count threshold, preset It is assumed that the read times threshold and the first read error related factor determine the read times threshold.

In an exemplary embodiment of the present invention, the memory control circuit unit determines the preset read count threshold according to the erase count of the physical unit.

In an exemplary embodiment of the present invention, the operation of the memory control circuit unit reading the physical unit and updating the reading count of the physical unit includes: obtaining the read error of the physical unit Yuan.

In an exemplary embodiment of the present invention, the operation of the memory control circuit unit scanning the physical unit when the updated read count is not less than the read count threshold includes: if the read error bit If it is greater than the read error bit threshold, copy the data in the physical unit to another physical unit; and if the read error bit is not greater than the read error bit threshold, record the updated read times.

In an exemplary embodiment of the present invention, the operation of obtaining the read error bit of the physical unit includes: if the read error bit is greater than the maximum read error bit, updating the maximum read error bit according to the read error bit .

In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to determine a second read error related factor according to the read error bit threshold of the physical unit and the updated maximum read error bit, the The memory control circuit unit is further used to determine an updated read count threshold according to the previous read count threshold, the preset read count threshold and the second read error-related factor, and the memory control circuit unit further and scanning the physical unit when the updated reading times is not less than the updated reading times threshold.

Based on the above, the memory management circuit can determine related read error factors according to the read error bit threshold and the maximum read error bit of the physical unit. Then, the read times threshold is determined according to the previous read times threshold, the preset read times threshold and related read error factors. After calculating the read times threshold, the memory management circuit determines whether the read times of the physical unit is not less than the read times threshold. And scan the solid unit when the number of reads is not less than the threshold value of the number of reads. In this way, unnecessary data scanning can be effectively reduced and/or the problem of data loss caused by not scanning the physical unit in time can be avoided.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

Generally speaking, a memory storage device (also called a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also called a control circuit). Generally, a memory storage device is used with a host system so that the host system can write data to or read data from the memory storage device.

FIG. 1 is a schematic diagram of a host system, a memory storage device and an input/output (I/O) device according to an exemplary embodiment of the present invention. FIG. 2 is a schematic diagram of a host system, a memory storage device and an I/O device according to another exemplary embodiment of the present invention.

Please refer to FIG. 1 and FIG. 2 , the host system 11 generally includes a processor 111 , a random access memory (random access memory, RAM) 112 , a read only memory (read only memory, ROM) 113 and a data transmission interface 114 . The processor 111 , the RAM 112 , the ROM 113 and the data transmission interface 114 are all coupled to the system bus 110 .

In this exemplary embodiment, the host system 11 is coupled to the memory storage device 10 through the data transmission interface 114 . For example, the host system 11 can store data into the memory storage device 10 or read data from the memory storage device 10 through the data transmission interface 114 . In addition, the host system 11 is coupled to the I/O device 12 through the system bus 110 . For example, the host system 11 can transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 through the system bus 110 .

In this exemplary embodiment, the processor 111 , the random access memory 112 , the read-only memory 113 and the data transmission interface 114 can be disposed on the motherboard 20 of the host system 11 . The number of data transmission interfaces 114 can be one or more. Through the data transmission interface 114 , the motherboard 20 can be coupled to the memory storage device 10 via wired or wireless means. The memory storage device 10 can be, for example, a flash drive 201 , a memory card 202 , a solid state drive (Solid State Drive, SSD) 203 or a wireless memory storage device 204 . The wireless memory storage device 204 can be, for example, a near field communication (Near Field Communication, NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth (Bluetooth) memory storage device or a Bluetooth low energy memory Storage devices (eg, iBeacon) and other memory storage devices based on various wireless communication technologies. In addition, the motherboard 20 can also be coupled to a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, etc. through the system bus 110. type I/O device. For example, in an exemplary embodiment, the motherboard 20 can access the wireless memory storage device 204 through the wireless transmission device 207 .

In an exemplary embodiment, reference to a host system is substantially any system that can cooperate with a memory storage device to store data. Although in the above exemplary embodiments, the host system is described as a computer system, however, FIG. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the present invention. Please refer to FIG. 3 , in another exemplary embodiment, the host system 31 may also be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 may be configured by it. Various non-volatile memory storage devices such as a secure digital (Secure Digital, SD) card 32, a compact flash (Compact Flash, CF) card 33 or an embedded storage device 34 are used. The embedded storage device 34 includes various types such as an embedded multimedia card (embedded Multi Media Card, eMMC) 341 and/or an embedded multi-chip package (embedded Multi Chip Package, eMCP) storage device 342. The memory module is directly coupled to the An embedded storage device on a substrate of a host system.

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention. Referring to FIG. 4 , the memory storage device 10 includes a connection interface unit 402 , a memory control circuit unit 404 and a rewritable non-volatile memory module 406 .

The connection interface unit 402 is used for coupling the memory storage device 10 to the host system 11 . The memory storage device 10 can communicate with the host system 11 through the connection interface unit 402 . In this exemplary embodiment, the connection interface unit 402 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it must be understood that the present invention is not limited thereto, and the connection interface unit 402 may also be a standard conforming to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 Standard, Peripheral Component Interconnect Express (PCI Express) standard, Universal Serial Bus (USB) standard, SD interface standard, Ultra High Speed-I (UHS-I) interface Standard, Ultra High Speed-II (UHS-II) interface standard, Memory Stick (MS) interface standard, MCP interface standard, MMC interface standard, eMMC interface standard, Universal Flash Memory (Universal Flash Storage, UFS) interface standard, eMCP interface standard, CF interface standard, Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 402 can be packaged with the memory control circuit unit 404 in a chip, or the connection interface unit 402 can be arranged outside a chip including the memory control circuit unit 404 .

The memory control circuit unit 404 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware and perform data storage in the rewritable non-volatile memory module 406 according to the instructions of the host system 11. Write, read and erase operations.

The rewritable non-volatile memory module 406 is coupled to the memory control circuit unit 404 and used for storing data written by the host system 11 . The rewritable non-volatile memory module 406 can be a single-level memory cell (Single Level Cell, SLC) NAND flash memory module (that is, a flash memory that can store 1 bit in a memory cell module), multi-level memory cell (Multi Level Cell, MLC) NAND flash memory module (that is, a flash memory module that can store 2 bits in a memory cell), three-level memory cell ( Triple Level Cell (TLC) NAND flash memory module (that is, a flash memory module that can store 3 bits in a memory cell), Quad Level Cell (QLC) NAND flash memory module A flash memory module (that is, a flash memory module that can store 4 bits in a memory cell), other flash memory modules, or other memory modules with the same characteristics.

Each memory cell in the rewritable non-volatile memory module 406 stores one or more bits by changing a voltage (also referred to as threshold voltage hereinafter). Specifically, there is a charge trapping layer between the control gate and the channel of each memory cell. By applying a writing voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. The operation of changing the threshold voltage of the memory cell is also called "writing data into the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell in the rewritable non-volatile memory module 406 has multiple storage states. Which storage state a memory cell belongs to can be judged by applying a read voltage, thereby obtaining one or more bits stored in the memory cell.

In this exemplary embodiment, the memory cells of the rewritable non-volatile memory module 406 can form a plurality of physical programming units, and these physical programming units can form a plurality of physical erasing units. Specifically, the memory cells on the same word line can form one or more physical programming units. If each memory cell can store more than 2 bits, the physical programming units on the same word line can be at least classified into lower physical programming units and upper physical programming units. For example, the Least Significant Bit (LSB) of a memory cell belongs to the lower physical programming unit, and the Most Significant Bit (MSB) of a memory cell belongs to the upper physical programming unit. Generally speaking, in MLC NAND flash memory, the writing speed of the lower physically programmed cells is greater than that of the upper physically programmed cells, and/or the reliability of the lower physically programmed cells is higher than that of the upper physically programmed cells. The solidity of the stylized unit.

In this exemplary embodiment, the entity stylized unit is the smallest stylized unit. That is, the entity stylized unit is the smallest unit for writing data. For example, a physical stylized unit may be a physical page or a physical sector. If the physical stylized units are physical pages, these physical stylized units may include data bit areas and redundancy bit areas. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area is used for storing system data (eg, management data such as error correction codes). In this exemplary embodiment, the data bit area includes 32 physical sectors, and the size of one physical sector is 512 bytes (byte, B). However, in other exemplary embodiments, the data bit area may also include 8, 16 or more or less physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, the physical erasing unit is the smallest unit of erasing. That is, each physical erase unit contains a minimum number of memory cells that are erased. For example, the physical erasing unit is a physical block.

FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Referring to FIG. 5 , the memory control circuit unit 404 includes a memory management circuit 502 , a host interface 504 and a memory interface 506 .

The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404 . Specifically, the memory management circuit 502 has a plurality of control instructions, and when the memory storage device 10 is operating, these control instructions are executed to perform operations such as writing, reading, and erasing data. When describing the operation of the memory management circuit 502 below, it is equivalent to describing the operation of the memory control circuit unit 404 .

In this exemplary embodiment, the control commands of the memory management circuit 502 are implemented in the form of firmware. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 10 is in operation, these control instructions will be executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

In another exemplary embodiment, the control commands of the memory management circuit 502 can also be stored in a specific area of the rewritable non-volatile memory module 406 in the form of code (for example, the memory module is dedicated to storing system data system area). In addition, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown) and a random access memory (not shown). In particular, the ROM has a boot code (boot code), and when the memory control circuit unit 404 is enabled, the microprocessor unit will first execute the boot code to store in the rewritable non-volatile memory The control instructions in the voxel module 406 are loaded into the random access memory of the memory management circuit 502 . Afterwards, the microprocessor unit executes these control instructions to perform operations such as writing, reading and erasing data.

In addition, in another exemplary embodiment, the control instructions of the memory management circuit 502 can also be implemented in a hardware form. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory writing circuit, a memory reading circuit, a memory erasing circuit and a data processing circuit. The memory cell management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are coupled to the microcontroller. The memory cell management circuit is used to manage memory cells or memory cell groups of the rewritable non-volatile memory module 406 . The memory writing circuit is used to issue a write command sequence to the rewritable non-volatile memory module 406 to write data into the rewritable non-volatile memory module 406 . The memory reading circuit is used to issue a read command sequence to the rewritable non-volatile memory module 406 to read data from the rewritable non-volatile memory module 406 . The memory erasing circuit is used to issue an erase command sequence to the rewritable non-volatile memory module 406 to erase data from the rewritable non-volatile memory module 406 . The data processing circuit is used for processing data to be written into the rewritable non-volatile memory module 406 and data read from the rewritable non-volatile memory module 406 . The write command sequence, the read command sequence and the erase command sequence may respectively include one or more program codes or command codes and are used to instruct the rewritable non-volatile memory module 406 to execute the corresponding write, read operations such as fetching and erasing. In an exemplary embodiment, the memory management circuit 502 can also issue other types of command sequences to the rewritable non-volatile memory module 406 to instruct to perform corresponding operations.

The host interface 504 is coupled to the memory management circuit 502 . The memory management circuit 502 can communicate with the host system 11 through the host interface 504 . The host interface 504 can be used to receive and identify commands and data sent by the host system 11 . For example, the commands and data sent by the host system 11 can be sent to the memory management circuit 502 through the host interface 504 . In addition, the memory management circuit 502 can transmit data to the host system 11 through the host interface 504 . In this exemplary embodiment, the host interface 504 is compatible with the SATA standard. However, it must be understood that the present invention is not limited thereto, and the host interface 504 can also be compatible with PATA standard, IEEE 1394 standard, PCI Express standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard , MMC standard, eMMC standard, UFS standard, CF standard, IDE standard or other suitable data transmission standards.

The memory interface 506 is coupled to the memory management circuit 502 and used for accessing the rewritable non-volatile memory module 406 . That is to say, the data to be written into the rewritable non-volatile memory module 406 will be converted into a format acceptable to the rewritable non-volatile memory module 406 through the memory interface 506 . Specifically, if the memory management circuit 502 wants to access the rewritable non-volatile memory module 406, the memory interface 506 will send a corresponding command sequence. For example, these command sequences may include a write command sequence for writing data, a read command sequence for reading data, an erase command sequence for erasing data, and instructions for various memory operations (for example, changing the read the corresponding sequence of instructions to fetch a voltage level or perform a garbage collection operation, etc.). These instruction sequences are, for example, generated by the memory management circuit 502 and sent to the rewritable non-volatile memory module 406 through the memory interface 506 . These command sequences can include one or more signals, or data on the bus. These signals or data may include instruction codes or program codes. For example, in the read command sequence, information such as read identification code and memory address will be included.

In an exemplary embodiment, the memory control circuit unit 404 further includes an error checking and correction circuit 508 , a buffer memory 510 and a power management circuit 512 .

The error checking and correction circuit 508 is coupled to the memory management circuit 502 and configured to perform error checking and correction operations to ensure correctness of data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correction circuit 508 will generate a corresponding error correcting code (ECC) for the data corresponding to the write command and/or error checking code (error detecting code, EDC), and the memory management circuit 502 will write the data corresponding to the write command and the corresponding error correction code and/or error checking code into the rewritable non-volatile In the memory module 406. Afterwards, when the memory management circuit 502 reads data from the rewritable non-volatile memory module 406, it will simultaneously read the error correction code and/or error check code corresponding to the data, and the error check and correction circuit 508 Error checking and correction operations will be performed on the read data according to the error correction code and/or error check code.

The buffer memory 510 is coupled to the memory management circuit 502 and used for temporarily storing data and instructions from the host system 11 or data from the rewritable non-volatile memory module 406 . The power management circuit 512 is coupled to the memory management circuit 502 and used for controlling the power of the memory storage device 10 .

In an exemplary embodiment, the rewritable non-volatile memory module 406 in FIG. 4 is also called a flash memory module, and the memory control circuit unit 404 is also called a Flash memory controller for the module. In an exemplary embodiment, the memory management circuit 502 of FIG. 5 is also called a flash memory management circuit.

FIG. 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. Referring to FIG. 6 , the memory management circuit 502 can logically group the physical units 610 ( 0 )˜610 (B) of the rewritable non-volatile memory module 406 into a storage area 601 and a replacement area 602 . The physical units 610(0)~610(A) in the storage area 601 are used to store data, and the physical units 610(A+1)~610(B) in the replacement area 602 are used to replace the data in the storage area 601 Damaged solid elements. For example, if the data read from a certain physical unit contains too many errors to be corrected, the physical unit will be regarded as a damaged physical unit. It should be noted that if there is no physical erase unit available in the replacement area 602, the memory management circuit 502 may declare the entire memory storage device 10 as a write-protected state, and data cannot be written any more. .

In this exemplary embodiment, each physical unit refers to a physical erasing unit. However, in another exemplary embodiment, a physical unit may also refer to a physical address, a physical stylized unit, or consist of multiple continuous or discontinuous physical addresses. The memory management circuit 502 configures the logical units 612 ( 0 )˜612 (C) to map the physical units 610 ( 0 )˜610 (A) in the storage area 601 . In this exemplary embodiment, each logical unit refers to a logical address. However, in another exemplary embodiment, a logical unit may also refer to a logical programming unit, a logical erasing unit, or consist of multiple consecutive or discontinuous logical addresses. Furthermore, each of logical units 612(0)-612(C) may be mapped to one or more physical units.

The memory management circuit 502 can record the mapping relationship between the logical unit and the physical unit (also referred to as the logical-physical address mapping relationship) in at least one logical-physical address mapping table. When the host system 11 intends to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 502 can execute the memory storage device 10 according to the logical-physical address mapping table. Data access operations.

In the memory management method provided in this embodiment, the memory management circuit 502 calculates a read count threshold (read count threshold) associated with the read count (read count) of each physical unit. And the memory management circuit 502 compares the calculated reading times threshold with the accumulated reading times of the physical unit to determine whether to scan the physical unit.

This embodiment takes scanning a physical erasing unit as an example. The memory management circuit 502 adjusts the read count threshold according to the read count and read error bits of the physical erasing unit. Specifically, the memory management circuit 502 determines the first read error related factor according to the first threshold of the physical erasing unit and the maximum read error bit. The first threshold (ie, the read error bit threshold) and the maximum read error bit are associated with the read error bit. For example, the memory management circuit 502 can calculate the first read error related factor according to the following equation (1).

(1)

(1)

In equation (1), factor _{error bit} represents a read error related factor, threshold _{error bit} represents a read error bit threshold, and error bit _max represents a maximum read error bit (max read error bit). The read error bit threshold is determined in advance, for example, through a series of experiments, and it can be used to determine whether the physical erasing unit needs a refresh operation. Specifically, the refresh operation is to copy the data in the physical erasing unit to another physical unit, and release the original physical erasing unit into the physical unit recycling area after erasing. The maximum read error bit is the largest read error bit in the recording entity erase unit.

Then, the memory management circuit 502 will determine the fourth threshold according to the second threshold (ie, the previous read times threshold), the third threshold (ie, the preset read times threshold) and the first read error-related factors. value (that is, the read count threshold). The second threshold and the third threshold are related to the reading times of the physical unit. For example, the memory management circuit 502 can calculate the read times threshold according to the following equation (2).

(2)

(2)

In equation (2), threshold _next represents the threshold value of the number of reads, threshold _pre represents the threshold value of the number of times previously read, threshold _normal represents the threshold value of the number of preset reads, and factor _{error bit} represents a factor related to misreading. Specifically, the previous reading times threshold is the reading times threshold used for judging whether to scan when the memory management circuit 502 scans the physical erasing unit last time. The preset read count threshold is, for example, determined by the memory management circuit 502 according to the erase count of the physical erase unit. When the number of times of erasing is higher, the overall space of the physical erasing unit may become smaller or may be damaged. Therefore, the number of times of erasing is negatively correlated with the threshold value of the preset number of times of reading. That is, the more erasing times of the physical erasing unit, the lower the preset reading times threshold. In other words, the reading times threshold can be recalculated according to the erasing times of the physical erasing unit. In an exemplary embodiment, the corresponding relationship between each erasing times and the preset reading times threshold can be stored in a lookup table, and the memory management circuit 502 can input the times of erasing into the lookup table and look up the The output of the table serves as a preset read count threshold corresponding to the erasure count. The corresponding relationship between the erasing times and the preset reading times threshold is shown in Table 1 below, wherein for different memories, the relationship between the erasing times and the preset reading times threshold may also be different. For the single level cell (Single Level Cell, SLC) NAND flash memory module, the preset read count threshold will decrease as the erase count increases. On the other hand, for the Multi Level Cell (MLC) NAND flash memory module, the preset read count threshold will first increase and then decrease as the erase count increases.

Table 1 Erase times Preset Read Threshold FULL SLC Erase Count Group 00-50 5.0M 51-4000 5.0M 4001-10000 3.2M 10001-20000 2.5M 20001- 600k FULL TLC Erase Count Group 0-50 1.0M 51-150 2.5M 151-500 1.9M 501-1000 1.4M 1001- 500k Open SLC Erase Count Group 00-50 3.0M 51-4000 3.0M 4001-10000 2.1M 10001-20000 1.6M 20001- 400k Open TLC Erase Count Group 0-50 500k 51-150 1.4M 151-500 1.1M 501-1000 800k 1001- 250k

In other embodiments, the corresponding relationship between each erasing count and the preset read count threshold can also be calculated using an equation, which is not limited by the present invention.

In an exemplary embodiment, equations (1) and (2) can also be adjusted, such as adding other variables or adjusting at least some logical operation elements to meet practical requirements, as long as the relationship between the read times threshold and the physical wipe can be calculated It is sufficient that the maximum read error bit of the division unit is negatively correlated.

When receiving a read command from the host system 11, the memory management circuit 502 sends a read command sequence to instruct the rewritable non-volatile memory module 406 to read data from these memory cells. The memory management circuit 502 reads the physical programming unit (also known as the physical page) according to the read command, and updates the reading times of the physical erasing unit. Specifically, each time the memory management circuit 502 reads the physical programming unit, it will continuously accumulate the reading times of the physical erasing unit and update the reading times. The memory management circuit 502 judges whether the updated read count is not less than the read count threshold, and scans the physical erasing unit when the updated read count is not less than the read count threshold. If the updated read times is less than the read times threshold, the memory management circuit 502 continues to receive read commands from the host system 11 and continues to accumulate the read times of the physical erasing unit until it is greater than or equal to the read times threshold.

The memory management method provided by this embodiment can accurately determine whether to scan the physical erasing unit by comprehensively considering the influence of factors such as erasing times and reading error bits on the reading times threshold.

In the memory management method provided in this embodiment, the memory management circuit 502 may also judge the operation to be performed on the physical erasing unit according to other conditions after scanning the physical erasing unit. Specifically, scanning the entity erasing unit can, for example, read all or part of the entity stylized units of the entity erase unit (for example, only read odd or even pages, every other fixed page such as three pages or five pages) read the physical programming unit), and the memory management circuit 502 can obtain the read error bit (read error bit) of each physical programming unit when reading the physical programming unit of the physical erasing unit as described above. The memory management circuit 502 determines whether the updated read error bit is greater than a first threshold (ie, the read error bit threshold). If the memory management circuit 502 determines that the read error bit is greater than the read error bit threshold, then refresh the physical erase unit. In the refresh operation, the memory management circuit 502 copies the data in the physical erasing unit to another physical erasing unit, and releases the physical erasing unit to the recycle area of the physical erasing unit after erasing. If the memory management circuit 502 judges that the read error bit is not greater than the read error bit threshold, then record the updated reading times, and return to step S803, the memory management circuit 502 continues to receive the read command from the host system 11, and The read error bit is updated when the physical erase unit is read.

In the memory management method provided in this embodiment, the memory management circuit 502 recalculates the read times threshold according to different conditions. For example, the maximum read error bit is updated according to the read error bit of the physical unit. Specifically, the memory management circuit 502 determines whether the read error bit is greater than the maximum read error bit. If the memory management circuit 502 determines that the read error bit of the read physical programming unit is greater than the maximum read error bit, it updates the maximum read error bit according to the read error bit. If it is determined that the read error bit of the read physical programming unit is not greater than the maximum read error bit, the memory management circuit 502 continues to receive the read command from the host system 11, and updates the read error bit when reading the physical unit.

In this exemplary embodiment, the memory management circuit 502 recalculates the read times threshold after updating the maximum read error bit. Specifically, the memory management circuit 502 determines the second read error related factor according to the read error bit threshold of the physical unit and the updated maximum read error bit. Next, a fifth threshold (that is, an updated threshold of read times) is determined according to the previous read times threshold, the preset read times threshold and the second read error related factor. And when the updated reading times is not less than the updated reading times threshold, the physical unit is scanned.

FIG. 7 is a flowchart of a memory management method according to an exemplary embodiment of the present invention. Referring to FIG. 7 , in step S701 , a first correlation factor is determined according to a first threshold value of a physical unit and a maximum read error bit. In step S702, a fourth threshold is determined according to the second threshold, the third threshold and the first correlation factor. In step S703, the reading instruction reads the physical unit, and updates the reading times of the physical unit. In step S704, it is determined whether the updated reading times are not less than the fourth threshold, and if the updated reading times are not less than the fourth threshold (step S704, yes), the entity unit is scanned (step S705). If the updated read times are less than the fourth threshold (step S704, no), go back to step S703.

FIG. 8 is a flowchart of a memory management method according to an exemplary embodiment of the present invention. Please refer to FIG. 8 , the specific content of steps S801 ~ S805 can refer to the aforementioned steps S701 ~ S705 , each step has been described in detail above, and will not be repeated here. It should be noted that, in step S803 , when reading the physical unit, in addition to updating the reading times of the physical unit, the read error bit of the physical unit is also obtained. In step S806, it is judged whether the updated read error bit is greater than the first threshold (ie, the read error threshold). If it is determined that the read error bit is greater than the first threshold (step S806, yes), then refresh the physical unit (step S807). If it is determined that the read error bit is not greater than the first threshold (step S806, no), record the updated reading times (step S808), and return to step S803. In step S809, it is judged whether the read error bit is greater than the maximum read error bit. If it is judged that the read error bit of the physical unit is greater than the maximum read error bit (step S809, yes), then update the maximum read error bit according to the read error bit (step S810). If it is judged that the read error bit of the physical unit is not greater than the maximum read error bit (step S809, judged as NO), go back to step S803.

It should be noted that each step in FIG. 7 to FIG. 8 can be implemented as a plurality of program codes or circuits, which is not limited by the present invention. In addition, in the above-mentioned embodiments, the memory management circuit 502 records and stores data such as threshold values, read times, (maximum) read error bits, and calculation results in the rewritable non-volatile memory module 406, for example. in a specific area.

To sum up, the memory management method, memory storage device and memory control circuit unit provided by the present invention comprehensively consider the influence of erasing times and read error bits on the reading times threshold. In addition, the threshold value of reading times of each physical unit can be dynamically calculated according to the maximum read error bit of each physical unit, so as to accurately determine whether the physical unit needs to perform data scanning. In this way, unnecessary data scanning can be effectively reduced and/or the problem of data loss caused by not scanning the physical unit in time can be avoided, and the performance of the memory can be improved.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

10, 30: memory storage device 11, 31: Host system 110: System bus 111: Processor 112: random access memory 113: read-only memory 114: Data transmission interface 12: Input/output (I/O) device 20: Motherboard 201: Pen drive 202: memory card 203: SSD 204: wireless memory storage device 205: GPS module 206: Network interface card 207: wireless transmission device 208: keyboard 209: screen 210: Horn 32: SD card 33: CF card 34: Embedded storage device 341: Embedded multimedia card 342: Embedded multi-chip package storage device 402: Connect the interface unit 404: memory control circuit unit 406:Rewritable non-volatile memory module 502: memory management circuit 504: host interface 506: memory interface 508: Error checking and correction circuit 510: buffer memory 512: power management circuit 601: storage area 602: Replacement area 610(0)~610(B): entity unit 612(0)~612(C): logic unit S701~S705, S801~S810: steps

FIG. 1 is a schematic diagram of a host system, a memory storage device and an input/output (I/O) device according to an exemplary embodiment of the present invention. FIG. 2 is a schematic diagram of a host system, a memory storage device and an I/O device according to another exemplary embodiment of the present invention. FIG. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the present invention. FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention. FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. FIG. 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. FIG. 7 is a flowchart of a memory management method according to an exemplary embodiment of the present invention. FIG. 8 is a flowchart of a memory management method according to an exemplary embodiment of the present invention.

S701~S705: steps

Claims (18)

A memory management method for a memory storage device, and the memory management method includes: receiving a read command from a host system; reading a physical erase unit according to the read command, and updating the physical erase unit The number of reads of the unit; when the updated number of reads is not less than a read times threshold, scan the entity erasing unit to read at least one entity programming unit included in the entity erasing unit, so as to update the entity erasing unit and adjusting the read count threshold according to the read count and the read fault bit, wherein the step of adjusting the read count threshold according to the read count and the read fault bit includes according to a previous The read count threshold, a preset read count threshold, and a first read error related factor determined according to a read error bit threshold and a maximum read error bit of the physical erasing unit determine the read count threshold, Wherein the threshold value of read times is negatively correlated with the maximum read error bit of the physical erasing unit. The memory management method described in item 1 of the scope of the patent application, wherein the memory management method includes: determining the preset reading times threshold according to the erasing times of the physical erasing unit. The memory management method described in item 1 of the scope of the patent application, wherein the step of reading the physical erasing unit according to the read command, and updating the reading times of the physical erasing unit further includes: obtaining the physical erasing unit The read error bit of the division unit. The memory management method described in item 3 of the scope of the patent application, wherein when the updated read times is not less than the read times threshold value, the physical erasing unit is scanned to read the at least A physical programming unit, the step of updating the read error bit of the physical erase unit further includes: if the read error bit is greater than a read error bit threshold, copying the data in the physical erase unit to another a physical erasing unit; and if the read error bit is not greater than the read error bit threshold, record the updated read times. The memory management method described in item 3 of the scope of the patent application, wherein the step of obtaining the read error bit of the physical erasing unit further includes: if the read error bit is greater than a maximum read error bit, update according to the read error bit The maximum read error bit. The memory management method as described in item 5 of the scope of the patent application, wherein the method further includes: determining a second read error-related factor according to a read error bit threshold of the physical erasing unit and the updated maximum read error bit ; Determine an updated read count threshold based on a previous read count threshold, a preset read count threshold and the second read error-related factor; and when the updated read count is not less than the updated read count The physical erasing unit is scanned when the times threshold is taken. A memory storage device, comprising: a connection interface unit for coupling to a host system; A rewritable non-volatile memory module; and a memory control circuit unit coupled to the connection interface unit and the rewritable non-volatile memory module, wherein the memory control circuit unit is used to receive A read command from the host system, the memory control circuit unit is further used to read the physical erasing unit according to the read command, and update the reading times of the physical erasing unit, and the memory control circuit unit further It is used for scanning the physical erasing unit to read at least one physical programming unit included in the physical erasing unit when the updated reading times is not less than a reading times threshold, so as to update the reading of the physical erasing unit error bit, and the memory control circuit unit is further used to adjust the read count threshold according to the read count and the read error bit, wherein the memory control circuit unit adjusts the read count threshold according to the read count and the read error bit The operation of the read times threshold includes a first read based on a previous read times threshold, a preset read times threshold and a read error bit threshold and a maximum read error bit of the physical erase unit. The error correlation factor determines the read times threshold, wherein the read times threshold is negatively correlated with the maximum read error bit of the physical erasing unit. The memory storage device as described in item 7 of the scope of the patent application, wherein the memory control circuit unit determines the preset reading times threshold according to the erasing times of the physical erasing unit. The memory storage device as described in item 7 of the patent scope of the application, wherein the memory control circuit unit reads the physical erasing unit according to the read instruction, and the operation of updating the read times of the physical erasing unit includes : Obtain the read error bit of the physical erase unit. The memory storage device as described in item 9 of the scope of the patent application, wherein the memory control circuit unit scans the physical erasing unit to read the physical erasing unit when the updated reading times is not less than the reading times threshold The at least one physical programming unit included in the erasing unit to update the read error bit of the physical erase unit further includes: if the read error bit is greater than a read error bit threshold, then erasing the entity in the unit Copy the data of the data to another physical erasing unit; and if the read error bit is not greater than the read error bit threshold, record the updated read times. The memory storage device as described in claim 9, wherein the operation of obtaining the read error bit of the physical erasing unit includes: if the read error bit is greater than a maximum read error bit, updating the maximum read error bit according to the read error bit Read wrong bit. The memory storage device as described in claim 11 of the scope of patent application, wherein the memory control circuit unit is further used to determine a second reading according to a read error bit threshold of the physical erasing unit and the updated maximum read error bit error related factors, the memory control circuit unit is further used to determine an updated read times according to a previous read times threshold, a preset read times threshold and the second read error related factors threshold, and the memory control circuit unit is further configured to scan the physical erasing unit when the updated read times is not less than the updated read times threshold. A memory control circuit unit for controlling a memory storage device including a rewritable non-volatile memory module, and the memory control circuit unit includes: a host interface for coupling to a host system ; a memory interface, used to be coupled to the rewritable non-volatile memory module; and a memory management circuit, coupled to the host interface and the memory interface, wherein the memory control circuit unit is used To receive a read command from the host system, the memory control circuit unit is further used to read the physical erasing unit according to the read command, and update the reading times of the physical erasing unit, the memory control circuit The unit is further used to scan the physical erasing unit to read at least one physical programming unit included in the physical erasing unit when the updated reading times is not less than a reading times threshold, so as to update the physical erasing unit The read error bit, and the memory control circuit unit is further used to adjust the read count threshold according to the read count and the read error bit, wherein the memory control circuit unit is based on the read count and the read error bit The operation of adjusting the read times threshold includes: according to a previous read times threshold, a preset read times threshold and according to a read of the physical erase unit The threshold value of read times is determined by a first read error related factor determined by an error bit threshold and a maximum read error bit, wherein the read number threshold is negatively correlated with the maximum read error bit of the physical erasing unit. The memory control circuit unit as described in claim 13 of the patent application, wherein the memory control circuit unit determines the preset reading times threshold according to the erasing times of the physical erasing unit. The memory control circuit unit as described in item 13 of the scope of the patent application, wherein the memory control circuit unit reads the physical erasing unit according to the read instruction, and updates the read times of the physical erasing unit Including: obtaining the read error bit of the physical erasing unit. The memory control circuit unit as described in item 15 of the scope of the patent application, wherein the memory control circuit unit scans the entity erasing unit to read the entity when the updated read count is not less than the read count threshold The operation of erasing the at least one physical programming unit included in the physical erasing unit to update the read error bit of the physical erasing unit further includes: if the read error bit is greater than a read error bit threshold, then erasing the physical unit Copy the data in the data to another physical erasing unit; and if the read error bit is not greater than the read error bit threshold, record the updated read times. The memory control circuit unit as described in claim 15 of the patent scope of the application, wherein the operation of obtaining the read error bit of the physical erasing unit includes: if the read error bit is greater than a maximum read error bit, updating the read error bit according to the read error bit Maximum read error bits. The memory control circuit unit as described in claim 17 of the scope of the patent application, wherein the memory control circuit unit is further used to determine a second read error bit threshold based on the physical erasing unit and the updated maximum read error bit The error-related factor, the memory control circuit unit is further used to determine an updated read-time threshold according to a previous read-time threshold, a preset read-time threshold and the second read-error-related factor, and The memory control circuit unit is further used for scanning the physical erasing unit when the updated read times is not less than the updated read times threshold.

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