TW202125265A - Memory management method, memory storage device and memory control circuit unit - Google Patents

Abstract

A memory management method is provided according to an exemplary embodiment of the invention. The method includes: reading a physical unit and updating a read count of the physical unit; scanning the physical unit if the updated read count is not less than a reading count threshold; and adjusting the reading count threshold according to the read count and an error bit. Therefore, the data unit that needs to be scanned can be determined to reduce unnecessary data scanning.

Description

Memory management method, memory storage device and memory control circuit unit

The present invention relates to a memory management technology, and particularly relates to a memory management method, a memory storage device and a memory control circuit unit.

Digital cameras, mobile phones and MP3 players have grown rapidly in the past few years, which has led to a rapid increase in consumer demand for storage media. As the rewritable non-volatile memory module (for example, flash memory) has the characteristics of non-volatile data, power saving, small size, and no mechanical structure, it is very suitable for internal Built in the various portable multimedia devices mentioned above.

In the memory management technology, when the host system reads the same data unit in the memory storage device more than a certain number of times, the data stored in the data unit may be unstable. Therefore, it is necessary to scan and check the data unit. Determine whether the data unit needs to be updated. However, if data units in good condition are scanned frequently, the performance of the memory will be affected. Or, data units that are not in good condition are not scanned and moved in time, which may cause data loss. Therefore, it is necessary to accurately determine the data unit that needs to be scanned.

The invention provides a memory management method, a memory storage device and a memory control circuit unit, which can determine the data unit that needs to be scanned for data.

An exemplary embodiment of the present invention provides a memory management method for a memory storage device, and the memory management method includes: reading a physical unit, and updating the number of times the physical unit is read; Scanning the physical unit when the number of reading times is not less than the threshold value of the number of reading times; and adjusting the threshold value of the number of reading times according to the number of reading times and read error bits.

In an exemplary embodiment of the present invention, the step of adjusting the threshold of the number of reads according to the number of reads and the number of misreads includes: according to the threshold of misreads and the maximum misread of the physical unit Decide the factors related to the first mispronunciation.

In an exemplary embodiment of the present invention, the step of adjusting the threshold of the number of readings according to the number of readings and the number of misreading bits includes: according to the threshold of the number of previous readings, a threshold of the number of presets, and The first reading error-related factor determines the threshold of the number of readings.

In an exemplary embodiment of the present invention, the memory management method includes: determining the preset read count threshold according to the erasure count of the physical unit.

In an exemplary embodiment of the present invention, the step of reading the physical unit and updating the read count of the physical unit further includes: obtaining the misread bit of the physical unit.

In an exemplary embodiment of the present invention, the step of scanning the physical unit when the updated number of reads is not less than the threshold of the number of reads includes: if the read error bit is greater than the read error bit threshold Value, copy the data in the physical unit to another physical unit; and if the misread bit is not greater than the misread bit threshold, record the updated read times.

In an exemplary embodiment of the present invention, the step of obtaining the misread bit of the physical unit further includes: if the misread bit is greater than the maximum misread bit, updating the maximum misread bit according to the misread bit Yuan.

In an exemplary embodiment of the present invention, the method further includes: determining a second read error related factor according to the read error bit threshold of the physical unit and the updated maximum read error bit; according to the previous read count threshold Value, the preset reading times threshold, and the second reading error-related factors determine the updated reading times threshold; and scanning when the updated reading times is not less than the updated reading times threshold The physical unit.

An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is used for coupling to the host system. The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used for reading the physical unit and updating the reading times of the physical unit. The memory control circuit unit is further configured to scan the physical unit when the updated read count is not less than the read count threshold. And the memory control circuit unit is further used to adjust the threshold of the number of reads according to the number of reads and read error bits.

In an exemplary embodiment of the present invention, the operation of the memory control circuit unit to adjust the threshold of the number of reads according to the number of reads and the number of read errors includes: according to the number of read errors of the physical unit The threshold value and the maximum misreading bit determine the factors related to the first misreading.

In an exemplary embodiment of the present invention, the operation of the memory control circuit unit to adjust the threshold of the number of reads according to the number of reads and the number of misread bits includes: according to the threshold of the number of previous reads, pre- It is assumed that the threshold of the number of readings and the first reading error-related factor determine the threshold of the number of readings.

In an exemplary embodiment of the present invention, the memory control circuit unit determines the preset read count threshold according to the erase count of the physical unit.

In an exemplary embodiment of the present invention, the operation of the memory control circuit unit to read the physical unit and update the read count of the physical unit includes: obtaining the read misalignment of the physical unit Yuan.

In an exemplary embodiment of the present invention, the operation of the memory control circuit unit to scan the physical unit when the updated read count is not less than the read count threshold includes: if the read error bit If it is greater than the misreading bit threshold, copy the data in the physical unit to another physical unit; and if the misreading bit is not greater than the misreading threshold, then recording the updated reading times.

In an exemplary embodiment of the present invention, the operation of obtaining the misread bit of the physical unit includes: if the misread bit is greater than the maximum misread bit, updating the maximum misread bit according to the misread bit .

In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to determine a second read error related factor according to the read error bit threshold of the physical unit and the updated maximum read error bit. The memory control circuit unit is further configured to determine an updated threshold of the number of reads according to the threshold of the number of previous reads, the threshold of the number of presets, and the second read error-related factor, and the memory control circuit unit further It is used to scan the physical unit when the updated read count is not less than the updated read count threshold.

Another exemplary embodiment of the present invention provides a memory control circuit unit for controlling a memory storage device including a rewritable non-volatile memory module, and the memory control circuit unit includes a host interface, a memory Body interface and memory management circuit. The host interface is used for coupling to a host system. The memory interface is used for coupling to the rewritable non-volatile memory module. The memory management circuit is coupled to the host interface and the memory interface. The memory control circuit unit is used for reading the physical unit and updating the reading times of the physical unit. The memory control circuit unit is further configured to scan the physical unit when the updated read count is not less than the read count threshold. And the memory control circuit unit is further used for adjusting the threshold of the number of reads according to the number of reads and the number of misalignments.

In an exemplary embodiment of the present invention, the operation of the memory control circuit unit to adjust the threshold of the number of reads according to the number of reads and the number of read errors includes: according to the number of read errors of the physical unit The threshold value and the maximum misreading bit determine the factors related to the first misreading.

In an exemplary embodiment of the present invention, the operation of the memory control circuit unit to adjust the threshold of the number of reads according to the number of reads and the number of misread bits includes: according to the threshold of the number of previous reads, pre- It is assumed that the threshold of the number of readings and the first reading error-related factor determine the threshold of the number of readings.

In an exemplary embodiment of the present invention, the memory control circuit unit determines the preset read count threshold according to the erase count of the physical unit.

In an exemplary embodiment of the present invention, the operation of the memory control circuit unit to read the physical unit and update the read count of the physical unit includes: obtaining the read misalignment of the physical unit Yuan.

In an exemplary embodiment of the present invention, the operation of the memory control circuit unit to scan the physical unit when the updated read count is not less than the read count threshold includes: if the read error bit If it is greater than the misreading bit threshold, copy the data in the physical unit to another physical unit; and if the misreading bit is not greater than the misreading threshold, then recording the updated reading times.

In an exemplary embodiment of the present invention, the operation of obtaining the misread bit of the physical unit includes: if the misread bit is greater than the maximum misread bit, updating the maximum misread bit according to the misread bit .

In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to determine a second read error related factor according to the read error bit threshold of the physical unit and the updated maximum read error bit. The memory control circuit unit is further configured to determine an updated threshold of the number of reads according to the threshold of the number of previous reads, the threshold of the number of presets, and the second read error-related factor, and the memory control circuit unit further It is used to scan the physical unit when the updated read count is not less than the updated read count threshold.

Based on the above, the memory management circuit can determine the related read error factors according to the read error bit threshold and the maximum read error bit of the physical unit. Then, the threshold of the number of readings is determined according to the threshold of the number of previous readings, the threshold of the number of readings preset, and related reading error factors. After calculating the threshold of the number of reads, the memory management circuit determines whether the number of reads of the physical unit is not less than the threshold of the number of reads. And scan the physical unit when the number of readings is not less than the threshold of the number of readings. In this way, unnecessary data scanning can be effectively reduced and/or the problem of data loss caused by failure to scan the physical unit in time can be avoided.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

Generally speaking, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as a control circuit). Generally, the memory storage device is used together with the host system, so that the host system can write data to the memory storage device or read data from the memory storage device.

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the present invention. FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to another exemplary embodiment of the present invention.

1 and FIG. 2, the host system 11 generally includes a processor 111, a random access memory (RAM) 112, a read only memory (ROM) 113, and a data transmission interface 114. The processor 111, the random access memory 112, the read-only memory 113, and the data transmission interface 114 are all coupled to a system bus 110.

In this exemplary embodiment, the host system 11 is coupled to the memory storage device 10 through the data transmission interface 114. For example, the host system 11 can store data to the memory storage device 10 or read data from the memory storage device 10 via the data transmission interface 114. In addition, the host system 11 is coupled to the I/O device 12 through the system bus 110. For example, the host system 11 can transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 via the system bus 110.

In this exemplary embodiment, the processor 111, the random access memory 112, the read-only memory 113, and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transmission interfaces 114 may be one or more. Through the data transmission interface 114, the motherboard 20 can be coupled to the memory storage device 10 in a wired or wireless manner. The memory storage device 10 may be, for example, a flash drive 201, a memory card 202, a solid state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a Near Field Communication (NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth (Bluetooth) memory storage device, or a Bluetooth low energy memory device. Storage devices (for example, iBeacon) and other memory storage devices based on various wireless communication technologies. In addition, the motherboard 20 can also be coupled to a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, etc. through the system bus 110. Type I/O device. For example, in an exemplary embodiment, the motherboard 20 can access the wireless memory storage device 204 through the wireless transmission device 207.

In an exemplary embodiment, the host system mentioned is any system that can substantially cooperate with a memory storage device to store data. Although in the above exemplary embodiment, the host system is described as a computer system, FIG. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the present invention. 3, in another exemplary embodiment, the host system 31 can also be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 can be used for it. Various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 are used. The embedded storage device 34 includes an embedded Multi Media Card (eMMC) 341 and/or an embedded Multi Chip Package (embedded Multi Chip Package, eMCP) storage device 342. The memory module is directly coupled to the Embedded storage device on the substrate of the host system.

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404, and a rewritable non-volatile memory module 406.

The connection interface unit 402 is used to couple the memory storage device 10 to the host system 11. The memory storage device 10 can communicate with the host system 11 through the connection interface unit 402. In this exemplary embodiment, the connection interface unit 402 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it must be understood that the present invention is not limited to this, and the connection interface unit 402 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 Standard, high-speed peripheral component connection interface (Peripheral Component Interconnect Express, PCI Express) standard, Universal Serial Bus (USB) standard, SD interface standard, Ultra High Speed-I (UHS-I) interface Standard, Ultra High Speed-II (UHS-II) interface standard, Memory Stick (MS) interface standard, MCP interface standard, MMC interface standard, eMMC interface standard, universal flash memory (Universal Flash Storage, UFS) interface standard, eMCP interface standard, CF interface standard, Integrated Device Electronics (IDE) standard or other suitable standards. The connection interface unit 402 and the memory control circuit unit 404 can be packaged in one chip, or the connection interface unit 402 can be arranged outside a chip including the memory control circuit unit 404.

The memory control circuit unit 404 is used to execute a plurality of logic gates or control commands implemented in a hardware type or a firmware type, and perform data processing in the rewritable non-volatile memory module 406 according to the instructions of the host system 11 Operations such as writing, reading, and erasing.

The rewritable non-volatile memory module 406 is coupled to the memory control circuit unit 404 and used to store data written by the host system 11. The rewritable non-volatile memory module 406 can be a single level cell (SLC) NAND flash memory module (that is, a flash memory that can store 1 bit in a memory cell). Module), Multi Level Cell (MLC) NAND-type flash memory module (that is, a flash memory module that can store 2 bits in a memory cell), and a third-level memory cell ( Triple Level Cell (TLC) NAND flash memory modules (that is, a flash memory module that can store 3 bits in a memory cell), Quad Level Cell (QLC) NAND flash memory modules Flash memory module (that is, a flash memory module that can store 4 bits in a memory cell), other flash memory modules, or other memory modules with the same characteristics.

Each memory cell in the rewritable non-volatile memory module 406 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, there is a charge trapping layer between the control gate and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data into the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell in the rewritable non-volatile memory module 406 has multiple storage states. By applying the read voltage, it is possible to determine which storage state a memory cell belongs to, thereby obtaining one or more bits stored in the memory cell.

In this exemplary embodiment, the memory cells of the rewritable non-volatile memory module 406 can constitute a plurality of physical programming units, and these physical programming units can constitute a plurality of physical erasing units. Specifically, the memory cells on the same character line can form one or more physical programming units. If each memory cell can store more than two bits, the physical programming unit on the same character line can be at least classified into a lower physical programming unit and an upper physical programming unit. For example, the Least Significant Bit (LSB) of a memory cell belongs to the lower physical programming unit, and the Most Significant Bit (MSB) of a memory cell belongs to the upper physical programming unit. Generally speaking, in MLC NAND flash memory, the writing speed of the lower physical programming unit is higher than that of the upper physical programming unit, and/or the reliability of the lower physical programming unit is higher than that of the upper physical programming unit. The reliability of the physical programming unit.

In this exemplary embodiment, the physical programming unit is the smallest programming unit. That is, the physical programming unit is the smallest unit for writing data. For example, the physical programming unit may be a physical page (page) or a physical sector (sector). If the physical programming unit is a physical page, these physical programming units may include a data bit area and a redundancy bit area. The data bit area includes multiple physical sectors for storing user data, and the redundant bit area is used for storing system data (for example, management data such as error correction codes). In this exemplary embodiment, the data bit area includes 32 physical sectors, and the size of one physical sector is 512 bytes (byte, B). However, in other exemplary embodiments, the data bit area may also include 8, 16, or more or less physical sectors, and the size of each physical sector can also be larger or smaller. On the other hand, the physical erasure unit is the smallest unit of erasure. That is, each physical erasing unit contains one of the smallest number of memory cells to be erased. For example, the physical erasing unit is a physical block.

FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. 5, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504, and a memory interface 506.

The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and when the memory storage device 10 is operating, these control commands are executed to perform operations such as writing, reading, and erasing data. The following description of the operation of the memory management circuit 502 is equivalent to the description of the operation of the memory control circuit unit 404.

In this exemplary embodiment, the control commands of the memory management circuit 502 are implemented in firmware. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control commands are burned into the read-only memory. When the memory storage device 10 is operating, these control commands are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

In another exemplary embodiment, the control commands of the memory management circuit 502 can also be stored in a specific area of the rewritable non-volatile memory module 406 in the form of code (for example, the memory module is dedicated to storing system data). System area). In addition, the memory management circuit 502 has a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). In particular, the read-only memory has a boot code, and when the memory control circuit unit 404 is enabled, the microprocessor unit will first execute the boot code to store it in the rewritable non-volatile memory The control commands in the volume module 406 are loaded into the random access memory of the memory management circuit 502. After that, the microprocessor unit runs these control commands to perform data writing, reading, and erasing operations.

In addition, in another exemplary embodiment, the control commands of the memory management circuit 502 can also be implemented in a hardware type. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory writing circuit, a memory reading circuit, a memory erasing circuit, and a data processing circuit. The memory cell management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are coupled to the microcontroller. The memory cell management circuit is used to manage the memory cell or the memory cell group of the rewritable non-volatile memory module 406. The memory write circuit is used to issue a write command sequence to the rewritable non-volatile memory module 406 to write data into the rewritable non-volatile memory module 406. The memory read circuit is used to issue a read command sequence to the rewritable non-volatile memory module 406 to read data from the rewritable non-volatile memory module 406. The memory erasing circuit is used to issue an erasing command sequence to the rewritable non-volatile memory module 406 to erase data from the rewritable non-volatile memory module 406. The data processing circuit is used for processing data to be written to the rewritable non-volatile memory module 406 and data read from the rewritable non-volatile memory module 406. The write command sequence, the read command sequence, and the erase command sequence may each include one or more program codes or command codes and are used to instruct the rewritable non-volatile memory module 406 to perform corresponding writing and reading. Take and erase operations. In an exemplary embodiment, the memory management circuit 502 can also send other types of command sequences to the rewritable non-volatile memory module 406 to instruct to perform corresponding operations.

The host interface 504 is coupled to the memory management circuit 502. The memory management circuit 502 can communicate with the host system 11 through the host interface 504. The host interface 504 can be used to receive and identify commands and data sent by the host system 11. For example, the commands and data sent by the host system 11 can be sent to the memory management circuit 502 through the host interface 504. In addition, the memory management circuit 502 can transmit data to the host system 11 through the host interface 504. In this exemplary embodiment, the host interface 504 is compatible with the SATA standard. However, it must be understood that the present invention is not limited to this. The host interface 504 can also be compatible with PATA standards, IEEE 1394 standards, PCI Express standards, USB standards, SD standards, UHS-I standards, UHS-II standards, and MS standards. , MMC standard, eMMC standard, UFS standard, CF standard, IDE standard or other suitable data transmission standards.

The memory interface 506 is coupled to the memory management circuit 502 and used to access the rewritable non-volatile memory module 406. In other words, the data to be written into the rewritable non-volatile memory module 406 is converted into a format acceptable by the rewritable non-volatile memory module 406 through the memory interface 506. Specifically, if the memory management circuit 502 needs to access the rewritable non-volatile memory module 406, the memory interface 506 will send the corresponding command sequence. For example, these command sequences may include a write command sequence instructing to write data, a read command sequence instructing to read data, an erase command sequence instructing to erase data, and various memory operations (for example, changing read Take the voltage level or execute the garbage collection operation, etc.) corresponding to the instruction sequence. These command sequences are generated by the memory management circuit 502 and transmitted to the rewritable non-volatile memory module 406 through the memory interface 506, for example. These command sequences can include one or more signals, or data on the bus. These signals or data may include script codes or program codes. For example, in the read command sequence, the read identification code, memory address and other information will be included.

In an exemplary embodiment, the memory control circuit unit 404 further includes an error checking and correction circuit 508, a buffer memory 510, and a power management circuit 512.

The error checking and correcting circuit 508 is coupled to the memory management circuit 502 and used to perform error checking and correcting operations to ensure the correctness of the data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correction circuit 508 will generate a corresponding error correcting code (ECC) for the data corresponding to the write command. And/or error detecting code (EDC), and the memory management circuit 502 will write the data corresponding to the write command and the corresponding error correction code and/or error check code to the rewritable non-volatile In the memory module 406. After that, when the memory management circuit 502 reads data from the rewritable non-volatile memory module 406, it will read the error correction code and/or error check code corresponding to the data at the same time, and the error check and correction circuit 508 Based on this error correction code and/or error check code, error checking and correction operations will be performed on the read data.

The buffer memory 510 is coupled to the memory management circuit 502 and used to temporarily store data and commands from the host system 11 or data from the rewritable non-volatile memory module 406. The power management circuit 512 is coupled to the memory management circuit 502 and used to control the power of the memory storage device 10.

In an exemplary embodiment, the rewritable non-volatile memory module 406 of FIG. 4 is also called a flash memory module, and the memory control circuit unit 404 is also called for controlling the flash memory The flash memory controller of the physical module. In an exemplary embodiment, the memory management circuit 502 of FIG. 5 is also referred to as a flash memory management circuit.

FIG. 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. 6, the memory management circuit 502 can logically group the physical units 610(0) to 610(B) of the rewritable non-volatile memory module 406 into the storage area 601 and the replacement area 602. The physical units 610(0)~610(A) in the storage area 601 are used to store data, and the physical units 610(A+1)~610(B) in the replacement area 602 are used to replace the storage area 601 Damaged physical unit. For example, if the data read from a certain physical unit contains too many errors to be corrected, the physical unit will be regarded as a damaged physical unit. It should be noted that if there is no available physical erasing unit in the replacement area 602, the memory management circuit 502 may declare the entire memory storage device 10 as a write protect state, and no more data can be written. .

In this exemplary embodiment, each physical unit refers to a physical erasing unit. However, in another exemplary embodiment, a physical unit may also refer to a physical address, a physical programming unit, or consist of multiple continuous or discontinuous physical addresses. The memory management circuit 502 will configure the logical units 612(0)-612(C) to map the physical units 610(0)-610(A) in the storage area 601. In this exemplary embodiment, each logical unit refers to a logical address. However, in another exemplary embodiment, a logic unit may also refer to a logic programming unit, a logic erasing unit, or consist of multiple consecutive or discontinuous logic addresses. In addition, each of the logical units 612(0)-612(C) may be mapped to one or more physical units.

The memory management circuit 502 can record the mapping relationship between the logical unit and the physical unit (also referred to as the logical-physical address mapping relationship) in at least one logical-physical address mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 502 can perform the processing of the memory storage device 10 according to the logical-physical address mapping table. Data access operations.

In the memory management method provided in this embodiment, the memory management circuit 502 calculates the read count threshold associated with the read count of each physical unit. In addition, the memory management circuit 502 compares the calculated reading frequency threshold with the accumulated reading frequency of the physical unit to determine whether to scan the physical unit.

In this embodiment, scanning a physical erasing unit is taken as an example. The memory management circuit 502 adjusts the read count threshold according to the read count and misread bits of the physical erasing unit. Specifically, the memory management circuit 502 determines the first read error related factor according to the first threshold of the physical erasing unit and the maximum read error bit. The first threshold (ie, the threshold for misreading bits) and the maximum misreading bits are related to the misreading bits. For example, the memory management circuit 502 can calculate the first misread-related factor according to the following equation (1).

(1)

(1)

In the equation (1), the factor _{error bit} represents the read error related factors, the threshold _{error bit} represents the read error bit threshold, and the error bit _max represents the maximum read error bit (max read error bit). The threshold for misreading bits is determined in advance through a series of experiments, for example, and can be used to determine whether the physical erasing unit needs a refresh operation. Specifically, the refresh operation is to copy the data in the physical erasing unit to another physical unit, and then release the original physical erasing unit to the physical unit recovery area after erasing the original physical erasing unit. The maximum read error bit is the largest read error bit in the record entity erasing unit.

Then, the memory management circuit 502 will determine the fourth valve according to the second threshold (ie, the threshold of the number of previous reads), the third threshold (ie, the threshold of the preset number of reads), and the first read error related factors. Value (that is, the threshold of the number of readings). The second threshold and the third threshold are related to the number of readings of the physical unit. For example, the memory management circuit 502 can calculate the threshold of the number of read times according to the following equation (2).

(2)

(2)

In equation (2), threshold _next represents the threshold of the number of reads, threshold _pre represents the threshold of the number of previous reads, threshold _normal represents the threshold of the preset number of reads, and factor _{error bit} represents factors related to reading errors. Specifically, the previous read count threshold is the read count threshold used to determine whether to scan the physical erasing unit the previous time when the memory management circuit 502 scans the physical erasing unit. The preset read count threshold is, for example, determined by the memory management circuit 502 according to the erase count of the physical erase unit. When the number of erasing times is higher, the physical erasing unit has the risk of becoming smaller or broken. Therefore, the number of erasing times is negatively correlated with the preset reading number threshold. That is, the more the erasing times of the physical erasing unit, the lower the preset reading times threshold. In other words, the threshold of the number of reads can be recalculated and determined according to the number of erasing of the physical erasing unit. In an exemplary embodiment, the corresponding relationship between each erase count and the preset read count threshold may be stored in a look-up table, for example, and the memory management circuit 502 may input the erase count into the look-up table and look it up. The output of the table is used as the preset reading number threshold corresponding to the number of erasures. The corresponding relationship between the number of erasing times and the threshold of the preset read times is shown in Table 1 below. For different memories, the relationship between the number of erasing and the threshold of the preset read times may be different. For Single Level Cell (SLC) NAND flash memory modules, the default read threshold will decrease as the number of erases increases. On the other hand, for Multi Level Cell (MLC) NAND flash memory modules, the default read threshold will first increase and then decrease as the number of erases increases.

Table 1 Number of erasures Preset reading threshold FULL SLC Erase Count Group 00-50 5.0M 51-4000 5.0M 4001-10000 3.2M 10001-20000 2.5M 20001- 600k FULL TLC Erase Count Group 0-50 1.0M 51-150 2.5M 151-500 1.9M 501-1000 1.4M 1001- 500k Open SLC Erase Count Group 00-50 3.0M 51-4000 3.0M 4001-10000 2.1M 10001-20000 1.6M 20001- 400k Open TLC Erase Count Group 0-50 500k 51-150 1.4M 151-500 1.1M 501-1000 800k 1001- 250k

In other embodiments, the corresponding relationship between the number of erasing times and the threshold value of the preset reading times can also be calculated using equations, and the present invention is not limited here.

In an exemplary embodiment, equations (1) and (2) can also be adjusted, such as adding other variables or adjusting at least part of the logical operation elements to meet practical needs, as long as the threshold for the number of reads and the physical wipe can be calculated In addition, the maximum misreading bit of the unit is negatively correlated.

When receiving a read command from the host system 11, the memory management circuit 502 will send a read command sequence to instruct the rewritable non-volatile memory module 406 to read data from these memory cells. The memory management circuit 502 reads the physical programming unit (also called the physical page) according to the read command, and updates the read count of the physical erase unit. Specifically, each time the memory management circuit 502 reads the physical programming unit, it will continue to accumulate the number of reads of the physical erase unit and update the number of reads. The memory management circuit 502 judges whether the updated read count is not less than the read count threshold, and scans the physical erasing unit when the updated read count is not less than the read count threshold. If the updated read count is less than the read count threshold, the memory management circuit 502 continues to receive the read command from the host system 11, and continues to accumulate the read count of the physical erasing unit until it is greater than or equal to the read count threshold.

By comprehensively considering the influence of the number of erasing times, misreading bits and other factors on the threshold of reading times, the memory management method provided in this embodiment can accurately determine whether the physical erasing unit needs to be scanned.

In the memory management method provided in this embodiment, the memory management circuit 502 can also determine the operation performed on the physical erasing unit according to other conditions after scanning the physical erasing unit. Specifically, the scanning physical erasing unit can, for example, read all the physical programming units or part of the physical programming units of the physical erasing unit (for example, reading only odd or even pages, fixed pages such as three or five pages). Read the physical programming unit), and the memory management circuit 502 can obtain the read error bit of each physical programming unit when reading the physical programming unit of the physical erasing unit as described above. The memory management circuit 502 determines whether the updated misread bit is greater than the first threshold (that is, the misread threshold). If the memory management circuit 502 determines that the misreading bit is greater than the misreading bit threshold, it refreshes the above-mentioned physical erasing unit. In the refresh operation, the memory management circuit 502 copies the data in the aforementioned physical erasing unit to another physical erasing unit, and releases the aforementioned physical erasing unit to the physical erasing unit recovery area after erasing. If the memory management circuit 502 determines that the read error bit is not greater than the read error bit threshold, it records the updated number of reads, and can return to step S803, the memory management circuit 502 continues to receive read commands from the host system 11, and The read error bit is updated when the physical erase unit is read.

In the memory management method provided in this embodiment, the memory management circuit 502 recalculates the threshold of the number of reads according to different conditions. For example, the maximum read error bit is updated according to the read error bit of the physical unit. Specifically, the memory management circuit 502 determines whether the misread bit is greater than the maximum misread bit. If the memory management circuit 502 determines that the read error bit of the read physical programming unit is greater than the maximum read error bit, then the maximum read error bit is updated according to the read error bit. If it is determined that the read error bit of the read physical programming unit is not greater than the maximum read error bit, the memory management circuit 502 continues to receive the read command from the host system 11, and updates the read error bit when reading the physical unit.

In this exemplary embodiment, the memory management circuit 502 recalculates the threshold of the number of read times after updating the maximum read error bit. Specifically, the memory management circuit 502 determines the second misread-related factor according to the read error bit threshold of the physical unit and the updated maximum read error bit. Then, the fifth threshold (ie, the updated threshold of the number of readings) is determined according to the threshold of the number of previous readings, the threshold of the preset readings, and the second reading error-related factors. And scan the physical unit when the updated reading times are not less than the updated reading times threshold.

FIG. 7 is a flowchart of a memory management method according to an exemplary embodiment of the present invention. Referring to FIG. 7, in step S701, the first relevant factor is determined according to the first threshold of the physical unit and the maximum misreading bit. In step S702, the fourth threshold is determined according to the second threshold, the third threshold, and the first related factor. In step S703, the read instruction reads the physical unit, and updates the number of reads of the physical unit. In step S704, it is determined whether the updated number of reads is not less than the fourth threshold, and the physical unit is scanned when the updated number of reads is not less than the fourth threshold (step S704, the determination is YES) (step S705). If the updated number of reads is less than the fourth threshold (step S704, judged as No), return to step S703.

FIG. 8 is a flowchart of a memory management method according to an exemplary embodiment of the present invention. Please refer to FIG. 8, the specific content of steps S801 to S805 can refer to the aforementioned steps S701 to S705, each step has been described in detail as above, and will not be repeated here. It should be noted that, in step S803, when the physical unit is read, in addition to updating the read times of the physical unit, the read error bit of the physical unit is also obtained. In step S806, it is determined whether the updated misreading bit is greater than the first threshold (that is, the misreading threshold). If it is determined that the misread bit is greater than the first threshold (step S806, the determination is YES), then the physical unit is refreshed (step S807). If it is judged that the misreading bit is not greater than the first threshold (step S806, judged as No), then the updated reading times are recorded (step S808), and step S803 can be returned to. In step S809, it is determined whether the misread bit is greater than the maximum misread bit. If it is determined that the misread bit of the physical unit is greater than the maximum misread bit (step S809, the judgment is YES), the maximum misread bit is updated according to the misread bit (step S810). If it is determined that the misreading bit of the physical unit is not greater than the maximum misreading bit (step S809, the judgment is No), the step S803 can be returned to.

It is worth noting that each step in FIG. 7 to FIG. 8 can be implemented as multiple program codes or circuits, and the present invention is not limited. In addition, in the foregoing embodiments, the memory management circuit 502 stores data records such as thresholds, read times, (maximum) misread bits, calculation results, etc., in the rewritable non-volatile memory module 406, for example. In a specific area.

In summary, the memory management method, memory storage device, and memory control circuit unit provided by the present invention comprehensively consider the effects of erasing times and misreading bits on the threshold of read times. In addition, the threshold value of the reading times of each physical unit can be dynamically calculated according to the maximum misread position of each physical unit, so as to accurately determine whether the physical unit needs to scan data. In this way, unnecessary data scanning can be effectively reduced and/or the problem of data loss caused by failure to scan the physical unit in time can be avoided, and the performance of the memory can be improved.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be subject to those defined by the attached patent application scope.

10.30: Memory storage device 11, 31: host system 110: system bus 111: processor 112: Random Access Memory 113: read-only memory 114: Data Transmission Interface 12: Input/output (I/O) device 20: Motherboard 201: flash drive 202: Memory Card 203: Solid State Drive 204: wireless memory storage device 205: Global Positioning System Module 206: network interface card 207: wireless transmission device 208: keyboard 209: Screen 210: Horn 32: SD card 33: CF card 34: Embedded storage device 341: Embedded Multimedia Card 342: Embedded multi-chip package storage device 402: connection interface unit 404: Memory control circuit unit 406: rewritable non-volatile memory module 502: Memory Management Circuit 504: Host Interface 506: Memory Interface 508: error checking and correction circuit 510: buffer memory 512: power management circuit 601: storage area 602: replacement area 610(0)~610(B): physical unit 612(0)~612(C): logic unit S701~S705, S801~S810: steps

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the present invention. FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to another exemplary embodiment of the present invention. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the present invention. FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention. FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. FIG. 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. FIG. 7 is a flowchart of a memory management method according to an exemplary embodiment of the present invention. FIG. 8 is a flowchart of a memory management method according to an exemplary embodiment of the present invention.

S701~S705: steps

Claims (24)

A memory management method used in a memory storage device, and the memory management method includes: Read a physical unit, and update the read count of the physical unit; Scan the physical unit when the updated read count is not less than a read count threshold; and Adjust the threshold of the number of reads according to the number of reads and read error bits. For the memory management method described in item 1 of the scope of patent application, the step of adjusting the threshold of the number of reads according to the number of reads and the number of misread bits includes: A first misread related factor is determined according to a misreading bit threshold and a maximum misreading bit of the physical unit. For the memory management method described in item 2 of the scope of patent application, the step of adjusting the threshold of the number of reads according to the number of reads and the number of misread bits includes: The threshold of the number of readings is determined according to a threshold of the number of previous readings, a threshold of the number of readings, and the first reading error-related factors. The memory management method described in item 3 of the scope of patent application, wherein the memory management method includes: The threshold of the preset reading times is determined according to the erasing times of the physical unit. For the memory management method described in item 1 of the scope of patent application, the step of reading the physical unit and updating the read count of the physical unit further includes: Obtain the misread bit of the physical unit. For the memory management method described in item 5 of the scope of patent application, the step of scanning the physical unit when the updated read count is not less than the read count threshold includes: If the misread bit is greater than a misread bit threshold, copy the data in the physical unit to another physical unit; and If the misreading bit is not greater than the misreading bit threshold, the updated reading times are recorded. For the memory management method described in item 5 of the scope of patent application, the step of obtaining the misread bit of the physical unit further includes: If the misread bit is greater than a maximum misread bit, the maximum misread bit is updated according to the misread bit. The memory management method described in item 7 of the scope of patent application, wherein the method further includes: Determine a second misread related factor according to a misreading bit threshold of the physical unit and the updated maximum misreading bit; Determine an updated threshold of the number of readings according to a threshold of the number of previous readings, a threshold of the number of presets, and the second reading error related factors; and Scan the physical unit when the updated reading times are not less than the updated reading times threshold. A memory storage device includes: A connection interface unit for coupling to a host system; A rewritable non-volatile memory module; and A memory control circuit unit coupled to the connection interface unit and the rewritable non-volatile memory module, The memory control circuit unit is used to read the physical unit and update the reading times of the physical unit, The memory control circuit unit is further used to scan the physical unit when the updated read count is not less than a read count threshold, and The memory control circuit unit is further used for adjusting the threshold of the number of reads according to the number of reads and read error bits. For the memory storage device described in claim 9, wherein the operation of the memory control circuit unit to adjust the threshold of the number of reads according to the number of reads and the number of misread bits includes: A first misread related factor is determined according to a misreading bit threshold and a maximum misreading bit of the physical unit. For the memory storage device described in claim 10, the operation of the memory control circuit unit to adjust the threshold of the read count according to the read count and the misread bit includes: The threshold of the number of readings is determined according to a threshold of the number of previous readings, a threshold of the number of readings, and the first reading error-related factors. According to the memory storage device described in claim 11, the memory control circuit unit determines the predetermined read count threshold according to the erasure count of the physical unit. In the memory storage device described in claim 9, wherein the operation of the memory control circuit unit to read the physical unit and update the read count of the physical unit includes: Obtain the misread bit of the physical unit. For the memory storage device described in item 13 of the scope of patent application, the operation of the memory control circuit unit to scan the physical unit when the updated read count is not less than the read count threshold includes: If the misread bit is greater than a misread bit threshold, copy the data in the physical unit to another physical unit; and If the misreading bit is not greater than the misreading bit threshold, the updated reading times are recorded. For the memory storage device described in the 13th scope of the patent application, the operation of obtaining the misread bit of the physical unit includes: If the misread bit is greater than a maximum misread bit, the maximum misread bit is updated according to the misread bit. For example, the memory storage device according to the scope of patent application, wherein the memory control circuit unit is further used for determining a second misread correlation according to a misread bit threshold of the physical unit and the updated maximum misread bit factor, The memory control circuit unit is further configured to determine an updated threshold for the number of reads according to a threshold for the number of previous reads, a threshold for the number of presets, and the second read error related factors, and The memory control circuit unit is further used to scan the physical unit when the updated read times are not less than the updated read times threshold. A memory control circuit unit for controlling a memory storage device including a rewritable non-volatile memory module, and the memory control circuit unit includes: A host interface for coupling to a host system; A memory interface for coupling to the rewritable non-volatile memory module; and A memory management circuit coupled to the host interface and the memory interface, The memory control circuit unit is used to read the physical unit and update the reading times of the physical unit, The memory control circuit unit is further used to scan the physical unit when the updated read count is not less than a read count threshold, and The memory control circuit unit is further used for adjusting the threshold of the number of reads according to the number of reads and read error bits. For the memory control circuit unit described in claim 17, wherein the operation of the memory control circuit unit to adjust the threshold of the number of reads according to the number of reads and the number of misread bits includes: A first misread related factor is determined according to a misreading bit threshold and a maximum misreading bit of the physical unit. For the memory control circuit unit described in item 18 of the scope of patent application, the operation of the memory control circuit unit to adjust the threshold of the read count according to the read count and the misread bit includes: The threshold of the number of readings is determined according to a threshold of the number of previous readings, a threshold of the number of readings, and the first reading error-related factors. According to the memory control circuit unit described in item 19 of the scope of patent application, the memory control circuit unit determines the preset read count threshold according to the erasing count of the physical unit. The memory control circuit unit according to claim 17, wherein the operation of the memory control circuit unit to read the physical unit and update the read count of the physical unit includes: Obtain the misread bit of the physical unit. For the memory control circuit unit described in item 21 of the scope of patent application, the operation of the memory control circuit unit to scan the physical unit when the updated read count is not less than the read count threshold includes: If the misread bit is greater than a misread bit threshold, copy the data in the physical unit to another physical unit; and If the misreading bit is not greater than the misreading bit threshold, the updated reading times are recorded. For the memory control circuit unit described in the 21st scope of the patent application, the operation of obtaining the misread bit of the physical unit includes: If the misread bit is greater than a maximum misread bit, the maximum misread bit is updated according to the misread bit. The memory control circuit unit according to the 23rd of the scope of patent application, wherein the memory control circuit unit is further used for determining a second read error according to a read error bit threshold of the physical unit and the updated maximum read error bit. relevant factors, The memory control circuit unit is further configured to determine an updated threshold for the number of reads according to a threshold for the number of previous reads, a threshold for the number of presets, and the second read error related factors, and The memory control circuit unit is further used to scan the physical unit when the updated read times are not less than the updated read times threshold.

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