TWI783710B - Protection circuit - Google Patents

Abstract

A protection circuit is provided. The protection circuit includes a detection circuit and a discharge circuit. The detection circuit is coupled to a first power pad and a second power pad and configured to detect whether an electrostatic discharge (ESD) event or an electrical overstress (EOS) event occurs at the first power pad. The detection circuit controls a detection voltage at a detection node according to a detection result. The first power pad and the second power pad belong to different power domains. The discharge circuit is coupled to the detection node and the first power pad. In response to the ESD event occurring at the first power pad, the discharge circuit provides a discharge path between the first power pad and a ground according to the detection voltage. In response to the EOS event occurring at the first power pad, the detection circuit enables a second discharge path between the first power pad and the ground.

Description

protect the circuit

The present invention relates to a protection circuit, in particular to a protection circuit for electrostatic discharge and excessive electrical stress.

Integrated circuits With the development of semiconductor manufacturing process, the size of components has been reduced to the sub-micron stage to improve the performance and operation speed of integrated circuits. However, the reduction of component sizes has caused some reliability problems, especially for integrated circuits. It has the greatest impact on the protection ability of electrostatic discharge (ESD). When the component size is reduced due to advanced process technology, the ESD protection ability is also greatly reduced, resulting in a significant decrease in the ESD tolerance of the component. Therefore, protection circuits are required to protect components from electrostatic discharge damage. However, existing protection circuits for ESD are not capable of coping with electrical overstress (EOS). Therefore, when an excessive electrical stress occurs on a bonding pad of the protection circuit, the excessive voltage will cause damage to components in the protection circuit, causing the protection circuit to lose its protection against ESD.

In view of this, the present invention proposes a protection circuit, which has a first power pad and a second power pad. The protection circuit includes a detection circuit and a discharge circuit. The detection circuit is coupled to the first power bonding pad and the second power bonding pad, and is used for detecting whether an electrostatic discharge event or an excessive electrical stress event occurs on the first power bonding pad. The protection circuit controls a detection voltage on a detection node according to a detection result. The first power bonding pad and the second power bonding pad belong to different power domains respectively. The discharge circuit is coupled to the detection node and the first power pad. When an electrostatic discharge event occurs on the first power pad, the discharge circuit provides a first discharge path between the first power pad and a ground terminal according to the detection voltage. When an excessive electrical stress event occurs on the first power pad, the detection circuit enables a second discharge path between the first power pad and the ground terminal.

The present invention further provides a protection circuit, which includes a detection circuit and a discharge circuit. The detection circuit includes a first transistor, a resistance element, and a second transistor. The first transistor has a first end coupled to a first power pad, a second end coupled to a first node, and a control end coupled to a second power pad. The first power bonding pad and the second power bonding pad belong to different power domains respectively. The resistance element is coupled between the first node and a ground terminal. The second transistor has a first terminal coupled to a detection node, a second terminal coupled to the ground terminal, and a control terminal coupled to the first node. The discharge circuit is coupled to the detection node and the first power pad, and includes a resistor, a third transistor, a fourth transistor, and a fifth transistor. The resistor is coupled between the first power pad and the detection node. The third transistor has a first end coupled to the first power pad, a second end coupled to a second node, and a control end coupled to the detection node. The fourth transistor has a first terminal coupled to the second node, a second terminal coupled to the ground terminal, and a control terminal coupled to the detection node. The fifth transistor has a first terminal coupled to the first power pad, a second terminal coupled to the ground terminal, and a control terminal coupled to the second node.

In order to make the above-mentioned purpose, features and advantages of the present invention more comprehensible, a preferred embodiment will be exemplified below and described in detail in conjunction with the accompanying drawings.

Figure 1 is a table showing a protection circuit according to an embodiment of the present invention. Referring to FIG. 1 , the protection circuit 1 includes a detection circuit 10 and a discharge circuit 11 . The protection circuit 1 further includes two power bonding pads PAD1 and PAD2. When the protection circuit 1 is in an operation mode, the power pads PAD1 and PAD2 belong to different voltage domains. The power supply voltages received by the power pads PAD1 and PAD2 will be described in detail later. The detection circuit 10 is coupled to the power pads PAD1 and PAD2. The discharge circuit 11 is coupled to the detection circuit 10 through the detection node N11, and is further coupled to the power pad PAD1.

The detection circuit 10 detects whether an electrostatic discharge (ESD) event or an electrical overstress (EOS) event occurs on the power bonding pad PAD1, and according to the occurrence of the electrostatic discharge event or the electrical overstress event The detection result is used to control the detection voltage on the detection node N11. When an electrostatic discharge event occurs on the power pad PAD1 , the discharge circuit 11 provides a discharge path between the power pad PAD1 and the ground terminal GND according to the detection voltage on the detection node N11 . When an excessive electrical stress event occurs on the power pad PAD1 , the detection circuit 10 enables at least one discharge path between the power pad PAD and the ground terminal GND. According to an embodiment of the present invention, the protection circuit 1 of the present invention not only provides protection for electrostatic discharge, but also provides protection for excessive electrical stress. The detailed circuit structure and operation of the protection circuit 1 will be described below.

As shown in FIG. 1 , the detection circuit 10 includes transistors 100 and 101 and a resistor 102 . In this embodiment, the transistor 100 is realized by a P-type Metal-Oxide-Semiconductor (PMOS) transistor, and the transistor 101 is realized by an N-type Metal-Oxide-Semiconductor (N-type Metal-Oxide-Semiconductor). -Semiconductor, NMOS) transistors to achieve. A first end (source) of the PMOS transistor 100 is coupled to the power pad PAD1, a second end (drain) thereof is coupled to the node N10, and a control end (gate) thereof is coupled to the power pad PAD2. A first terminal (drain) of the NMOS transistor 101 is coupled to the detection node N11, a second terminal (source) thereof is coupled to the ground terminal GND, and a control terminal (gate) thereof is coupled to the node N10. In this embodiment, the resistive element 102 includes a resistor R10. The resistor R10 is coupled between the node N10 and the ground terminal GND.

The discharge circuit 11 includes transistors 110 - 112 , a resistor 113 , and a capacitor 114 . The resistor 113 is coupled between the power pad PAD1 and the detection node N11. The capacitor 114 is coupled between the detection node N11 and the ground. In this embodiment, the transistor 110 is implemented as a PMOS transistor, and the transistors 111 - 112 are implemented as NMOS transistors. A first terminal of the PMOS transistor 110 is coupled to the power pad PAD1 , a second terminal thereof is coupled to the node N12 , and a control terminal thereof is coupled to the detection node N11 . A first terminal of the NMOS transistor 111 is coupled to the node N12 , a second terminal thereof is coupled to the ground terminal GND, and a control terminal thereof is coupled to the detection node N11 . A first terminal of the NMOS transistor 112 is coupled to the power pad PAD1 , a second terminal thereof is coupled to the ground terminal GND, and a control terminal thereof is coupled to the node N12 .

In the embodiment of FIG. 1 , the thickness of the gate oxide layer of the PMOS transistor 100 is preferably greater than the thickness of the gate oxide layer of the PMOS transistor 110 . Therefore, the gates of the PMOS transistors 100 and 110 are shown in different patterns, but the invention is not limited thereto. In other embodiments, the thickness of the gate oxide layer of the PMOS transistor 100 may be equal to or smaller than the thickness of the gate oxide layer of the PMOS transistor 110 .

Referring to FIG. 2, when the protection circuit 1 is operating normally in the operating mode, one operating voltage is provided to the power bonding pad PAD1, and the other operating voltage is provided to the power bonding pad PAD2, and the ground terminal GND has a ground voltage (for example, 0 volts ( V)). In this embodiment, the operating voltage supplied to the power pad PAD2 is greater than or equal to the operating voltage supplied to the power pad PAD1, for example, the operating voltage supplied to the power pad PAD1 is 18V and the operation voltage supplied to the power pad PAD2 The voltage is 24V. Therefore, the voltage VP1 of the power pad PAD1 is 18V, and the voltage VP2 of the power pad PAD2 is 24V.

Based on the voltages VP1 and VP2, the PMOS transistor 100 is turned off. In Figure 2 and subsequent figures, transistors that are turned off will be marked with "(OFF)". At this time, since the PMOS transistor 100 is turned off and the resistor R10 is coupled to the ground terminal GND, the voltage V10 on the node N10 is at a low level. Referring to FIG. 4, the voltage V10 is approximately the voltage level (0V) of the ground terminal GND. According to the voltage V10 of 0V, the NMOS transistor 101 is turned off (OFF). In addition, in response to the voltage VP1 , the detection voltage V11 on the detection node N11 is approximately equal to the voltage VP1 . For example, referring to FIG. 4 , the detection voltage V11 is approximately equal to 18V (V11≈18V). According to the detection voltage V11 of about 18V, the PMOS transistor 110 is turned off (OFF), and the NMOS transistor 111 is turned on (ON). In Figure 2 and subsequent figures, a transistor that is turned on will be marked with "(ON)". Since the NMOS transistor 111 is turned on, the voltage V12 on the node N12 is close to or equal to the voltage level (0V) of the ground terminal GND, so that the NMOS transistor 112 is turned off (OFF).

According to the above, when the protection circuit 1 operates normally in the operation mode, the transistors 100 and 101 of the detection circuit 10 are turned off, so that the detection voltage V11 on the detection node N11 has a level of about 18V. According to the detection voltage V11, the transistors 110 and 112 of the discharge circuit 11 are both turned off. Therefore, the detection circuit 10 does not provide any circuit path between the power pad PAD1 and the ground terminal GND, and the discharge circuit 11 does not provide any circuit path between the power pad PAD1 and the ground terminal GND.

During normal operation, if the power pad PAD1 encounters excessive electrical stress (ie, an excessive electrical stress event occurs on the power pad PAD1 ), the voltage VP1 of the power pad PAD1 rises. Referring to FIGS. 3 and 4 , for example, when an excessive electrical stress event occurs on the power pad PAD1 , the voltage VP of the power pad PAD1 rises to 30V. Based on the voltages VP1 and VP2 , the PMOS transistor 100 is turned on (ON). Since the PMOS transistor 100 is turned on, a detection path P10 is formed between the power pad PAD1 and the ground terminal GND, that is, the detection circuit 10 enables the detection path P10 through the conduction of the PMOS transistor 100 . At this time, since the PMOS transistor 100 is turned on, the voltage V10 on the node N10 rises. Referring to Figure 4, when the voltage VP1 rises to 30V, the voltage V10 also rises. In this embodiment, according to the size of the PMOS transistor 100 and the resistance value of the resistor R10, in one embodiment, the raised level of the voltage V10 is lower than the detection voltage V11, for example, the voltage V10 is approximately less than or equal to 5V.

In response to the rise of the voltage V10, the NMOS transistor 101 is turned on (ON). Since the NMOS transistor 101 is turned on, a discharge path P11 is formed between the power pad PAD1 and the ground terminal GND, that is, the detection circuit 10 enables the discharge path P11 through the conduction of the NMOS transistor 101 . Through the voltage dividing operation realized by the resistor 113 and the turned-on NMOS transistor 101 , the detection voltage V11 on the detection node N11 is approximately equal to a predetermined voltage. In this embodiment, the preset voltage must be lower than the breakdown voltage of the NMOS transistor 111 (for example, 26V). By adjusting the resistance value of the resistor 113 and the size of the NMOS transistor 101 , the above-mentioned preset voltage can be equal to 18V, that is, the detection voltage V11 is approximately equal to 18V. Referring to FIG. 4, when the voltage VP1 rises to 30V, the detection voltage V11 is approximately equal to 18V (V11≈18V).

In response to the voltage VP1 of 30V and the detection voltage V11 of about 18V, the PMOS transistor 110 is turned on (ON). In addition, according to the detection voltage V11 of 18V, the NMOS transistor 111 is also turned on (ON). Therefore, the voltage V12 on the node N12 rises through the voltage dividing operation realized by the turned-on transistors 110 and 111 . Referring to FIG. 4, when the voltage VP rises to 30V, the voltage V12 also rises. In this embodiment, according to the sizes of the PMOS transistor 110 and the NMOS transistor 111, the voltage V12 rises to a level lower than the detection voltage V11 For example, the voltage V12 is approximately less than or equal to 5V. In response to the detection voltage V12, the NMOS transistor 112 is turned on (ON) to provide a discharge path P12 between the power pad PAD1 and the ground terminal GND.

According to the above, when an excessive electrical stress event occurs on the power pad PAD1 in the operation mode, the transistors 100 and 101 of the detection circuit 10 are both turned on, so that a detection path is formed between the power pad PAD1 and the ground terminal GND P10 and discharge path P11. The charge on the power pad PAD1 is conducted to the ground terminal GND through the detection path P10 and the discharge path P11 . In addition, through the resistor 113 and the NMOS transistor 101, the detection voltage V11 on the detection node N11 is approximately equal to the preset voltage, which will not be too high to damage the components in the discharge circuit 11, especially the capacitor 114 and the NMOS transistor. Crystal 111. In addition, the NMOS transistor 112 is also turned on. Therefore, when an excessive electrical stress event occurs on the power pad PAD1 , the discharge circuit 11 also provides a discharge path P12 between the power pad PAD1 and the ground terminal GND.

Referring to FIG. 4 , it can be seen that when the excessive electrical stress event disappears, the voltage VP1 of the power pad PAD1 recovers to 24V, and the protection circuit 1 resumes normal operation. At this time, the voltages V10 and V12 decrease to be close to or equal to the voltage level (0V) of the ground terminal GND, and the detection voltage V11 is approximately equal to 18V in response to the voltage VP1.

Referring to FIG. 5, when the protection circuit 1 is not in the operation mode, the operating voltage is not supplied to the power pads PAD1 and PAD2, that is, the power pads PAD1 and PAD2 are in a floating state or their voltages VP1 and VP2 are equal to 0V . When an ESD event (for example, a positive ESD event) occurs on the power pad PAD1 , the voltage VP of the power pad PAD1 increases instantaneously. At this time, since the power pad PAD2 is in a floating state or its voltage VP2 is equal to 0V, the PMOS transistor 100 is turned on (ON). Since the PMOS transistor 100 is turned on, the voltage V10 on the node N10 increases instantaneously along with the voltage VP1.

In response to the instantaneous increase of the voltage V10, the NMOS transistor 101 is turned on (ON). Based on the device characteristics of the capacitor 114 , the detection voltage V11 does not rise instantaneously with VP1 , and the detection voltage V11 on the detection node N11 is pulled down by the turned-on NMOS transistor 101 . At this time, according to the detection voltage V11, the PMOS transistor 110 is turned on (ON), and the NMOS transistor 111 is turned off (OFF). Through the turned-on PMOS transistor 110 , the voltage V12 on the node N12 increases instantaneously along with the voltage VP1 to turn on the NMOS transistor 112 . Due to the conduction of the NMOS transistor 112, a discharge path P12 is formed between the power pad PAD1 and the ground terminal GND, so that the electrostatic charge on the power pad PAD1 is conducted to the ground terminal GND through the discharge path P12, thereby This protects components in other circuits coupled to the power pad PAD1 from being damaged by electrostatic charges.

According to the above, when an electrostatic discharge event occurs on the power pad PAD1, the transistors 100 and 101 of the detection circuit 10 are both turned on, so that the detection voltage V11 can be at a low level (close to or equal to the voltage level of the ground terminal GND (0V)), thereby enabling the formation of the discharge path P12.

In addition, compared with the electrostatic discharge protection circuit that only has the discharge circuit 11 (but does not have the detection circuit 10), when an electrostatic discharge event occurs on the power pad PAD1, through the operation of the detection circuit 10 of this case, the detection The voltage V11 has a lower level, and the voltage V12 has a higher level.

Referring to FIGS. 6A~6B, when an electrostatic discharge event occurs on the power bonding pad PAD1, the changes of the detected voltage V11 and the voltage V12 of the electrostatic discharge protection circuit having only the discharge circuit 11 are represented by curves 60 and 62, respectively, and The changes of the detection voltage V11 and the voltage V12 of the protection circuit 1 in this case are represented by curves 61 and 63 respectively. By comparing curves 60 and 61 and comparing curves 62 and 63, it can be seen that the level of the detection circuit V11 in this case is low, so that the PMOS transistor 110 can be completely turned on, and the level of the circuit V12 in this case is high, so that the NMOS transistor 110 can be completely turned on. The crystal 112 can be fully turned on, thereby providing a stable discharge path P12.

According to the embodiment shown in FIG. 1 , the protection circuit 1 of the present application can not only provide electrostatic discharge protection, but also provide excessive electrical stress protection. By coupling the power pads PAD1 and PDA2 of different power domains, when the detection circuit 10 detects an electrostatic discharge event or an excessive electrical stress on the power pad PDA1, the transistors 100 and 101 in the detection circuit 10 In the ON state, it indicates the detection result. According to the detection result, the detection circuit 10 controls the detection node N11 to have different voltages and enables at least one discharge path.

In detail, when the detection circuit 10 detects that an excessive electrical stress event occurs on the power pad PDA1, it controls the detection voltage V11 on the detection node N11 to be lower than the breakdown voltage of the NMOS transistor 111 (for example, , 26V) level (for example, 18V), and enables the detection path P10 passing through the PMOS transistor 100, the node N10, and the resistor R11, passing through the resistor 113, the detecting node N11, and the NMOS transistor 101 The discharge path P11 and the discharge path P12 passing through the NMOS transistor 112 (shown in FIG. 3 ). When the detection circuit 10 detects that an electrostatic discharge event occurs on the power pad PDA1, it controls the detection voltage V11 on the detection node N11 to be at a low level (close to or equal to the voltage level (0V) of the ground terminal GND) , and enable the discharge path P12 (shown in FIG. 5 ) through the NMOS transistor 112 .

According to the relevant description of FIG. 5 , the capacitor 114 is used to prevent the detection voltage V11 from rising instantaneously with VP1 to be at a low level when an electrostatic discharge event occurs on the power pad PAD1 . According to the operation of the detection circuit 10 in this case, when an electrostatic discharge event occurs, the detection circuit 10 can pull down the detection voltage V11 , that is, the detection voltage V11 will not increase instantaneously with VP1 . Thus, in other embodiments, capacitor 114 may be omitted.

Referring to FIG. 7 , the discharge circuit 11 does not include the capacitor 114 , which can reduce the area of the protection circuit 1 . Even though the discharge circuit 11 does not include the capacitor 114 , due to the operation of the detection circuit 10 , the detection voltage V11 can still be at a low level when an ESD event occurs. For the operation of the protection circuit 1 in Fig. 7, please refer to the related descriptions in Figs. 1 to 6A, which are omitted here.

In the above-mentioned embodiments, the resistance element 102 is realized by a resistor R10. In other embodiments, the resistive element 102 can be realized by other elements capable of providing impedance.

Referring to FIG. 8 , the resistive element 102 includes an NMOS transistor 90 . The first terminal of the NMOS transistor 90 is coupled to the node N10 , the second terminal thereof is coupled to the ground terminal GND, and the control terminal thereof is coupled to the power pad PAD2 . For the connection structure of other components of the protection circuit 1 in FIG. 8 , please refer to the related description in FIG. 1 , which is omitted here. Referring to FIG. 9, when the protection circuit 1 is operating normally in the operation mode, one operating voltage is provided to the power bonding pad PAD1, another operating voltage is provided to the power bonding pad PAD2, and the ground terminal GND has a ground voltage (for example, 0 volts ( V)). For example, the operating voltage provided to the power pad PAD1 is 18V and the operating voltage provided to the power pad PAD2 is 24V. Therefore, the voltage VP1 of the power pad PAD1 is 18V, and the voltage VP2 of the power pad PAD2 is 24V.

Based on the voltages VP1 and VP2, the PMOS transistor 100 is turned off (OFF). In addition, the NMOS transistor 90 is turned on (ON) in response to the voltage VP2. At this time, the voltage V10 on the node N10 is pulled down to 0 (0V) which is approximately the voltage level of the ground terminal GND through the turned-on NMOS transistor 90 , so that the NMOS transistor 101 is turned off (OFF). In addition, in response to the voltage VP1 , the detection voltage V11 on the detection node N11 is approximately equal to the voltage VP1 , for example, the detection voltage V11 is approximately equal to 18V. According to the detection voltage V11, the PMOS transistor 110 is turned off (OFF), and the NMOS transistor 111 is turned on (ON). Through the turned-on NMOS transistor 111 , the voltage V12 on the node N12 is close to or equal to the voltage level (0V) of the ground terminal GND, so that the NMOS transistor 112 is turned off (OFF).

According to the above, when the protection circuit 1 operates normally in the operation mode, the transistors 100 and 101 of the detection circuit 10 are turned off, and in addition, the transistors 110 and 112 of the discharge circuit 11 are also turned off. Therefore, the detection circuit 10 does not provide any circuit path between the power pad PAD1 and the ground terminal GND, and the discharge circuit 11 does not provide any circuit path between the power pad PAD1 and the ground terminal GND.

Referring to FIG. 10, during normal operation, if an electrical overstress event occurs on the power pad PAD1, the voltage VP1 of the power pad PAD1 rises to, for example, 30V. Based on the voltages VP1 and VP2 , the PMOS transistor 100 is turned on (ON). In addition, the NMOS transistor 90 is turned on (ON) in response to the voltage VP2. Since both the PMOS transistor 100 and the NMOS transistor 90 are turned on, a detection path P10 is formed between the power pad PAD1 and the ground terminal GND, that is, the detection circuit 10 is enabled through the conduction of the PMOS transistor 100 Detection path P10. The detection path P10 passes through the PMOS transistor 100 , the node N10 , and the NMOS transistor 90 . At this moment, through the voltage division operation realized by the turned-on PMOS transistor 100 and the NMOS transistor 90 , the voltage V10 on the node N10 rises to turn on the NMOS transistor 101 (ON).

Since the NMOS transistor 101 is turned on, a discharge path P11 is formed between the power pad PAD1 and the ground terminal GND, that is, the detection circuit 10 enables the discharge path P11 through the conduction of the NMOS transistor 101 . The discharge path P11 passes through the resistor 113 , the detection node N11 , and the NMOS transistor 101 . Through the voltage division operation realized by the resistor 113 and the turned-on NMOS transistor 101 , the detection voltage V11 is approximately equal to a predetermined voltage. By adjusting the resistance of the resistor 113 and the size of the NMOS transistor 101 , the preset voltage can be made equal to 18V, which is lower than the breakdown voltage of the NMOS transistor 111 (eg, 26V). In response to the voltage VP1 of 30V and the detection voltage V11 of about 18V, the PMOS transistor 110 is turned on (ON). In addition, according to the detection voltage V11 of 18V, the NMOS transistor 111 is also turned on (ON). Therefore, through the voltage dividing operation realized by the turned-on transistors 110 and 111, the voltage V12 on the node N12 rises, so that the NMOS transistor 112 is turned on (ON) to provide a discharge between the power pad PAD1 and the ground terminal GND Path P12.

According to the above, when an excessive electrical stress event occurs on the power pad PAD1 in the operation mode, the transistors 100, 101, and 90 of the detection circuit 10 are all turned on, so that a power supply pad PAD1 and the ground terminal GND are formed. The detection path P10 and the discharge path P11. The charge on the power pad PAD1 is conducted to the ground terminal GND through the detection path P10 and the discharge path P11 . In addition, through the resistor 113 and the NMOS transistor 101, the detection voltage V11 on the detection node N11 is approximately equal to the preset voltage, which will not be too high to damage the components in the discharge circuit 11, especially the capacitor 114 and the NMOS transistor. Crystal 111. In addition, the NMOS transistor 112 is also turned on. Therefore, when an excessive electrical stress event occurs on the power pad PAD1 , the discharge circuit 11 also provides a discharge path P12 between the power pad PAD1 and the ground terminal GND.

Referring to FIG. 11, when the protection circuit 1 is not in the operation mode, the operating voltage is not supplied to the power pads PAD1 and PAD2, that is, the power pads PAD1 and PAD2 are in a floating state or their voltages VP1 and VP2 are equal to 0V . When an electrostatic discharge event occurs on the power pad PAD1 , the voltage VP of the power pad PAD1 increases instantaneously. At this time, since the power pad PAD2 is in a floating state or its voltage VP2 is equal to 0V, the PMOS transistor 100 is turned on (ON), and the NMOS transistor 90 is turned off (OFF). Through the turned-on PMOS transistor 100, the voltage V10 on the node N10 increases instantaneously along with the voltage VP1.

In response to the instantaneous increase of the voltage V10, the NMOS transistor 101 is turned on (ON). Based on the device characteristics of the capacitor 114 , the detection voltage V11 does not rise instantaneously with VP1 , and the detection voltage V11 on the detection node N11 is pulled down by the turned-on NMOS transistor 101 . At this time, according to the detection voltage V11, the PMOS transistor 110 is turned on (ON), and the NMOS transistor 111 is turned off (OFF). Through the turned-on PMOS transistor 110 , the voltage V12 on the node N12 increases instantaneously along with the voltage VP1 to turn on the NMOS transistor 112 . Due to the conduction of the NMOS transistor 112, a discharge path P12 is formed between the power pad PAD1 and the ground terminal GND, so that the electrostatic charge on the power pad PAD1 is conducted to the ground terminal GND through the discharge path P12, thereby This protects components in other circuits coupled to the power pad PAD1 from being damaged by electrostatic charges.

According to the above, when an electrostatic discharge event occurs on the power pad PAD1, the transistors 100 and 101 of the detection circuit 10 are both turned on and the transistor 90 is turned off, so that the detection voltage V11 can be at a low level (close to or equal to ground The voltage level of the terminal GND (0V)), thereby enabling the formation of the discharge path P12.

According to the above, the protection circuit 1 of FIG. 8 can not only provide ESD protection, but also provide protection against electrical overstress. By coupling the power pads PAD1 and PDA2 of different power domains, when the detection circuit 10 detects an electrostatic discharge event or an excessive electrical stress on the power pad PDA1, the transistors 100 and 101 in the detection circuit 10 In the ON state, it indicates the detection result. According to the detection result, the detection circuit 10 controls the detection node N11 to have different voltages and enables at least one discharge path.

In detail, when the detection circuit 10 detects that an excessive electrical stress event occurs on the power pad PDA1, it controls the detection voltage V11 on the detection node N11 to be lower than the breakdown voltage of the NMOS transistor 111 (for example, , 26V) level (for example, 18V), and enables the detection path P10 passing through the PMOS transistor 100, the node N10, and the resistor R11, passing through the resistor 113, the detecting node N11, and the NMOS transistor 101 The discharge path P11 and the discharge path P12 passing through the NMOS transistor 112 (shown in FIG. 10 ). When the detection circuit 10 detects that an electrostatic discharge event occurs on the power pad PDA1, it controls the detection voltage V11 on the detection node N11 to be at a low level (close to or equal to the voltage level (0V) of the ground terminal GND) , and enable the discharge path P12 (shown in FIG. 11 ) through the NMOS transistor 112 .

In the embodiment shown in FIG. 8 , the thickness of the gate oxide layer of the PMOS transistor 100 is greater than the thickness of the gate oxide layer of the PMOS transistor 110 , but the invention is not limited thereto. In other embodiments based on the circuit structure of FIG. 8 , the thickness of the gate oxide layer of the PMOS transistor 100 may be equal to or smaller than the thickness of the gate oxide layer of the PMOS transistor 110 .

In addition, in the embodiment of FIG. 8, the discharge circuit 11 may not include the capacitor 114, so that the protection circuit 1 occupies a smaller area. Even though the discharge circuit 11 does not include the capacitor 114 , due to the operation of the detection circuit 10 , when an ESD event occurs, the detection voltage V11 can be at a low level through the turned-on NMOS transistor 101 to enable the formation of the discharge path P12 .

In the above embodiments, when the protection circuit 1 enters the operation mode, two different operation voltages can be provided to the power pads PAD1 and PAD2 at the same time. In other embodiments, when the protection circuit 1 enters the operation mode, two different operating voltages can be provided to the power pads PAD1 and PAD2 successively, for example, one operating voltage is provided to the power pad PAD2 first, and then another operation voltage is provided. Voltage to Power Bonding Pad PAD1. In this way, when the protection circuit 1 enters the operation mode, the voltage VP2 of the power pad PAD2 is at a high level at the first time to turn off the PMOS transistor 100 , thereby avoiding the leakage current through the PMOS transistor 100 .

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Anyone skilled in this art can make changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be subject to what is defined in the scope of the attached patent application.

1: Protection circuit

10: Detection circuit

11: Discharge circuit

60~63: curve

90: NMOS transistor

100: PMOS transistor

101: NMOS transistor

102: Impedance element

110: PMOS transistor

111,112: NMOS transistor

113: Resistor

114: Capacitor

GND: ground terminal

N10, N12: nodes

N11: detection node

P10: Detection path

P11, P12: discharge path

PAD1,PAD2: power bonding pads

R10: Resistor

V10, V12: Voltage

V11: detection voltage

VP1, VP2: Voltage

Fig. 1 shows a protection circuit of an embodiment of the present invention. FIG. 2 is a schematic diagram showing the normal operation of the protection circuit in FIG. 1 in the operation mode. FIG. 3 is a schematic diagram showing the operation of the protection circuit in FIG. 1 when it encounters an electrical overstress event in the operation mode. FIG. 4 is a schematic diagram showing the main voltages of the protection circuit in FIG. 1 in normal operation and when it encounters an electrical overstress event. FIG. 5 is a schematic diagram showing the operation of the protection circuit in FIG. 1 when it encounters an electrostatic discharge event. Figures 6A-6B are schematic diagrams showing main voltages when the protection circuit in Figure 1 encounters an electrostatic discharge event. Fig. 7 shows a protection circuit of another embodiment of the present invention. Fig. 8 shows a protection circuit of another embodiment of the present invention. FIG. 9 is a schematic diagram showing the normal operation of the protection circuit in FIG. 8 in the operation mode. FIG. 10 is a schematic diagram showing the operation of the protection circuit in FIG. 8 when it encounters an electrical overstress event in the operation mode. FIG. 11 is a schematic diagram showing the operation of the protection circuit in FIG. 8 when it encounters an electrostatic discharge event.

1: Protection circuit

10: Detection circuit

11: Discharge circuit

100: PMOS transistor

101: NMOS transistor

102: Impedance element

110: PMOS transistor

111,112: NMOS transistor

102: Impedance element

113: Resistor

114: Capacitor

GND: ground terminal

N10, N12: nodes

N11: detection node

PAD1,PAD2: power bonding pads

R10: Resistor

Claims (20)

A protection circuit having a first power supply pad and a second power supply pad, comprising: a detection circuit coupled to the first power supply pad and the second power supply pad for detecting Whether an electrostatic discharge event or an excessive electrical stress event occurs on a power pad, and controlling a detection voltage on a detection node according to a detection result, wherein the first power pad is connected to the second power pad The pads belong to different power domains; and a discharge circuit is coupled to the detection node and the first power pad; wherein, when the electrostatic discharge event occurs on the first power pad, the discharge circuit according to the detection measuring voltage to provide a first discharge path between the first power pad and a ground; and wherein the detection circuit is enabled when the electrical overstress event occurs on the first power pad A second discharge path between the first power pad and the ground terminal. The protection circuit of claim 1, wherein when the excessive electrical stress event occurs on the first power pad, the discharge circuit provides the first discharge path according to the detection voltage. The protection circuit of claim 1, wherein: when the protection circuit operates in an operation mode, the first power pad receives a first voltage, and the second power pad receives a second voltage; and the second The voltage is greater than or equal to the first voltage. The protection circuit of claim 3, wherein the second voltage is provided to The second power pad is supplied to the first power pad earlier than the first voltage. The protection circuit of claim 3, wherein when the protection circuit is not in the operation mode, the first power pad does not receive the first voltage, and the second power pad is floating or receives a voltage of zero volts. The protection circuit according to claim 1, wherein the detection circuit includes: a first transistor having a first end coupled to the first power pad, a second end coupled to a first node, and a control terminal coupled to the second power pad; a resistance element coupled between the first node and the ground terminal; and a second transistor having a first terminal coupled to the detection node , a second terminal coupled to the ground terminal, and a control terminal coupled to the first node. The protection circuit of claim 6, wherein: the discharge circuit includes a resistor coupled between the first power pad and the detection node; and when the excessive electrical stress occurs on the first power pad event, the second discharge path passes through the resistor, the detection node, and the second transistor. The protection circuit according to claim 7, wherein when the electrical overstress event occurs on the first power pad, the detection circuit is further capable of enabling a contact between the first power pad and the ground terminal a detection path, and the detection path passes through the first transistor, the first node, and the resistance element. The protection circuit of claim 6, wherein the resistive element comprises a resistor. The protection circuit according to claim 6, wherein the resistance element includes a third transistor, and the third transistor has a first end coupled to the first node, coupled to A second end connected to the ground end, and a control end coupled to the second power pad. A protection circuit, comprising: a detection circuit, including: a first transistor, having a first end coupled to a first power pad, a second end coupled to a first node, and a first end coupled to a a control terminal of the second power pad, wherein the first power pad and the second power pad respectively belong to different power domains; a resistance element coupled between the first node and a ground terminal; and a second transistor having a first terminal coupled to a detection node, a second terminal coupled to the ground terminal, and a control terminal coupled to the first node; and a discharge circuit coupled to the The detection node and the first power supply pad, and includes: a resistor coupled between the first power supply pad and the detection node; a third transistor with a coupling to the first power supply pad a first terminal coupled to a second node, a second terminal coupled to the detection node, and a control terminal coupled to the detection node; a fourth transistor has a first terminal coupled to the second node, coupled to a second end connected to the ground end, and a control end coupled to the detection node; and a fifth transistor, having a first end coupled to the first power pad, a first end coupled to the ground end two terminals, and a control terminal coupled to the second node. The protection circuit of claim 11, wherein: when an electrostatic discharge event occurs on the first power supply pad, the fifth transistor is turned on; and in an operation mode of the protection circuit, when the first power supply is connected to When an excessive electrical stress event occurs on the pad, the first transistor and the second transistor are turned on. The protection circuit according to claim 12, wherein, when the first power supply When the excessive electrical stress event occurs on the bonding pad, the fifth transistor is turned on. The protection circuit of claim 12, wherein: when the protection circuit is in the operation mode, the first power pad receives a first voltage, and the second power pad receives a second voltage; and the second voltage greater than or equal to the first voltage. The protection circuit according to claim 14, wherein the second voltage is supplied to the second power pad earlier than the first voltage is supplied to the first power pad. The protection circuit of claim 14, wherein when the protection circuit is not in the operation mode, the first power pad does not receive the first voltage, and the second power pad is floating or receives a voltage of zero volts. The protection circuit according to claim 11, wherein the discharge circuit further includes: a capacitor coupled between the detection node and the ground terminal. The protection circuit according to claim 11, wherein the thickness of the gate oxide layer of the first transistor is greater than the thickness of the gate oxide layer of the third transistor. The protection circuit of claim 11, wherein the resistive element comprises a resistor. The protection circuit according to claim 11, wherein the resistance element includes a sixth transistor, and the sixth transistor has a first end coupled to the first node, a second end coupled to the ground end, and a control terminal coupled to the second power pad.

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