TWI783497B - 碳化矽複合晶圓及其製造方法 - Google Patents

碳化矽複合晶圓及其製造方法 Download PDF

Info

Publication number
TWI783497B
TWI783497B TW110118804A TW110118804A TWI783497B TW I783497 B TWI783497 B TW I783497B TW 110118804 A TW110118804 A TW 110118804A TW 110118804 A TW110118804 A TW 110118804A TW I783497 B TWI783497 B TW I783497B
Authority
TW
Taiwan
Prior art keywords
silicon carbide
wafer
substrate
composite wafer
acid
Prior art date
Application number
TW110118804A
Other languages
English (en)
Other versions
TW202246599A (zh
Inventor
曾彥凱
江柏萱
Original Assignee
鴻創應用科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 鴻創應用科技有限公司 filed Critical 鴻創應用科技有限公司
Priority to TW110118804A priority Critical patent/TWI783497B/zh
Priority to JP2021149274A priority patent/JP7347845B2/ja
Priority to US17/499,226 priority patent/US20220384385A1/en
Priority to EP21212892.0A priority patent/EP4095291A1/en
Application granted granted Critical
Publication of TWI783497B publication Critical patent/TWI783497B/zh
Publication of TW202246599A publication Critical patent/TW202246599A/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/36—Carbides
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • C30B33/06—Joining of crystals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/08225—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80009—Pre-treatment of the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/802—Applying energy for connecting
    • H01L2224/80236—Applying energy for connecting using electro-static corona discharge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8038—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/80399—Material
    • H01L2224/80486—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2224/80487—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8038—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/80399—Material
    • H01L2224/80486—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2224/80488—Glasses, e.g. amorphous oxides, nitrides or fluorides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1027—IV
    • H01L2924/10272—Silicon Carbide [SiC]

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Organic Chemistry (AREA)
  • Metallurgy (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

本發明為一種碳化矽複合晶圓及其製造方法，適用於半導體製程程序、電子產品及半導體設備所需。該碳化矽複合晶圓包含 (a) 一碳化矽材料及(b) 一晶圓基底，該晶圓基底之上表面結合於該碳化矽材料之下表面，其中，該碳化矽材料之下表面及該晶圓基底之上表面兩者或任一係經表面改質，使該碳化矽材料與該晶圓基底直接緊密接合。本發明之功效在於該複合晶圓不同材料間接合處之接合能力強，後續加工處理較容易，材料間彼此緊密結合的狀態下能縮短製程並且提高良率，產業利用性高。

Description

碳化矽複合晶圓及其製造方法
本發明係一種碳化矽複合晶圓及其製造方法，可用於半導體製程。
隨著通訊高頻化的趨勢，使得相關通訊元件性能急需提升以因應市場的需求，因此，能夠薄層化的晶圓或複合晶圓成為經濟實惠的選擇。已知的複合晶圓，係於底層基板晶圓上，以氣相法形成種結晶膜後，再生長GaN層；或是，可使用HVPE(混合氣相磊晶法)於底層基板晶圓上形成種結晶層。但對於複合晶圓無論是材料或製程仍有進一步的需求。
習知複合晶圓的製程，該基底與上方材料的接合處需要形成薄膜，才能使得該兩種不同的材料緊密接合，該製程複雜而耗時。是以，為了解決上述缺點，本發明人開始著手於複合晶圓製程上的改良。
本發明之目的為提供一種碳化矽複合晶圓，包含(a) 一碳化矽材料及(b) 一晶圓基底，該晶圓基底之上表面結合於該碳化矽材料之下表面，其中，該碳化矽材料之下表面之及該晶圓基底之上表面兩者或任一係經表面改質，使該碳化矽材料與該晶圓基底直接接合。
進一步地，如所述之碳化矽複合晶圓，其中，該晶圓基底係陶瓷或玻璃。
進一步地，如所述之碳化矽複合晶圓，其中，該陶瓷係選自由氮化鋁、氧化鋁、碳化矽及氮化矽所組成之群組。
進一步地，如所述之碳化矽複合晶圓，其中，該晶圓基底為單晶或多晶材料。
進一步地，如所述之碳化矽複合晶圓，其中，該碳化矽材料之厚度為0.2~500μm。
進一步地，如所述之碳化矽複合晶圓，其中該碳化矽材料之上表面進一步包含結晶層。
進一步地，如所述之碳化矽複合晶圓，其中該表面改質係表面產生靜電或氫鍵或物理鍵結；於較佳實施態樣中，該物理鍵結為凡德瓦力、庫倫力或摩擦力。
本發明之另一目的為提供一種碳化矽複合晶圓之製造方法，其包含下列步驟：(a) 一碳化矽經長晶處理為一碳化矽材料；及(b) 提供一晶圓基底，將該碳化矽材料之下表面及該晶圓基底之上表面兩者或任一者係經表面改質產生氫鍵或靜電或物理鍵結後，直接接合形成一碳化矽複合晶圓。
進一步地，如所述之製造方法，其中，該表面改質係經氫氟酸或其他包含氫原子液體浸泡處理使該碳化矽材料之下表面及該晶圓基底之上表面兩者或任一產生氫鍵。
進一步地，如所述之製造方法，其中，該碳化矽材料與晶圓基底以靜電結合。
相較於習知技術，本發明之碳化矽複合晶圓因該基底為陶瓷或玻璃材料，因此具有高介電常數、絕緣性、高熱傳導率、耐熱性及散熱性佳及特別係在高濕度下具有穩定性能等特性，且由於本發明之製造方法為碳化矽材料與晶圓基底直接接合，接合能力較佳，且無須如同先前技術必須於接合形成薄膜才能使得該兩種不同的材料緊密接合，因此本發明之製程更為簡潔便利。
以下實施方式不應視為過度地限制本發明。本發明所屬技術領域中具有通常知識者可在不背離本發明之精神或範疇的情況下對本文所討論之實施例進行修改及變化，而仍屬於本發明之範圍。
本文中所稱之「包含或包括」意指不排除一或多個其他組件、步驟、操作和/或元素的存在或添加至所述之組件、步驟、操作和/或元素。「約或接近」或「基本上」意指具有接近於允許指定誤差的數值或範圍，以避免被任何不合理之第三方，違法或不公平的使用為理解本發明揭示之精確或絕對數值。「一」意指該物的語法對象為一或一個以上(即，至少為一)。
本發明提供一種碳化矽複合晶圓，包含(a) 一碳化矽材料及(b) 一晶圓基底，該晶圓基底之上表面結合於該碳化矽材料之下表面，其中，該碳化矽材料之下表面之及該晶圓基底之上表面兩者或任一係經表面改質，使該碳化矽材料與該晶圓基底直接接合。
本發明另一提供一種碳化矽複合晶圓之製造方法，其包含下列步驟：(a) 一碳化矽經長晶處理為一碳化矽材料；及(b) 提供一晶圓基底，將該碳化矽材料之下表面及該晶圓基底之上表面兩者或任一者係經表面改質產生氫鍵或靜電後，直接接合形成一碳化矽複合晶圓。
請參見圖1，為本發明之碳化矽複合晶圓示意圖。該碳化矽複合晶圓1為晶圓基底12與碳化矽材料11直接接合而成，該晶圓基底12與碳化矽材料11之間不存在額外的薄膜結構而僅為兩者直接接合的接觸面111。進一步地，該碳化矽材料11上方可視需求再包含一結晶層13。
前述之晶圓基底12，於一較佳實施例中係為陶瓷或玻璃，其中該「陶瓷」係指金屬與非金屬的化合物，經人為高溫處理的無機非金屬固體材料，包括矽酸鹽、氧化物、碳化物、氮化物、硫化物、硼化物等，較佳包含但不限於係選自由氮化鋁、氧化鋁、碳化矽及氮化矽所組成的群組。例如所述之基底，該陶瓷選自氮化鋁、氧化鋁、碳化矽及氮化矽；所述之基底，該陶瓷選自氮化鋁、氧化鋁及碳化矽；所述之基底，該陶瓷選自氧化鋁、碳化矽及氮化矽；所述之基底，該陶瓷選自氮化鋁、碳化矽及氮化矽；所述之基底，該陶瓷選自氮化鋁及氧化鋁；所述之基底，該陶瓷選自氮化鋁及碳化矽；所述之基底，該陶瓷選自氮化鋁及氮化矽；所述之基底，該陶瓷選自氧化鋁及碳化矽；所述之基底，該陶瓷選自氧化鋁及氮化矽；所述之基底，該陶瓷選自碳化矽及氮化矽；所述之基底，該陶瓷選自氮化鋁；所述之基底，該陶瓷選自氧化鋁；所述之基底，該陶瓷選自碳化矽；所述之基底，該陶瓷選自氮化矽。
本文所述之「單晶或多晶材料」係指單晶向和多晶向材料。其差異為當熔融的單質材料凝固時，原子以金剛石晶格排列成許多晶核，若該晶核長成晶面取向相同的晶粒，則形成單晶材料；反之，若該晶核長成晶面取向不同的晶粒，則形成多晶材料。多晶與單晶材料的差異主要表現在物理性質方面。例如在力學性質、電學性質等方面，多晶材料均不如單晶材料。於一較佳實施例中，該晶圓基底為單晶或多晶材料。
本文所述之「碳化矽材料之厚度」，於一較佳實施例中，該厚度可以係介於0.2μm~500μm，例如介於0.4μm~500μm、介於0.6μm~500μm、介於0.8μm~500μm、介於1.0μm~500μm、介於2.0μm~500μm、介於4.0μm~500μm、介於6.0μm~500μm、介於8.0μm~500μm、介於10μm~500μm、介於12μm~500μm、介於14μm~500μm、介於16μm~500μm、介於18μm~500μm、介於0.2μm~180μm、介於0.2μm~160μm、介於0.2μm~140μm、介於0.2μm~120μm、介於0.2μm~100μm、介於0.2μm~80μm、介於0.2μm~60μm、介於0.2μm~40μm、介於0.2μm~20μm、介於0.2μm~1μm、介於0.2μm~0.8μm、介於0.2μm~0.6μm、介於0.2μm~0.4μm。此碳化矽材料之厚度可視需求調整，例如，當該碳化矽材料11接合於晶圓基底12表面後，可以雷射切割或研磨方式使該碳化矽材料11薄型化。
本文所述之「結晶層」，係指單晶材料所構成之發光層主要基板材質。例如單晶砷化鎵(GaAs)基板、磷化鎵(GaP)基板、磷化銦(InP)基板、藍寶石(Al 2O 3)基板、碳化矽(SiC)基板、氮化鎵(GaN)基板等。
前述之結晶層以磊晶方式生長。所述之「磊晶」係指單晶基板上成長薄膜的延伸，經由在單晶基板上增添的原子而形成的一個單晶結構的連續體。例如液相磊晶(LPE)、氣相磊晶(VPE)及分子束磊晶(MBE)等，其中氣相磊晶包含物理氣相沉積(PVD)與化學氣相沉積(CVD)。
本文所述之「表面改質」係指該碳化矽材料與晶圓接合的表面，即碳化矽材料之下表面與該晶圓基底之上表面兩者或任一者的表面，經過化學或物理方式處理，使該表面能產生氫鍵或帶電荷離子或物理鍵結包含但不限於凡德瓦力、庫倫力或摩擦力等等。
產生氫鍵的方式例如但不限於經由浸泡含氫原子之液體，以改質該表面並且產生氫鍵結合力。該氫原子液體可為鉻酸、硫酸、鹽酸、硝酸、亞硫酸、氫氟酸、高氯酸、氫溴酸、高溴酸、氟矽酸、氯鉛酸偏磷酸、鋨酸、高錳酸、硒酸、高鐵酸、氟硼酸、氟磺酸、氰酸、硫氰酸、偏高碘酸、2,4,6-三硝基苯酚、2,4,6-三硝基苯甲酸、三氟乙酸、三氯乙酸、甲磺酸、苯磺酸、環己硫醇磺酸、2-氯乙硫醇等。
產生靜電的方式例如但不限於為，可藉由該接觸表面以電漿衝擊，產生正負電荷，利用電荷彼此吸附。
產生物理鍵結的型式如凡德瓦力、庫倫力、摩擦力等，其中凡德瓦力係因極平坦的表面，不同的材料或相同的材料都會有電位差，利用電位差產生的電荷相吸即為凡德瓦力；提供表面電荷(例如以電漿提供)形成的電位差即為庫倫力；固體表面之間的靜摩擦力則源於固體表面原子、分子之間相互的吸引力和它們之間的表面粗糙所造成的互相之間卡住的阻力。
前述之「電漿」係指在固態、液態和氣態以外的第四大物質狀態，又稱做等離子體。氣體在高溫或強電磁場下，會變為電漿，電漿為一種帶有等量的正電荷與負電荷的離子化氣體，由離子、電子與中性的原子或分子所組成。藉由外加的能量來促使氣體內的電子獲得能量並且加速撞擊不帶電的中性原子，由於不帶電中性原子受加速的電子撞擊後會產生離子與另一帶能量的加速電子，這些被釋出的電子，在經由電場加速與其他中性原子碰撞，如此反覆不斷，進而使氣體產生崩潰效應 (gas breakdown)，形成電漿狀態。本發明係利用產生的電漿與腔體內的製程氣體發生碰撞讓氣體離子化，而離子化的氣體會被吸引到晶片上進行表面改質，於表面上形成靜電電荷。
綜上所述，本發明之碳化矽複合晶圓具有以下優勢：
1. 高介電常數、絕緣性、高熱傳導率、耐熱性及散熱性佳，特別係在高濕度下具有穩定性能的特性。
2.本發明之碳化矽複合晶圓製造方法為碳化矽材料與晶圓基底直接接合，且兩者的表面或任一者的表面經過改質，接合能力較強，因此能降低製程複雜度。
3. 藉由本發明之碳化矽複合晶圓該材料彼此結合能力強的特性，進一步能依照需求對該晶圓進行研磨加工使之薄層化，後續產業利用性高。
以上已將本發明做一詳細說明，惟以上所述者，僅惟本發明之一較佳實施例而已，當不能以此限定本發明實施之範圍，即凡依本發明申請專利範圍所作之均等變化與修飾，皆應仍屬本發明之專利涵蓋範圍內。
1:碳化矽複合晶圓 11:碳化矽材料 12:晶圓基底 13:結晶層 111:接觸面
圖1為本發明之碳化矽複合晶圓結構示意圖。
無。
1:碳化矽複合晶圓
11:碳化矽材料
12:晶圓基底
13:結晶層
111:接觸面

Claims (1)

  1. 一種碳化矽複合晶圓之製造方法，包含下列步驟：(a)一碳化矽經長晶處理為一碳化矽材料；及(b)提供一晶圓基底，將該碳化矽材料之下表面及該晶圓基底之上表面兩者或任一者浸泡含有氫原子之液體以產生氫鍵後，直接接合形成一碳化矽複合晶圓。
TW110118804A 2021-05-25 2021-05-25 碳化矽複合晶圓及其製造方法 TWI783497B (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
TW110118804A TWI783497B (zh) 2021-05-25 2021-05-25 碳化矽複合晶圓及其製造方法
JP2021149274A JP7347845B2 (ja) 2021-05-25 2021-09-14 炭化ケイ素複合ウェハ及びその製造方法
US17/499,226 US20220384385A1 (en) 2021-05-25 2021-10-12 Silicon carbide composite wafer and manufacturing method thereof
EP21212892.0A EP4095291A1 (en) 2021-05-25 2021-12-07 Silicon carbide composite wafer and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW110118804A TWI783497B (zh) 2021-05-25 2021-05-25 碳化矽複合晶圓及其製造方法

Publications (2)

Publication Number Publication Date
TWI783497B true TWI783497B (zh) 2022-11-11
TW202246599A TW202246599A (zh) 2022-12-01

Family

ID=80035062

Family Applications (1)

Application Number Title Priority Date Filing Date
TW110118804A TWI783497B (zh) 2021-05-25 2021-05-25 碳化矽複合晶圓及其製造方法

Country Status (4)

Country Link
US (1) US20220384385A1 (zh)
EP (1) EP4095291A1 (zh)
JP (1) JP7347845B2 (zh)
TW (1) TWI783497B (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103021814A (zh) * 2012-12-25 2013-04-03 上海新储集成电路有限公司 一种氮化镓基半导体材料外延复合衬底的制备方法
TW201342494A (zh) * 2011-12-15 2013-10-16 Power Integrations Inc 用於半導體裝置的製造之合成晶圓
TW201627150A (zh) * 2014-12-22 2016-08-01 Shinetsu Chemical Co 複合基板、奈米碳膜之製作方法及奈米碳膜
US9741685B2 (en) * 2015-08-07 2017-08-22 Lam Research Corporation Methods for directly bonding silicon to silicon or silicon carbide to silicon carbide
CN111383915A (zh) * 2018-12-28 2020-07-07 中国科学院上海微系统与信息技术研究所 异质键合结构的制备方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3576432B2 (ja) * 1998-10-10 2004-10-13 Ｈｏｙａ株式会社 炭化珪素膜及びその製造方法
JP2013062339A (ja) * 2011-09-13 2013-04-04 Seiko Epson Corp 複合基板、電子デバイス及び電子機器
JP5896038B2 (ja) * 2012-10-15 2016-03-30 信越化学工業株式会社 ナノカーボン膜の作製方法
KR101580015B1 (ko) * 2013-08-30 2015-12-24 주식회사 엔씰텍 임시 점착/탈착층을 사용하는 플렉시블 정보 표시 소자 제조용 지지 기판, 이의 제조 방법, 그를 이용한 플렉시블 정보 표시 소자 및 그의 제조 방법
JP2017114694A (ja) * 2015-12-21 2017-06-29 信越化学工業株式会社 化合物半導体積層基板及びその製造方法、並びに半導体素子
JP2019193242A (ja) * 2018-04-23 2019-10-31 住友金属鉱山株式会社 表面弾性波素子用複合基板とその製造方法
JP7258494B2 (ja) * 2018-04-26 2023-04-17 株式会社Maruwa 複合基板、及び、複合基板の製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201342494A (zh) * 2011-12-15 2013-10-16 Power Integrations Inc 用於半導體裝置的製造之合成晶圓
CN103021814A (zh) * 2012-12-25 2013-04-03 上海新储集成电路有限公司 一种氮化镓基半导体材料外延复合衬底的制备方法
TW201627150A (zh) * 2014-12-22 2016-08-01 Shinetsu Chemical Co 複合基板、奈米碳膜之製作方法及奈米碳膜
US9741685B2 (en) * 2015-08-07 2017-08-22 Lam Research Corporation Methods for directly bonding silicon to silicon or silicon carbide to silicon carbide
CN111383915A (zh) * 2018-12-28 2020-07-07 中国科学院上海微系统与信息技术研究所 异质键合结构的制备方法

Also Published As

Publication number Publication date
JP7347845B2 (ja) 2023-09-20
US20220384385A1 (en) 2022-12-01
TW202246599A (zh) 2022-12-01
JP2022181154A (ja) 2022-12-07
EP4095291A1 (en) 2022-11-30

Similar Documents

Publication Publication Date Title
US7939428B2 (en) Methods for making substrates and substrates formed therefrom
US9196703B2 (en) Selective deposition of diamond in thermal vias
JP5051962B2 (ja) 基板、特に光学、電子工学または電子光学用基板の製造方法、およびこの製造方法により得られる基板
US20060008676A1 (en) Protective coating on a substrate and method of making thereof
US10612121B2 (en) Plasma resistant coating with tailorable coefficient of thermal expansion
CN111540684A (zh) 一种金刚石基异质集成氮化镓薄膜与晶体管的微电子器件及其制备方法
US7208392B1 (en) Creation of an electrically conducting bonding between two semi-conductor elements
EP1376660B1 (en) Wafer heating apparatus with electrostatic attraction function
US20230197435A1 (en) Method for manufacturing a composite structure comprising a thin layer made of monocrystalline sic on a carrier substrate made of sic
US7605055B2 (en) Wafer with diamond layer
US9224904B1 (en) Composite substrates of silicon and ceramic
TWI783497B (zh) 碳化矽複合晶圓及其製造方法
CN113903656A (zh) 一种碳化硅晶圆加工工艺
CN111540710B (zh) 一种高导热氮化镓高功率hemt器件的制备方法
US20220270875A1 (en) Method for manufacturing a composite structure comprising a thin layer of monocrystalline sic on a carrier substrate of polycrystalline sic
Blanton et al. Spalling‐Induced Liftoff and Transfer of Electronic Films Using a van der Waals Release Layer
CN115410899A (zh) 碳化硅复合晶圆及其制造方法
US9466758B2 (en) Composite substrates of silicon and ceramic
WO2020019312A1 (zh) 多层复合半导体基板结构及其制备方法
Takagi et al. Surface Activated Wafer Bonding; Principle and Current Status
US20240112908A1 (en) Method for manufacturing a composite structure comprising a thin single-crystal semiconductor layer on a carrier substrate
GB2560446A (en) Semiconductor device and method for manufacturing semiconductor device
WO2022259651A1 (ja) 窒化物半導体基板及びその製造方法
US20240030033A1 (en) Method for producing a semiconductor structure comprising an interface region including agglomerates
CN117568925A (zh) 一种金刚石-类金刚石结构晶圆的制备方法