TWI781344B - Display driving device for driving display panel and display device including the same - Google Patents

Abstract

A display driving device for driving a display panel and a display device including the same are disclosed. The display driving device includes a first driving circuit configured to output a first image signal, a second driving circuit configured to output a second image signal, a first switch circuit connected to the first driving circuit, and configured to transmit the first image signal to a part of a first set of sub-pixels arranged in the display panel based on a first switching signal during a first horizontal time interval, and a second switch circuit connected to the second driving circuit, and configured to transmit the second image signal to a part of a second set of sub-pixels arranged in the display panel adjacent to the first set of sub-pixels based on a second switching signal during the first horizontal time interval, wherein a width of the first switching signal and a width of the second switching signal differ from each other during the first horizontal time interval.

Description

Display driving device for driving display panel and display device including same

The following description relates to a display driving device. The following description is also related to a display device including such a display driving device. The following description also relates to a display driving device, and a display device including such a display driving device, which can adjust the timing of signals used in the display driving device. These adjustments reduce noise.

In recent years, as a display driver or a driver circuit processes more data, the amount of current used in the driver increases accordingly. In particular, the enlarged size and high resolution of a display screen, and the improved picture quality of a panel in a flat panel display device are used to increase the probability of occurrence of noise due to electromagnetic interference (EMI) in the panel.

Noise associated with EMI may appear in the panel due to the temporary output of various signals for the display driving device, thus causing failure of the display driving device.

This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

In a general aspect, a display driving device for driving a display panel includes: a first driving circuit configured to output a first image signal; a second driving circuit configured to output a second image signal; a first switch circuit, which is connected to the first driving circuit and configured to transmit the first image signal to the device configured on the basis of a first switching signal during a first horizontal time interval a portion of a first set of sub-pixels in the display panel; and a second switching circuit connected to the second driving circuit and configured to switch during the first horizontal time interval based on a second switching signal The second image signal is transmitted to a portion of a second sub-pixel set adjacent to the first sub-pixel set disposed in the display panel, wherein a width of the first switching signal and a width of the second switching signal are between The durations of the first horizontal time intervals are different from each other.

During the first horizontal time interval, a falling time point of the first switching signal may be earlier than a falling time point of the second switching signal.

During the first horizontal time interval, a rising time point of the first switching signal may be the same as a rising time point of the second switching signal.

The first switch circuit may be further configured to transmit the first image signal to another part of the first sub-pixel set based on a third switching signal during a second horizontal time interval after the first horizontal time interval, the second switch The circuit may be further configured to transmit the second image signal to another portion of the second set of sub-pixels based on a fourth switching signal during the second horizontal time interval, and a width of the third switching signal and the fourth switching signal One of the widths of the signals may be different from each other during the second horizontal time interval.

The first driving circuit may include a first multiplexer configured to output one pixel data of the first pixel data and the second pixel data in response to receiving a first selection signal during the first horizontal time interval, The two driving circuits may include a second multiplexer configured to output one of the third pixel data and the fourth pixel data in response to receiving a second selection signal during the first horizontal time interval, the first pixel data A phase of a selection signal and a phase of the second selection signal may be different from each other during the first horizontal time interval, and a width of the first selection signal and a width of the second selection signal may be the same.

During the first horizontal time interval, a falling time point of the first selection signal may be earlier than a falling time point of the second selection signal.

The first driving circuit may further include a first latch configured to output the first pixel data and the second pixel data to the first multiplexer, and configured to output A first voltage of one pixel data output by the device is output to a first source amplifier set as a first image signal in the first sub-pixel, and the second driving circuit may further include a configuration configured to convert the third pixel data and the first Four pixel data are output to a second latch in the second multiplexer, and configured to output a second voltage corresponding to one pixel data output from the second multiplexer to the second set of sub-pixels As a second source amplifier for the second image signal.

The display driving device may further include a logic circuit configured to adjust the width of the first switching signal and the width of the second switching signal.

The logic circuit may be further configured to sequentially set the width of the first switching signal during each horizontal period to a reference width, set to a value smaller than the reference width, set to the reference width, and set based on a four-cycle counter, is one of the values greater than the reference width.

In another general aspect, a display device includes a display panel and a display driving device for driving the display panel, wherein the display panel includes sub-pixels disposed in the display panel, wherein the display driving device includes: a a first drive circuit configured to output a first image signal; a second drive circuit configured to output a second image signal; a first switch circuit connected to the first drive circuit, and configured to transmit the first image signal to a portion of a first sub-pixel set disposed in the display panel based on a first switching signal during a first horizontal time interval; and a second switching circuit, It is connected to the second driving circuit and is configured to transmit the second image signal to adjacent first sub-pixel sets disposed in the display panel based on a second switching signal during the first horizontal time interval A portion of a second sub-pixel set, and wherein a width of the first switching signal and a width of the second switching signal are different from each other during the first horizontal time interval.

During the first horizontal time interval, a falling time point of the first switching signal may be earlier than a falling time point of the second switching signal.

The first driving circuit may include a first multiplexer configured to output one of the first pixel data and the second pixel data in response to receiving a first selection signal during the first horizontal time interval, and The second driving circuit may include a second multiplexer configured to output one of the third pixel data and the fourth pixel data in response to receiving a second selection signal during the first horizontal time interval, the A phase of the first selection signal and a phase of the second selection signal may be different from each other during the first horizontal time interval, and a width of the first selection signal and a width of the second selection signal may be the same.

The display driving device may further include a logic circuit configured to adjust the width of the first switching signal and the width of the second switching signal, and the logic circuit may be further configured to divide the period of each horizontal period based on a four-cycle counter. The width of the first switching signal is sequentially set to a reference width, set to a value smaller than the reference width, set to the reference width, and set to a value greater than the reference width.

In another general aspect, a display driving device for driving a display panel in which a plurality of pixels are arranged in parallel includes: a first driving circuit unit configured to output a first image signal to a plurality of In an odd-numbered pixel among the plurality of pixels; a second driving circuit unit configured to output a second image signal to an even-numbered pixel among the plurality of pixels; a first switch circuit unit inserted into between the odd-numbered pixels and the first driving circuit unit, and configured to perform a switching operation for connecting the odd-numbered pixels and the first driving circuit unit; and a second switching circuit unit interposed between Between the even pixel and the second driving circuit unit, configured to perform a switching operation for connecting the even pixel and the second driving circuit unit, wherein a switching timing of the first switching circuit unit and the One of the switching timings of the second switching circuit units may be different from each other.

The display driving device may further include a plurality of first switching circuit units, and the switching timing of each of the plurality of first switching circuit units may be the same, and the display driving device may further include a plurality of second switching circuit units, and the The switching timings of each of the plurality of second switch circuit units may be the same.

The first switching circuit unit may be further configured to perform a switching operation for connecting the odd-numbered pixels and the first driving circuit unit in response to a first switching signal, and the second switching circuit unit may be further configured to respond to a first switching signal. Two switching signals are used to perform a switching operation for connecting the even pixels and the second driving circuit unit, wherein the width of the first switching signal and the width of the second switching signal can be different from each other.

The first drive circuit unit may be further configured to perform a data selection operation for selecting a portion of input pixel data, and the second drive circuit unit may be further configured to perform a data selection operation for selecting a portion of input pixel data operation, and the data selection timing of the first driving circuit unit and the data selection timing of the second driving circuit unit may be different from each other.

In another general aspect, a display device includes a display panel and a display driving device for driving the display panel, wherein the display panel includes a plurality of pixels disposed in the display panel, wherein the display driving device includes : a first drive circuit unit configured to output a first image signal to an odd pixel in the plurality of pixels; a second drive circuit unit configured to output a second image signal output to one of the even pixels among the plurality of pixels; a first switch circuit unit, which is inserted between the odd pixel and the first driving circuit unit, and is configured to connect the odd pixel and the A switching operation of the first driving circuit unit; and a second switching circuit unit interposed between the even-numbered pixel and the second driving circuit unit and configured to perform an operation for connecting the even-numbered pixel and the second driving circuit unit A switching operation of the second driving circuit unit, wherein a switching timing of the first switching circuit unit and a switching timing of the second switching circuit unit are different from each other.

The display driving device may further include a plurality of first switch circuit units, the switching timing of each of the plurality of first switch circuit units may be the same, and the display drive device may further include a plurality of second switch circuit units, and the plurality of The switching timings of each of the second switch circuit units may be the same.

The first switching circuit unit may be further configured to perform a switching operation for connecting the odd-numbered pixels and the first driving circuit unit in response to a first switching signal, and the second switching circuit unit may be further configured to respond to a first switching signal. Two switching signals are used to perform a switching operation for connecting the even pixels and the second driving circuit unit, and the width of the first switching signal and the width of the second switching signal can be different from each other.

The first drive circuit unit may be further configured to perform a data selection operation for selecting a portion of input pixel data, and the second drive circuit unit may be further configured to perform a data selection operation for selecting a portion of input pixel data operation, and the data selection timing of the first driving circuit unit and the data selection timing of the second driving circuit unit may be different from each other.

Other features and aspects will be apparent from the following detailed description, drawings and claims.

Cross References to Related Applications This application claims the rights of Korean Patent Application No. 10-2018-0093726 filed with the Korean Intellectual Property Office on August 10, 2018, the entire disclosure of which is incorporated herein by reference for all purposes .

Hereinafter, examples will be described with reference to the accompanying drawings.

The following detailed description is provided to assist the reader in gaining a comprehensive understanding of the methods, devices and/or systems described herein. However, various changes, modifications, and equivalents of the methods, apparatus, and/or systems described herein will become apparent upon understanding the disclosure of the present application. For example, the sequences of operations described herein are examples only and are not limited to those sequences set forth herein, but may vary as will become apparent after understanding the disclosure of this application, but must occur in a particular order except for operations. Furthermore, descriptions of features known in the art may be omitted for increased clarity and conciseness.

The features described herein may be embodied in different forms and should not be construed as limited to the examples described herein. Rather, the examples described herein have been provided merely to illustrate some of the many possible ways of implementing the methods, apparatus and/or systems described herein, which will become apparent upon understanding the disclosure of this application.

Throughout the specification, when an element (such as a layer, region, or substrate) is described as being "on," "connected to," or "coupled to" another element, it may be directly "on" the other element. An element may be "on," "connected to," or "coupled to" another element, or there may be one or more other elements intervening therebetween. In contrast, when an element is described as being “directly on,” “directly connected to” or “directly coupled to” another element, there may be no intervening elements present therebetween.

As used herein, the term "and/or" includes any and any combination of any two or more of the associated listed items.

Although terms such as "first", "second" and "third" may be used herein to describe various elements, components, regions, layers or sections, such elements, components, regions, layers or sections do not shall be limited by these terms. In fact, these terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, a first component, component, region, layer or section involved in the examples described herein may also be referred to as a second component, component, region, layer or section without departing from the teachings of the examples.

Spatially relative terms such as "above," "on," "below," and "under" may be used herein for ease of description to describe the relationship of one element relative to another, as shown in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, an element described as "above" or "on" relative to another element would then be oriented "below" or "beneath" relative to the other element. Thus, the term "above" encompasses both an orientation above and below, depending on the spatial orientation of the device. A device may be otherwise oriented (eg, rotated 90 degrees or at other orientations), and the spatially relative terms used herein interpreted accordingly.

The terminology used herein is for describing various examples only and should not be used to limit the invention. The articles "a", "an" and "the" are intended to include the plural forms as well unless the context clearly dictates otherwise. The terms "comprising", "comprising" and "having" specify the presence of stated features, numbers, operations, components, elements and/or combinations thereof, but do not exclude the presence or addition of one or more other features, numbers, operations, Combinations of parts, elements and/or the like.

Variations from the shapes shown in the drawings may occur due to manufacturing techniques and/or tolerances. Thus, examples described herein are not limited to the particular shapes shown in the drawings, but include changes in shape that occur during manufacture.

The features of the examples described herein can be combined in various ways, as will become apparent after understanding the disclosure of this application. Furthermore, while the examples described herein have various configurations, other configurations are possible, as will become apparent after understanding the disclosure of this application.

Herein, it should be noted that use of the term "may" with respect to an instance or embodiment (eg, with reference to what an instance or embodiment may include or implement) means that there is at least one instance or embodiment that includes or implements such features, and all examples and embodiments are not limited thereto.

It is an object of the present invention to provide a display driving device and a display device including the same, which can adjust the timing of signals used in the display driving device, thus reducing noise due to EMI occurring in the display driving device.

The display driving device according to the example can differently set the timing of the switching signal to differently set the switching timing of a switch circuit unit, thus reducing noise caused by EMI.

The display driving device according to the example can differently set the timing of the selection signal to differently set the selection timing of the pixel data, thus reducing noise caused by EMI.

FIG. 1 conceptually illustrates a diagram of a display device according to an example. Referring to the example of FIG. 1 , a display device 1000 includes a display panel 100 , a display driving device 200 , a gate driver 300 , and a timing controller 400 .

According to an example, the display device 1000 may be a device capable of displaying an image or a video. For example, the display device 1000 may refer to a smart phone, a tablet personal computer, a mobile phone, a video phone, an e-book reader, a computer, a camera, or a wearable device, etc., but the display The device 1000 is not limited thereto.

The display panel 100 may include a plurality of sub-pixels PX arranged in columns and rows. For example, by selecting as a light emitting diode (LED) display, an organic LED (OLED) display, an active matrix OLED (AMOLED) display, an electrochromic display (ECD), a digital mirror device ( DMD), an actuated mirror device (AMD), a grating light valve (GLV), a plasma display panel (PDP), an electroluminescent display (ELD), and a vacuum fluorescent display (VFD) one of technology implements display panel 100, although the display technology is not limited to these examples and other display panel technologies may be used in other examples.

The display panel 100 includes a plurality of gate lines GL1 to GLn arranged in columns (where n is a natural number), a plurality of data lines DL1 to DLm arranged in rows (where m is a natural number), and formed on a plurality of The sub-pixels PX at intersections of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm. Accordingly, the display panel 100 includes a plurality of horizontal lines, and each of the horizontal lines is composed of sub-pixels PX connected to one gate line. During one horizontal time interval, sub-pixels arranged along one horizontal line can be driven, and during the next 1H horizontal time interval, sub-pixels arranged along another horizontal line can be driven.

The sub-pixel PX may include a light emitting diode (LED) and a diode driving circuit for independently driving the light emitting diode. The diode driver circuit can be connected to a gate line and a data line, and the LEDs can be connected between the diode driver circuit and a power supply voltage, for example, a ground voltage.

The diode driving circuit may include a switching element, for example, a thin film transistor (TFT) connected to the gate lines GL1 to GLn. When a gate-on signal is applied from the gate lines GL1 to GLn to turn on the switching elements, the diode driving circuit can transmit an image signal received from the data lines DL1 to DLm connected to the diode driving circuit (also called a pixel signal) is supplied to the light-emitting diode. The light emitting diode can output an optical signal corresponding to the image signal.

Each of the sub-pixels PX may be one of a red element R for outputting red light, a green element G for outputting green light, and a blue element B for outputting blue light. The pixels corresponding to red elements, green elements, and blue elements may be configured in the display panel 100 according to various methods. According to an example, the sub-pixels PX of the display panel 100 may be repeatedly arranged in the order of R, G, B, G, or B, G, R, G, and so on. However, these are only examples, and other ways of configuring the sub-pixels PX are also possible. For example, the sub-pixels PX of the display panel 100 may be configured according to an RGB stripe structure or an RGB pentile structure, but not limited thereto, and other RGB structures are also feasible.

The gate driver 300 can sequentially provide a gate turn-on signal to the plurality of gate lines GL1 to GLn in response to a gate control signal GCS. For example, the gate control signal GCS may include a gate start pulse for indicating the output start of the gate turn-on signal, a gate offset time for controlling the output time point of the gate turn-on signal Pulse and so on.

When the gate start pulse is applied, the gate driver 300 can sequentially generate a gate turn-on signal (eg, a gate voltage corresponding to a logic high) in response to the gate offset clock, and can The gate turn-on signal is sequentially supplied to the plurality of gate lines GL1 to GLn. At this time, a gate turn-off signal (for example, a gate voltage corresponding to a logic low) is supplied to the plurality of gate lines GL1 to GLn during a time period during which the gates are not supplied. Turn on signals to the plurality of gate lines GL1 to GLn.

In response to a data control signal DCS, the display driving device 200 can convert the digital image data DATA into an analog image signal, and can provide the converted image signal to a plurality of data lines DL1 to DLm. The display driving device 200 can provide an image signal corresponding to one horizontal line to a plurality of data lines DL1 to DLm during a 1H time interval.

The display driving device 200 can be implemented as a semiconductor chip including a switching circuit unit 210 , a driving circuit unit 230 , and a logic circuit 250 .

The switch circuit unit 210 can transmit the signal transmitted from the driving circuit unit 230 to the display panel 100 . According to an example, the switch circuit unit 210 may connect each of the plurality of channels CH1 to CHk to two data lines from among the plurality of data lines DL1 to DLm.

According to an example, the switch circuit unit 210 can adjust the switching timing between the data lines of the plurality of channels CH1 to CHk, thereby reducing noise caused by EMI.

The driving circuit unit 230 can convert the image data DATA into an image signal in response to receiving the data control signal DCS. Therefore, the driving circuit unit 230 can output image signals as a grayscale voltage corresponding to the image data DATA, and can output these image signals to a plurality of channels CH1 to CHk, where k has a value of m or less One of the natural numbers. For example, the data control signal DCS may include a source start signal, a source offset clock, a source output enable signal, and so on.

The logic circuit 250 can control the operation of one of the switch circuit unit 210 and the drive circuit unit 230 . According to an example, the logic circuit 250 can control the operation timing of the switching circuit unit 210 and the driving circuit unit 230 . For example, as will be further described later, the logic circuit 250 may control the generation of various signals (for example, the signals of FIG. 3 ) for operating the switch circuit unit 210 and the drive circuit unit 230 .

According to an example, the logic circuit 250 may receive the signal generated by the timing controller 400 and may correspondingly control the operation of one of the switching circuit unit 210 and the driving circuit unit 230 based on the received signal.

The timing controller 400 can receive video image data RGB from an external source, and can image process the video image data RGB or convert it into a structure suitable for the display panel 100 to generate image data DATA. The timing controller 400 can transmit the image data DATA to the display driving device 200 .

The timing controller 400 can receive a plurality of control signals from an external host device. For example, the control signal may include a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, and a clock signal DCLK.

The timing controller 400 can generate a gate control signal GCS and a data control signal DCS for controlling the gate driver 300 and the display driving device 200 based on the received control signal. The timing controller 400 can control respective operation timings of the gate driver 300 and the display driving device 200 based on the gate control signal GCS and the data control signal DCS.

According to an example, the timing controller 400 may control the gate driver 300 such that the gate driver 300 drives the plurality of gate lines GL1 to GLn based on the gate control signal GCS. The timing controller 400 can control the display driving device 200 so that the display driving device 200 provides image signals to the plurality of data lines DL1 to DLm based on the data control signal DCS.

Respective configurations of the display device 1000 may each consist of a circuit capable of performing a corresponding function.

FIG. 2 conceptually illustrates a diagram of a display panel and a display driving device according to an example. 1 and 2, the display panel 100 may include a plurality of sub-pixels P11 to P14 and P21 to P24 arranged in parallel and a plurality of data switches DSW11 to P24 connected to each of the plurality of sub-pixels P11 to P14 and P21 to P24. DSW14 and DSW21 to DSW24. Each pair of data switches DSW11 to DSW14 and DSW21 to DSW24 may be connected to respective channels CH1 to CH4.

A first sub-pixel set P11 to P14 and a second sub-pixel set P21 to P24 may be arranged in parallel, and may also be arranged adjacent to each other. For example, the first sub-pixel set P11 to P14 may be four consecutive sub-pixels, and the second sub-pixel set P21 to P24 may be the next four consecutive sub-pixels.

The first set of sub-pixels P11 to P14 can be defined to form a first pixel, and the second set of sub-pixels P21 to P24 can be defined to form a second pixel. For example, the first pixel can be an odd pixel and the second pixel can be an even pixel.

The data switches DSW11 to DSW14 and DSW21 to DSW24 can switch between corresponding sub-pixels and channels based on data switching signals DSSa and DSSb. For example, the data switch DSW11 can connect the first channel CH1 and the sub-pixel P11 based on the first data switching signal DSSa, and the data switch DSW12 can connect the first channel CH1 and the sub-pixel P12 based on the second data switching signal DSSb. For example, when the first data switching signal DSSa is at a first level (for example, a logic low level), each of the data switches DSW11, DSW13, DSW21 and DSW23 can enable the channels CH1, CH3, CH2 and Each of CH4 and each of pixels P11, P13, P21, and P23 are connected to each other. However, when the second data switching signal DSSb is at a logic low level, each of the data switches DSW12, DSW14, DSW22 and DSW24 can make each of the channels CH1, CH3, CH2 and CH4 and the pixels P12, P14, P22 and P24 Each is connected to each other.

According to an example, the states (eg, on or off) of adjacent data switches (eg, DSW11 and DSW12 ) can be different from each other. That is, when the data switch DSW11 is turned on, the data switch DSW12 can be turned off, and when the data switch DSW12 is turned on, the data switch DSW11 can be turned off. Therefore, the analog image signal transmitted through each of the channels CH1 to CH4 can be selectively supplied to two sub-pixels connected to each of the channels CH1 to CH4 (for example, Either of P11 and P12).

The switch circuit unit 210 may include a first switch SW1 , a second switch SW2 , a third switch SW3 , and a fourth switch SW4 . According to an example, the number of switches included in the switch circuit unit 210 may be the same as the number of channels.

A first switch circuit unit may include a first switch SW1 and a third switch SW3, and a second switch circuit unit may include a second switch SW2 and a fourth switch SW4. That is, the first switch circuit units SW1 and SW3 may be connected to the first sub-pixel sets P11 to P14, and the second switch circuit units SW2 and SW4 may be connected to the second sub-pixel sets P21 to P24.

In this example, each of the switches SW1 to SW4 may perform a switching operation to connect each of the source amplifiers 231-1 to 231-4 to the channels CH1 to CH4 in response to each of the switching signals SS1 to SS4 each of them. According to an example, the switches SW1 and SW3 may perform a switching based on the switching signals SS1 and SS3, and the switches SW2 and SW4 may perform a switching based on the switching signals SS2 and SS4.

According to an example, the first switch SW1 may connect the first source amplifier 231-1 to the first channel CH1 based on the first switching signal SS1, and may connect the first source amplifier 231-1 to the first channel CH1 based on the third switching signal SS3. Three-channel CH3. The third switch SW3 may connect the third source amplifier 231-3 to the third channel CH3 based on the first switching signal SS1, and may connect the third source amplifier 231-3 to the first channel CH1 based on the third switching signal SS3. . Similarly, the second switch SW2 can connect the second source amplifier 231-2 to the second channel CH2 based on the second switching signal SS2, and can connect the second source amplifier 231-2 to the second channel CH2 based on the fourth switching signal SS4. Four channel CH4. The fourth switch SW4 may connect the fourth source amplifier 231-4 to the fourth channel CH4 based on the second switching signal SS2, and may connect the fourth source amplifier 231-4 to the second channel CH2 based on the fourth switching signal SS4. .

For example, when the first switching signal SS1 is at a second level (for example, a logic high level), the first switch SW1 can connect the first source amplifier 231-1 and the first channel CH1, and the second The three switches SW3 can be connected to the third source amplifier 231-3 and the third channel CH3. When the third switching signal SS3 is at a logic high level, the first switch SW1 can be connected to the first source amplifier 231-1 and the third channel CH3, and the third switch SW3 can be connected to the third source amplifier 231-3 and the first Channel CH1. Similarly, when the second switching signal SS2 is at a logic high level, the second switch SW2 can be connected to the second source amplifier 231-2 and the second channel CH2, and the fourth switch SW4 can be connected to the fourth source amplifier 231-4. And the fourth channel CH4. When the fourth switching signal SS4 is at a logic high level, the second switch SW2 can be connected to the second source amplifier 231-2 and the fourth channel CH4, and the fourth switch SW4 can be connected to the fourth source amplifier 231-4 and the second Channel CH2. Therefore, based on the switching signal, the source amplifier and the channel are connected to each other in an appropriately changed one.

The first switching signal SS1 and the third switching signal SS3 may be activated alternatively, and the second switching signal SS2 and the fourth switching signal SS4 may be activated alternatively. For example, a period during which the first switching signal SS1 is at a logic high level and a period during which the third switching signal SS3 is at a logic high level may not overlap with each other.

As further described later, the display driving device 200 according to the example can set the timings of the first switching signal SS1 and the second switching signal SS2 differently from each other, and can set the timings of the third switching signal SS3 and the fourth switching signal SS4 differently from each other. timing. By setting the switching timing between switches SW1 and SW3 and switches SW2 and SW4 differently, in this way, noise based on EMI that would otherwise be generated by a switching process can be reduced.

The driving circuit unit 230 may include source amplifiers 231-1 to 231-4, multiplexers 235-1 to 235-4, and latches 237-1 to 237-4, as shown in the example of FIG. 2 . According to an example, the driving circuit unit 230 may further include decoders 233-1 to 233-4 disposed between the source amplifiers 231-1 to 231-4 and the multiplexers 235-1 to 235-4, as shown in FIG. shown in the example.

For convenience, the first source amplifier 231-1, the first decoder 233-1, the first multiplexer 235-1, and the first latch 237-1 are collectively referred to as a first driving circuit. A second driving circuit, a third driving circuit, and a fourth driving circuit are also defined in a similar manner with respect to their constituent parts. The first driving circuit unit may include a first driving circuit and a third driving circuit, and the second driving circuit unit may include a second driving circuit and a fourth driving circuit.

The first driving circuit unit may output image signals to the first pixels P11 to P14, and the second driving circuit unit may output image signals to the second pixels P21 to P24. In addition, the first switching circuit units SW1 and SW3 can perform a switching operation to connect the first pixels P11 to P14 and the first driving circuit unit, and the second switching circuit units SW2 and SW4 can perform a switching operation to connect the second pixel P21 To P24 and the second drive circuit unit.

In addition, the display driving device 200 according to the example may include an odd-numbered driving circuit unit for outputting image signals to odd-numbered pixels among pixels arranged in parallel in the display panel 100 and for performing an operation for connecting the odd-numbered pixels and the odd-numbered driving circuit unit. One of the odd switching circuit cells for switching operation. The display driving device 200 according to the example may also include an even driving circuit unit for outputting an image signal to an even pixel among pixels arranged in parallel and an even driving circuit unit for performing a switching operation for connecting the even pixel and the even driving circuit unit. switch circuit unit.

That is, as consistent with the above description, the display driving device 200 according to the example can set the switching timing of odd-numbered switching circuit units and the switching timing of even-numbered switching circuit units differently from each other, thereby reducing troubles due to EMI generated by a switching procedure. noise.

Each of the source amplifiers 231 - 1 to 231 - 4 can output each of the video signals VS1 to VS4 to the display panel 100 through the switch circuit unit 210 .

Each of the latches 237-1 to 237-4 can store pixel data internally. According to an example, each of the latches 237-1 to 237-4 may store at least one of red pixel data R, green pixel data G, and blue pixel data B inside. For example, the first latch 237-1 can store red pixel data R and green pixel data G inside.

The latches 237 - 1 to 237 - 4 may internally store pixel data corresponding to each of the sub-pixels PX connected to the gate lines GL1 to GLn of the display panel 100 . For example, when the sub-pixel PX connected to the first gate line GL1 is driven, the latches 237-1 to 237-4 may internally store light corresponding to the light output from the sub-pixel PX connected to the first gate line GL1. and when driving the sub-pixel PX connected to the second gate line GL2, the latches 237-1 to 237-4 can internally store the pixel data corresponding to the output from the sub-pixel PX connected to the second gate line GL2. The pixel data of the light.

The multiplexers 235-1 to 235-4 can select one pixel data of the pixel data stored in the corresponding latches 237-1 to 237-4 based on the selection signals SELa and SELb, and can transfer the selected one pixel data to Output to decoders 233-1 to 233-4 or source amplifiers 231-1 to 231-4. For example, the first multiplexer 235-1 can select one pixel data (for example, R) of the pixel data R and G stored in the first latch 237-1 based on the first selection signal SELa, And the selected pixel data (for example, R) can be output to the first decoder 233-1 or the first source amplifier 231-1.

As will be further described later, the display driving device 200 according to the example can set the timings of the first selection signal SELa and the second selection signal SELb differently from each other to set the timing of the pixel data at the multiplexers 235-1 to 235-4 differently. Timing is chosen, thus reducing noise otherwise caused by EMI.

That is, as consistent with the above description, the display driving device 200 according to the example can set the data selection timing of the odd-numbered driving circuit units and the data selection timing of the even-numbered driving circuit units differently from each other, thereby reducing The noise of EMI.

The decoders 233-1 to 233-4 can output a grayscale voltage corresponding to the selected pixel data and output the grayscale voltage from the multiplexers 235-1 to 235-4 to the source amplifiers 231-1 to 231 -4 in. According to an example, the decoders 233-1 to 233-4 may receive one grayscale voltage (eg, R gamma voltage, G gamma voltage, and B gamma voltage) corresponding to each of the pixel data, and may Output a grayscale voltage corresponding to the selected pixel data and output the grayscale voltage from the multiplexers 235-1 to 235-4 to the source amplifiers 231-1 to 231-4.

The source amplifiers 231-1 to 231-4 can convert the pixel data output from the multiplexers 235-1 to 235-4 into image signals VS1 to VS4 using, for example, a digital-to-analog (DA) conversion, and The converted image signals VS1 to VS4 may be output to the channels CH1 to CH4, or alternatively the grayscale voltages (ie, gamma voltages corresponding to pixel data) output from the decoders 233-1 to 233-4 may be used as image Signals VS1 to VS4 are output to channels CH1 to CH4.

According to an example, the source amplifiers 231-1 to 231-4 can output the image signals VS1 to VS4 to the corresponding channels CH1 to CH4 through the connected switches SW1 to SW4. For example, the first source amplifier 231-1 can output the first video signal VS1 to the first channel CH1 or the third channel CH3 through the first switch SW1, and the third source amplifier 231-3 can output the first image signal VS1 to the first channel CH1 or the third channel CH3 through the third switch SW1. SW3 outputs the third video signal VS3 to the third channel CH3 or the first channel CH1, and the second source amplifier 231-2 can output the second video signal VS2 to the second channel CH2 or the fourth channel through the second switch SW2 In CH4, and the fourth source amplifier 231-4 can output the fourth video signal VS4 to the fourth channel CH4 or the second channel CH2 through the fourth switch SW4.

3 is a diagram illustrating a switching signal and a selection signal used in a display driving device according to an example. Referring to the example of FIG. 3 , the logic circuit 250 can generate switching signals SS1 to SS4 collectively referred to as SS and selection signals SELa and SELb collectively referred to as SEL.

According to an example, in one horizontal time interval, the logic circuit 250 can adjust the width of the switching signal SS, and can adjust the phase of the selection signal SEL. For example, the logic circuit 250 can adjust the falling time point or rising time point of the switching signal SS, generate the switching signal SS with the adjusted falling time point or rising time point, and adjust the rising time point and falling time point of the selection signal SEL. Or, and generate a selection signal SEL with an adjusted rising time point and an adjusted falling time point.

For example, the logic circuit 250 may adjust the width of the switching signal SS to a reference width, for example in an instance of ORIGIN as shown in FIG. It is adjusted to be smaller than the reference width in an instance of a MINUS, or larger than the reference width in an instance of a PLUS as shown in FIG. 3, for example.

For example, the logic circuit 250 may adjust the phase of the select signal SEL to a reference phase, such as in an instance of ORIGIN, earlier than the reference phase, such as in an instance of MINUS, or earlier than the reference phase, such as in an instance of PLUS. Adjust it later than the reference phase in .

The logic circuit 250 can read the value stored in a register, and can generate the switching signal SS and the selection signal SEL based on the read value read from the register.

According to an example, the logic circuit 250 can read at least one value from the register, and can use the at least one value read from the register to adjust the falling time point or rising time point of the switching signal SS to adjust the width of the switching signal SS .

According to an example, the logic circuit 250 can read at least one value from the register, and can use the at least one value read from the register to adjust the falling time point and rising time point of the selection signal SEL to adjust the phase of the selection signal SEL .

According to an example, the logic circuit 250 can determine whether to adjust the width of the switching signals SS1 to SS4 based on at least one value read from the temporary register, can determine whether to adjust the phases of the selection signals SELa and SELb, can determine whether to adjust the phases of the switching signals SS1 to SS4 Width, and can determine the phase of the select signal SELa and SELb.

FIG. 4 is a timing chart for explaining an operation of a display driving device according to an example, and FIGS. 5 to 8 are diagrams illustrating states of the display driving device at various time points in an example.

Lines 1H, 2H, 3H and 4H can be synchronized by a horizontal synchronization signal Hsync. 2 to 4, in the first line 1H, the logic circuit 250 can generate switching signals SS1 and SS2, so that the width of the switching signals SS1 and SS2 is the reference width in an example of ORIGIN, and in an example of MINUS smaller than the reference width in PLUS, or larger than the reference width in one instance of PLUS. That is, the logic circuit 250 can adjust and/or set the width of the switching signals SS1 and SS2 based on a predetermined reference width.

In addition, similar to the first line 1H, in the second line 2H, the logic circuit 250 may generate switching signals SS3 and SS4 such that the width of the third switching signal SS3 and the width of the fourth switching signal SS4 become different from each other. According to an example, in the second line 2H, the logic circuit 250 may generate the switching signals SS3 and SS4 such that the widths of the switching signals SS3 and SS4 are the reference width in an instance of ORIGIN and smaller than the reference width in an instance of MINUS, or In one instance of PLUS it is larger than the reference width.

According to an example, the logic circuit 250 can adjust or set the width of the switching signals SS1 to SS4 so that there is or is not a floating period in each horizontal time interval, which is in which the switching signals SS1 and SS3 or both SS2 and SS4 are at a logic low level standard cycle. For example, as shown in the example of FIG. 4 , there may be floating periods of the switching signals SS1 and SS3 in a first horizontal time interval 1H. However, there may be no floating periods of the switching signals SS1 and SS3 in a third horizontal time interval 3H.

As described above, although the logic circuit 250 has been described by way of example to adjust the switching signals SS1 to SS4 in two lines 1H and 2H, the logic circuit 250 can perform the same adjustment in a series of lines, and thus can be used in three lines. This adjustment occurs in one of the similar instances of three or more lines.

According to an example, the adjustment operation for the switching signals SS1 and SS2 in the first line 1H can also be applied to the odd lines 3H, 5H, etc. in the same way, and the adjustment operation for the switching signals SS3 and SS4 in the second line 2H can also be The same applies to the even lines 2H, 4H, and so on.

In addition, in the first line 1H, the logic circuit 250 can generate the selection signals SELa and SELb, so that the phase of the first selection signal SELa and the phase of the second selection signal SELb become different. For example, in the first line 1H, the logic circuit 250 may generate the selection signals SELa and SELb so that each of the falling time point and the rising time point of the first selection signal SELa becomes different from the falling time point of the second selection signal SELb. Each of the time point and the rising time point. At this time, in addition, the widths of the selection signals SELa and SELb can be kept the same.

As described above, although only one wire 1H has been described by way of example, the techniques used in the example can be applied to a series of wires in the same manner. According to an example, the adjustment operation for the selection signals SELa and SELb in the first line 1H can also be applied in the same way to the next successive lines 2H, 3H and so on.

For convenience, an operation in which the logic circuit 250 according to the example adjusts the widths of the switching signals SS1 to SS4 or adjusts the phases of the selection signals SELa and SELb is called a timing adjustment operation.

The operation of the display driving device at a first time point t ₀ in the example of FIG. 4 is further described with reference to the example of FIG. 5 . Referring to the example in FIG. 4 and FIG. 5 , at the first time point t ₀ , the first multiplexer 235-1 outputs the output stored in the first latch 237-1 based on the first selection signal SELa of a logic low level. One pixel data (for example, G) of the pixel data, and the second multiplexer 235-2 outputs the data stored in the second latch 237-2 based on the second selection signal SELb of a logic low level Pixel data A pixel data (for example, G).

Similarly, the third multiplexer 235-3 outputs one pixel data (for example, G) of the pixel data stored in the third latch 237-3 based on the first selection signal SELa of a logic low level, And the fourth multiplexer 235-4 outputs one pixel data (for example, G) of the pixel data stored in the fourth latch 237-4 based on the second selection signal SELb of a logic low level.

At the first time point t ₀ , the first switch SW1 is connected to the first source amplifier 231-1 and the first channel CH1 based on the first switching signal SS1 of a logic high level. Also at the first time point t ₀ , the second switch SW2 is connected to the second source amplifier 231-2 and the second channel CH2 based on the second switching signal SS2 of a logic high level. Similarly, the third switch SW3 connects the third source amplifier 231-3 and the third channel CH3 based on the first switching signal SS1 of a logic high level, and the fourth switch SW4 is based on the second switching signal SS2 of a logic high level to connect the fourth source amplifier 231-4 and the fourth channel CH4.

In addition, at the first time point t ₀ , the switches DSW12, DSW14, DSW22 and DSW24 make each of the channels CH1, CH3, CH2 and CH4 and the pixels P11, P13, P21 and P23 based on a low-level second data selection signal DSSb Each of them is connected to each other.

The operation of the display driving device at a second time point t ₁ in the example of FIG. 4 is further described with reference to the example of FIG. 6 . Referring to the example in FIG. 4 and FIG. 6 , at the second time point t ₁ , the first multiplexer 235-1 outputs the data stored in the first latch 237-1 based on the first selection signal SELa of a logic high level. Another pixel data (for example, R). As at the first time point _t0 , the second multiplexer 235-2 outputs a pixel data stored in the second latch 237-2 based on the second selection signal SELb of a logic low level (for example , G). That is, only the level of the first selection signal SELa of the selection signals SELa and SELb of a logic low level is changed. Therefore, only the data selection of the first multiplexer 235-1 is changed from G to R, for example. Similarly, the third multiplexer 235-3 outputs another pixel data (for example, B) stored in the third latch 237-3 based on the first selection signal SELa of a logic high level, and communicates with As at the first time point _t0 , the fourth multiplexer 235-4 outputs a pixel data stored in the fourth latch 237-4 based on the second selection signal SELb of a logic low level (for example, G).

Since the phases of the first selection signal SELa and the second selection signal SELb in the first line 1H are different from each other, the data selection of the multiplexers 235-1 and 235-3 corresponding to the first sub-pixel sets P11 to P14 timing changes. That is, the timing of changing the level of the selection signal SELa is different from the timing of data selection changing of the other multiplexers 235 - 2 and 235 - 4 corresponding to the second adjacent sub-pixel sets P21 to P24 . Therefore, compared with the example of the same change timing of the data selection in the first multiplexer 235-1 and the third multiplexer 235-3 and the second multiplexer 235-2 and the fourth multiplexer 235-4 , less EMI occurs in the display driver. Therefore, this method can reduce the noise caused by EMI.

In addition, at the second time point t ₁ , the first switch SW1 releases the connection between the first source amplifier 231-1 and the first channel CH1 based on the first switching signal SS1 of a logic low level. Same as at the first time point _t0 , the second switch SW2 is connected to the second source amplifier 231-2 and the second channel CH2 based on the second switching signal SS2 of a logic high level. Similarly, the third switch SW3 connects the third source amplifier 231-3 and the third channel CH3 based on the first switching signal SS1 of a logic low level, and the fourth switch SW4 is based on the second switching signal SS2 of a logic high level to connect the fourth source amplifier 231-4 and the fourth channel CH4.

Since the width of the first switching signal SS1 and the width of the second switching signal SS2 are different from each other during the first line 1H, the time point when the first switching signal SS1 enters a logic low level and the second switching signal SS2 enters a logic low level The time points become different from each other. Therefore, the switching timing (ie, the state change timing from off to on or from on to off) of the switches SW1 and SW3 connected to the first sub-pixel set P11 to P14 becomes different from that connected to the second adjacent sub-pixel set P21 Switching timing of other switches SW2 and SW4 to P24. Therefore, less EMI occurs in the display driving device compared to an example in which the switching timing of the switches SW1 to SW4 is the same, which can reduce noise caused by EMI.

The operation of the display driving device at a third time point _t2 in the example of FIG. 4 is further described with reference to the example of FIG. 7 . Meanwhile, since the operation of the multiplexers 235-1 to 235-4 at the third time point _t2 is the same as the operation of the multiplexers 235-1 to 235-4 at the first time point _t0 , it is omitted for brevity. A description of this operation.

Referring to the examples in FIG. 4 and FIG. 7 , at the third time point t ₂ , the first switch SW1 connects the first source amplifier 231 - 1 and the third channel CH3 based on the third switching signal SS3 of a logic high level. In addition, the second switch SW2 is connected to the second source amplifier 231-2 and the fourth channel CH4 based on the fourth switching signal SS4 of a logic high level. Similarly, the third switch SW3 connects the third source amplifier 231-3 and the first channel CH1 based on the third switching signal SS3 of a logic high level, and the fourth switch SW4 is based on the fourth switching signal SS4 of a logic high level to connect the fourth source amplifier 231-4 and the second channel CH2.

The operation of the display driving device at a fourth time point _t3 in the example of FIG. 4 is further described with reference to the example of FIG. 8 . Meanwhile, since the operation of the multiplexers 235-1 to 235-4 at the fourth time point _t3 is the same as the operation of the multiplexers 235-1 to 235-4 at the second time point _t1 , it is omitted for brevity. A description of this operation.

That is, since the phases of the first selection signal SELa and the second selection signal SELb in the second line 2H are different from each other, the multiplexers 235-1 and 235-3 corresponding to the first sub-pixel sets P11 to P14 The timing of the data selection change (that is, the timing of the level change of the selection signal SELa) becomes different from that of the data selection changes of the other multiplexers 235-2 and 235-4 corresponding to the second adjacent sub-pixel sets P21 to P24. timing. Therefore, compared to the one with the same change timing of the data selection in the first multiplexer 235-1 and the third multiplexer 235-3 and the second multiplexer 235-2 and the fourth multiplexer 235-4 In one example, less EMI occurs in the display driver. Therefore, using this method can reduce the noise caused by EMI.

Referring to the example in FIG. 4 and FIG. 8 , at the fourth time point t ₃ , the first switch SW1 releases the connection between the first source amplifier 231-1 and the third channel CH3 based on the third switching signal SS3 of a logic low level. connect. Same as at the first time point _t0 , the second switch SW2 is connected to the second source amplifier 231-2 and the fourth channel CH4 based on the fourth switching signal SS4 of a logic high level. Similarly, the third switch SW3 releases the connection between the third source amplifier 231-3 and the first channel CH1 based on the third switching signal SS3 at a logic low level, and the fourth switch SW4 releases the connection between the third source amplifier 231-3 and the first channel CH1 based on a logic high level. The fourth switching signal SS4 is used to connect the fourth source amplifier 231-4 and the second channel CH2.

Since the width of the third switching signal SS3 and the width of the fourth switching signal SS4 are different from each other during the second line 2H, the time point when the third switching signal SS3 enters a logic low level and the fourth switching signal SS4 enters a logic low level The time points become different from each other. Therefore, the switching timing of the switches SW1 and SW3 connected to the first sub-pixel set P11 to P14 becomes different from the switching timing of the other switches SW2 and SW4 connected to the second adjacent sub-pixel set P21 to P24. Therefore, less EMI occurs in the display driving device than in the example in which the switching timing of the switches SW1 to SW4 is the same, thus reducing noise caused by EMI.

FIG. 9 is a timing diagram for explaining an operation of a display driving device according to an example. As described above, in a horizontal time interval, the logic circuit 250 can adjust the width of the switching signal SS, and can adjust the phase of the selection signal SEL.

Different from the example of FIG. 4 , the width of the first switching signal SS1 shown in the example of FIG. 9 is the same as the reference width, and the width of the second switching signal SS2 is larger than the reference width. That is, according to an example, the display driving device 200 or the logic circuit 250 can adjust the width of the switching signal SS, and can adjust the phase of the selection signal SEL according to various methods.

FIG. 10 is a timing diagram for explaining an operation of a display driving device according to an example. Referring to the example of FIG. 10 , the logic circuit 250 can adjust the width of each of the switching signals SS1 to SS4 in adjacent odd lines or adjacent even lines differently from each other. For example, as shown in the example of FIG. 3 and FIG. 5 , the logic circuit 250 can adjust the width of the first switching signal SS1 in adjacent odd lines differently from each other, and can adjust the width of the third switching signal in adjacent even lines differently from each other. Switches the width of the signal SS3.

Similarly, logic circuit 250 may adjust the phase of each of select signals SELa and SELb in adjacent lines differently from each other. For example, as shown in the examples of FIGS. 3 and 5 , the logic circuit 250 may adjust the phase of the first selection signal SELa in adjacent lines differently from each other.

Therefore, switching timings of switches SW1 to SW4 or data selection timings of multiplexers 235-1 to 235-4 in adjacent lines (for example, lines 1H and 2H or lines 2H and 3H, etc.) become different from each other. That is, the total cycle of switching or data selection becomes uneven. Therefore, less EMI occurs in the display driver than in an example with the same timing. Therefore, noise caused by EMI can be reduced.

11 and 12 are diagrams for explaining a timing adjustment operation of a logic circuit according to an example. FIG. 11 shows an Nth frame FR0 (wherein N is a natural number) and an N+1th frame FR1, and FIG. 12 shows an N+2th frame FR2 and an N+3th frame FR3 .

Each block of the respective frame FR0 to FR3 may correspond to a timing connected with one sub-pixel set in one horizontal time interval. For example, a block P1 may correspond to the data selection timing of the first multiplexer 235-1 and the third multiplexer 235-3 or correspond to the first horizontal time interval 1H in the respective frames FR0 to FR3 The switching timing of the first switch SW1 and the third switch SW3 of the first sub-pixel sets P11 to P14. Similarly, a block arranged on the right side of the block P1 may correspond to the data selection timing of the second multiplexer 235-2 and the fourth multiplexer 235-4 or correspond to the first The switching timing of the second switch SW2 and the fourth switch SW4 of the second sub-pixel set P21 to P24 in the horizontal time interval 1H.

Likewise, each row of a respective frame FR0 to FR3 may correspond to a timing connected to a set of sub-pixels in a plurality of horizontal time intervals.

In the examples of FIG. 11 and FIG. 12 , the sign "+" shown in each block of frames FR0 to FR3 indicates that the corresponding timing is slower than the reference timing. That is, the sign "+" indicates that the width or phase of the switching signal SS or the selection signal SEL respectively corresponding to the block is appropriately a larger width or a later phase than the reference width or reference phase.

In the example of FIG. 11 and FIG. 12 , the symbol "-" shown in each block of frames FR0 to FR3 indicates that the corresponding timing is faster than the reference timing. That is, the sign "-" indicates that the width or phase of the switching signal SS or the selection signal SEL respectively corresponding to the block is appropriately a smaller width or an earlier phase than the reference width or reference phase.

In the example of FIG. 11 and FIG. 12 , the symbol “0” shown in each block of frames FR0 to FR3 indicates that the corresponding timing is the same as the reference timing. That is, "0" indicates that the width or phase of the switching signal SS or the selection signal SEL respectively corresponding to the block is properly the same as the reference width or the reference phase.

According to an example, the logic circuit 250 may adjust the widths of the switching signals SS1 to SS4 or the phases of the selection signals SELa and SELb so that the difference in timing between blocks in a certain number of lines becomes the same. For example, the logic circuit 250 may perform an adjustment such that the sum of the width differences between the switching signals SS1 and SS2 or SS3 and SS4, or the selection signal SELa and The sum of the phase differences between SELb becomes 0. As shown in the example of FIG. 11 and FIG. 12 , the number of occurrences of the symbol "-" and the number of occurrences of the symbol "+" in a range from 1H to 4H may be the same.

Similarly, the logic circuit 250 can adjust the width of the switching signals SS1 to SS4 or the phases of the selection signals SELa and SELb, so that the timing difference between the blocks within a certain number of frames becomes the same. For example, the logic circuit 250 can perform the adjustment so that the sum of the width differences between the switching signals SS1 and SS2 or SS3 and SS4 within frames FR0 to FR3, or likewise the sum of the phase differences between the selection signals SELa and SELb The sum becomes 0. As shown in the examples of FIG. 11 and FIG. 12 , the number of occurrences of the symbol "-" and the number of occurrences of the symbol "+" in a range from FR0 to FR3 may be the same.

That is, when parts of the logic circuit 250 belong to different frames from each other even in the same line, the corresponding switching timing or data selection timing may become different, so the timing is adjusted so that the deviation of the entire frame becomes 0.

According to an example, the logic circuit 250 can be based on a first counter that operates based on the horizontal synchronization signal Hsync and is composed of a four-cycle counter or a two-bit counter, and operates based on the vertical synchronization signal Vsync and is also composed of a four-cycle counter or a two-bit counter. A second counter constituted by a bit counter adjusts the width of the switching signal SS and can adjust the phase of the selection signal SEL. The counter can be implemented by a hardware counter or a software counter.

In the present invention, a four-cycle counter refers to a counter that periodically generates four count values (for example, "00", "01", "10" and "11"). That is, when the first counter generates a first count value in a first line 1H, it can also generate the first count value in a fifth line again. Similarly, when the second counter generates the first count value during a first vertical time, it can generate the first count value again during a fifth vertical time.

According to an example, the logic circuit 250 can sequentially adjust the widths of the switching signals SS1 to SS4 according to the count value generated by the first counter and can also sequentially adjust the phases of the selection signals SELa and SELb to perform a timing adjustment operation for each line.

For example, the logic circuit 250 can set the width of the first switching signal SS1 to be smaller than the reference width when the first counter generates a first count value (for example, "00") in a first line 1H, When the first counter generates a second count value (for example, "01") in a second line 2H, the width of the first switching signal SS1 is set as the reference width, and the first counter generates in a third line 3H A third count value (for example, "10") sets the width of the first switching signal SS1 to be greater than the reference width, and generates a fourth count value (for example, in a fourth line 4H) in the first counter In other words, "11"), the width of the first switching signal SS1 is set as the reference width.

Meanwhile, when adjusting the widths of other switching signals SS2 to SS4 , the logic circuit 250 can use to shift the count value generated by the first counter. For example, when the first counter generates a first count value in the first line 1H, the logic circuit 250 may adjust based on a value obtained by offsetting the first count value (ie, the second count value) Width of the second switching signal SS2.

For example, the logic circuit 250 can set the phase of the first selection signal SELa to be earlier than the reference phase when the first counter generates the first count value (for example, "00"), and can set the phase of the first selection signal SELa earlier than the reference phase when the first counter generates the second count value. When the count value (for example, "01"), the phase of the first selection signal SELa is set as the reference phase, the first selection signal can be set when the first counter generates a third count value (for example, "10") The phase of SELa is set later than the reference phase, and the phase of the first selection signal SELa can be set as the reference phase when the first counter generates a fourth count value (for example, "11").

The logic circuit 250 can adjust the width of the switching signal SS according to the sum of the count value generated by the first counter and the value generated by the second counter and can adjust the phase of the selection signal SEL to perform a timing adjustment operation for each frame. When a frame is different even in the same line, the widths of the switching signals SS1 to SS4 or the phases of the selection signals SELa and SELb can be adjusted accordingly so that the timing difference between the blocks within the frame can be adjusted by making the corresponding The count value of the line is shifted and becomes the same.

For example, as shown in the example of FIG. 11 and FIG. 12 , the timing of the block P1 in the Nth frame FR0 and the timing of the block P1 in the N+1th frame FR1 may be different from each other.

While this disclosure includes specific examples, it will be apparent after reading the disclosure of this application that various changes in form and details may be made in these examples without departing from the spirit and scope of the claimed invention and its equivalents. The examples described herein are to be considered descriptive only and not for purposes of limitation. Descriptions of features or aspects in each example should be considered as applicable to similar features or aspects in other examples. If the described techniques are performed in a different order, and/or if components in a described system, architecture, device, or circuit are combined in a different manner, and/or are replaced or supplemented by other components or their equivalents, the achieve suitable results. Therefore, the scope of the present invention is defined not by the detailed description but by the scope of the patent claims and their equivalents, and all changes within the scope of the patent claims and their equivalents should be construed as being included in the present invention.

100: display panel 200: display drive device 210: switch circuit unit 230: drive circuit unit 231-1: first source amplifier 231-2: second source amplifier 231-3: third source amplifier 231-4: Fourth source amplifier 233-1: decoder 233-2: decoder 233-3: decoder 233-4: decoder 235-1: first multiplexer 235-2: second multiplexer 235-3 : the third multiplexer 235-4: the fourth multiplexer 237-1: the first latch 237-2: the second latch 237-3: the third latch 237-4: the fourth latch Device 250: logic circuit 300: gate driver 400: timing controller 1000: display device CH1 to CHk: channel DATA: image data DCLK: clock signal DCS: data control signal DL1 to DLm: data line DSSa: first data switching Signal DSSb: second data switching signal DSW11: data switch DSW12: data switch DSW13: data switch DSW14: data switch DSW21: data switch DSW22: data switch DSW23: data switch DSW24: data switch FR0: Nth frame FR1: Nth +1 frame FR2: N+2th frame FR3: N+3th frame GCS: gate control signals GL1 to GLn: first gate line Hsync: horizontal synchronization signal P1: block P11: first sub-pixel Set P12: first subpixel set P13: first subpixel set P14: first subpixel set P21: second subpixel set P22: second subpixel set P23: second subpixel set P24: second subpixel set PX: sub-pixel RGB: video image data SEL: selection signal SELa: first selection signal SELb: second selection signal SS: switching signal SS1: first switching signal SS2: second switching signal SS3: third switching signal SS4: second switching signal Four switching signals SW1: first switch SW2: second switch SW3: third switch SW4: fourth switch _t0 : first time point _t1 : second time point _t2 : third time point _t3 : fourth time point Point VS1: first video signal VS2: second video signal VS3: third video signal VS4: fourth video signal Vsync: vertical synchronization signal

FIG. 1 conceptually illustrates a diagram of a display device according to an example.

FIG. 2 conceptually illustrates a diagram of a display panel and a display driving device according to an example.

3 is a diagram illustrating a switching signal and a selection signal used in a display driving device according to an example.

FIG. 4 is a timing diagram for explaining an operation of a display driving device according to an example.

5 to 8 are diagrams showing states of the driving device at various time points.

FIG. 9 is a timing diagram for explaining an operation of a display driving device according to an example.

FIG. 10 is a timing diagram for explaining an operation of a display driving device according to an example.

11 is a diagram for illustrating a timing adjustment operation of a logic circuit according to an example.

FIG. 12 is a diagram for illustrating a timing adjustment operation of a logic circuit according to an example.

Throughout the drawings and the detailed description, like reference numerals refer to like elements. The drawings may not be drawn to scale, and the relative size, proportion and depiction of elements in the drawings may be exaggerated for clarity, illustration and convenience.

100: display panel

210: switch circuit unit

230: drive circuit unit

231-1: First source amplifier

231-2: Second source amplifier

231-3: Third source amplifier

231-4: Fourth source amplifier

233-1: first decoder

233-2: Decoder

233-3: Decoder

233-4: Decoder

235-1: The first multiplexer

235-2: Second multiplexer

235-3: The third multiplexer

235-4: Fourth multiplexer

237-1: The first latch

237-2: second latch

237-3: The third latch

237-4: The fourth latch

CH1: the first channel

CH2: second channel

CH3: the third channel

CH4: the fourth channel

DSSa: first data switching signal

DSSb: second data switching signal

DSW11: data switch

DSW12: data switch

DSW13: data switch

DSW14: data switch

DSW21: data switch

DSW22: data switch

DSW23: data switch

DSW24: data switch

P11: the first sub-pixel set

P12: the first sub-pixel set

P13: the first sub-pixel set

P14: the first sub-pixel set

P21: Second sub-pixel set

P22: Second sub-pixel set

P23: Second sub-pixel set

P24: Second sub-pixel set

SELa: first choice signal

SELb: Second selection signal

SS1: the first switching signal

SS2: Second switching signal

SS3: The third switching signal

SS4: The fourth switching signal

SW1: first switch

SW2: Second switch

SW3: Third switch

SW4: Fourth switch

VS1: the first video signal

VS2: Second video signal

VS3: The third video signal

VS4: Fourth video signal

Claims (21)

A display driving device for driving a display panel, the display driving device includes: a first driving circuit configured to output a first image signal; a second driving circuit configured to output a first Two image signals; a first switch circuit connected to the first drive circuit and configured to transmit the first image signal to the configured device based on a first switching signal during a first horizontal time interval a portion of a first set of sub-pixels in the display panel; and a second switch circuit connected to the second drive circuit and configured to, during the first horizontal time interval, based on a second The switching signal transmits the second image signal to a part of a second sub-pixel set adjacent to the first sub-pixel set configured in the display panel, wherein a width of the first switching signal and a width of the second switching signal One widths are different from each other during the first horizontal time interval. The display driving device according to claim 1, wherein during the first horizontal time interval, a falling time point of the first switching signal is earlier than a falling time point of the second switching signal. The display driving device according to claim 2, wherein during the first horizontal time interval, a rising time point of the first switching signal is the same as a rising time point of the second switching signal. Such as the display drive device of claim 1, Wherein the first switch circuit is further configured to transmit the first image signal to another of the first sub-pixel set based on a third switching signal during a second horizontal time interval after the first horizontal time interval A portion, wherein the second switch circuit is further configured to transmit the second image signal to another portion of the second sub-pixel set based on a fourth switching signal during the second horizontal time interval, and wherein the first A width of the three switching signals and a width of the fourth switching signal are different from each other during the second horizontal time interval. The display driving device according to claim 1, wherein the first driving circuit includes: a first multiplexer configured to output a first selection signal in response to receiving a first selection signal during the first horizontal time interval pixel data and a pixel data of second pixel data, wherein the second drive circuit includes: a second multiplexer configured to respond to a second selection signal received during the first horizontal time interval outputting one pixel data of third pixel data and fourth pixel data, wherein a phase of the first selection signal and a phase of the second selection signal are different from each other during the first horizontal time interval, and wherein the first selection A width of the signal is the same as a width of the second selection signal. The display driving device according to claim 5, wherein during the first horizontal time interval, a falling time point of the first selection signal is earlier than a falling time point of the second selection signal. The display driving device according to claim 5, wherein the first driving circuit further includes: a first latch configured to output the first pixel data and the second pixel data to the first multiplexer , and a first source amplifier configured to output a first voltage corresponding to the pixel data output from the first multiplexer as the first image signal to the first set of sub-pixels , and wherein the second driving circuit further comprises: a second latch configured to output the third pixel data and the fourth pixel data into the second multiplexer, and a second source A pole amplifier configured to output a second voltage corresponding to the pixel data output from the second multiplexer to the second set of sub-pixels as the second image signal. The display driving device according to claim 1, wherein the display driving device further comprises a logic circuit configured to adjust the width of the first switching signal and the width of the second switching signal. As the display driving device of claim 8, wherein the logic circuit is further configured to sequentially set the width of the first switching signal during each horizontal period to a reference width, set to be less than the width based on a four-cycle counter One of the reference widths, set to the reference width, and set to a value greater than one of the reference widths value. A display device comprising a display panel and a display driving device for driving the display panel, wherein the display panel comprises sub-pixels configured in the display panel; and wherein the display driving device comprises: a first driving circuit , which is configured to output a first image signal; a second drive circuit, which is configured to output a second image signal; a first switch circuit, which is connected to the first drive circuit, and is assembled state to transmit the first image signal to a portion of a first sub-pixel set configured in the display panel based on a first switching signal during a first horizontal time interval; and a second switching circuit, which connected to the second drive circuit, and configured to transmit the second image signal to adjacent first sub-displays disposed in the display panel during the first horizontal time interval based on a second switching signal A portion of a second sub-pixel set of the pixel set, and wherein a width of the first switching signal and a width of the second switching signal are different from each other during the first horizontal time interval. The display device according to claim 10, wherein during the first horizontal time interval, a falling time point of the first switching signal is earlier than a falling time point of the second switching signal. The display device according to claim 10, wherein the first driving circuit includes: a first multiplexer configured to output one pixel data of first pixel data and second pixel data in response to receiving a first selection signal during the first horizontal time interval, wherein the second drive The circuit includes: a second multiplexer configured to output a pixel data of third pixel data and fourth pixel data in response to receiving a second selection signal during the first horizontal time interval, wherein the A phase of the first selection signal and a phase of the second selection signal are different from each other during the first horizontal time interval, and a width of the first selection signal is the same as a width of the second selection signal. The display device according to claim 10, wherein the display driving device further comprises: a logic circuit configured to adjust the width of the first switching signal and the width of the second switching signal, wherein the logic circuit is further passed configured to sequentially set the width of the first switching signal during each horizontal period to a reference width, set to a value less than the reference width, set to the reference width, and set to the reference width based on a four-cycle counter One value greater than this reference width. A display driving device for driving a plurality of pixels arranged in parallel in one of the display panels, the display driving device includes: a first driving circuit unit configured to output a first image signal to the plurality of pixels In an odd pixel among the pixels; a second drive circuit unit configured to output a second image signal to the plurality of In an even pixel among the pixels; a first switch circuit unit, which is inserted between the odd pixel and the first driving circuit unit, and is configured to perform a connection between the odd pixel and the first a switching operation of a driving circuit unit; and a second switching circuit unit interposed between the even pixel and the second driving circuit unit and configured to perform a function for connecting the even pixel and the second A switching operation of the driving circuit unit, wherein a switching timing of the first switching circuit unit and a switching timing of the second switching circuit unit are different from each other. The display driving device according to claim 14, further comprising a plurality of first switch circuit units, wherein the switching timings of each of the plurality of first switch circuit units are the same, and further comprising a plurality of second switch circuit units, wherein the The switching timings of each of the plurality of second switch circuit units are the same. The display driving device according to claim 14, wherein the first switching circuit unit is further configured to respond to a first switching signal to perform the switching operation for connecting the odd-numbered pixels and the first driving circuit unit, wherein the The second switching circuit unit is further configured to perform the switching operation for connecting the even pixels and the second driving circuit unit in response to a second switching signal, and wherein a width of the first switching signal and the first switching signal The widths of one of the two switching signals are different from each other. The display driving device according to claim 14, wherein the first driving circuit unit is further configured to perform a data selection operation for selecting a portion of input pixel data, wherein the second driving circuit unit is further configured to perform In a data selection operation of selecting a part of input pixel data, the data selection timing of the first driving circuit unit and the data selection timing of the second driving circuit unit are different from each other. A display device comprising a display panel and a display driving device for driving the display panel, wherein the display panel comprises a plurality of pixels arranged in the display panel, wherein the display driving device comprises: a first driving circuit A unit configured to output a first image signal to an odd pixel of the plurality of pixels; a second drive circuit unit configured to output a second image signal to the plurality of pixels In one of the even-numbered pixels; a first switch circuit unit, which is inserted between the odd-numbered pixel and the first driving circuit unit, and is configured to perform connection between the odd-numbered pixel and the first driving circuit a switching operation of a unit; and a second switch circuit unit interposed between the even pixel and the second drive circuit unit and configured to perform an operation for connecting the even pixel and the second drive circuit A switching operation of a unit, wherein a switching sequence of a switching circuit unit of the first switching circuit unit and a switching sequence of a switching circuit unit of the second switching circuit unit The switching timings are different from each other. The display device according to claim 18, wherein the display driving device further includes a plurality of first switch circuit units, wherein the switching timings of each of the plurality of first switch circuit units are the same, and the display driving device further includes a plurality of The second switch circuit unit, wherein the switching timings of each of the plurality of second switch circuit units are the same. The display device of claim 18, wherein the first switching circuit unit is further configured to respond to a first switching signal to perform the switching operation for connecting the odd-numbered pixels and the first driving circuit unit, wherein the first switching circuit unit The two switching circuit units are further configured to perform the switching operation for connecting the even pixels and the second driving circuit unit in response to a second switching signal, and wherein a width of the first switching signal and the second switching signal The widths of one of the switching signals are different from each other. The display device of claim 18, wherein the first drive circuit unit is further configured to perform a data selection operation for selecting a portion of the input pixel data, wherein the second drive circuit unit is further configured to perform a data selection operation for A data selection operation for selecting a part of input pixel data, and wherein the data selection timing of the first driving circuit unit and the data selection timing of the second driving circuit unit are different from each other.

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