TWI779973B - Chip resistor and method of making the same - Google Patents

Abstract

A method for manufacturing chip resistors, comprising a providing step, a resistor forming step, a printing step, and a sintering step. In the providing step, a substrate is provided, and the substrate includes two process surfaces. The resistance forming step sputters an adhesion layer on at least one of the process surfaces, and sputters an alloy layer on the adhesion layer, and after printing a shielding layer on the alloy layer, removes the alloy layer and the adhesion layer, and then removes the shielding layer The alloy layer remains. In the printing step, two first copper paste layers are printed on one process surface, and two second copper paste layers are printed on the other process surface. In the sintering step, nitrogen sintering is performed on the adhesion layer, the alloy layer, the first copper paste layers, and the second copper paste layers to obtain a resistance layer, a first copper electrode, and a second copper electrode respectively. The present invention also provides the wafer resistor prepared by the above method.

Description

Chip resistor and manufacturing method thereof

The present invention relates to a passive element and its manufacturing method, in particular to a chip resistor and its manufacturing method.

Referring to FIGS. 1 and 2 , a conventional manufacturing method of chip resistors is illustrated. The manufacturing method of chip resistors firstly provides a substrate 91 having an upper surface 911 and a lower surface 912 . Next, a shielding layer 92 is printed on the upper surface 911 of the substrate 91, and the shielding layer 92 surrounds and defines a central region 920 that does not shield the upper surface 911, and an alloy material is sputtered on the central region 920 to form a Resistive layer 93 .

Next, the masking layer 92 is removed and the two front electrodes 94 and the two rear electrodes 95 are covered. First remove the shielding layer 92 by brushing and retain the resistance layer 93, and cover the front electrodes 94 on the surface of the resistance layer 93 by electroplating, and the back electrodes 95 are arranged on the lower surface. After the surface 912 and the positions correspond to the front electrodes 94 respectively, two side electrodes 96 are respectively covered on the left and right sides of the substrate 91 and electrically connected to the front electrodes 94 and the back electrodes 95 .

Finally, a protection layer 97 is coated on the resistance layer 93 to protect the resistance layer 93, and two electroplating layers 98 are coated on the front electrodes 94, the back electrodes 95 and the side electrodes 96 respectively. , a chip resistor 9 can be formed.

However, when the preparation method of the chip resistor forms the front electrodes 94 on the resistance layer 93 by electroplating, it is easy to cause the resistance layer 93 and the front surfaces to be separated due to the long processing time and the contamination of the electroplating solution. The electrodes 94 need to be individually heat-treated to be firmly attached to the substrate 91 , which seriously limits the production efficiency and further increases the production cost. this. Therefore, the existing method for preparing wafer resistors still needs to be improved.

Therefore, the object of the present invention is to provide a method for manufacturing chip resistors.

Therefore, the manufacturing method of the chip resistor of the present invention includes a providing step, a resistor forming step, a printing step, and a sintering step.

In the providing step, a substrate is provided, and the substrate includes two process surfaces respectively located on opposite sides.

In the resistance forming step, an adhesion layer is sputtered on at least one process surface of the substrate, and an alloy layer is sputtered on the adhesion layer.

In the printing step, two first copper paste layers spaced apart from each other and located at both ends of the alloy layer are printed on one of the process surfaces of the substrate, and two first copper paste layers spaced apart from each other and located on the other process surface of the substrate are printed. A second copper paste layer corresponding to the position of the first copper paste layer. The sintering step performs nitrogen sintering on the adhesion layer, the alloy layer, the first copper paste layers and the second copper paste layers to obtain a resistance layer, two first copper electrodes and two second copper paste layers respectively. Copper electrodes.

Furthermore, another object of the present invention is to provide a chip resistor.

Therefore, the chip resistor of the present invention includes a substrate, a resistor unit disposed on the substrate, and an electrode unit disposed on the substrate.

The substrate includes two process surfaces on opposite sides, and two side surfaces connected to the process surfaces respectively.

The resistance unit includes a first adhesion layer sputtered on one of the process surfaces of the substrate, and a first functional alloy layer sputtered on the first adhesion layer; and

The electrode unit includes two first copper electrodes spaced apart from each other on at least one process surface and partially covering both ends of the first adhesion layer, and two second copper electrodes spaced apart from each other on the other process surface. copper electrodes, and two third electrodes respectively formed on the side surfaces and electrically connected to the first copper electrodes and the second copper electrodes.

The effect of the present invention is that: the first copper paste layer and the second copper paste layer are processed by printing, which can shorten the working time and avoid the pollution of the electroplating solution, so only one sintering operation is required The resistance layer, the first copper electrodes and the second copper electrodes can be obtained, so that the process efficiency of the chip resistance can be effectively improved.

Before the present invention is described in detail, it should be noted that in the following description, similar elements are denoted by the same numerals.

Referring to Figures 3 and 4, it is an embodiment of the manufacturing method of the chip resistor of the present invention, the manufacturing method of the chip resistor includes a providing step 101, a resistance forming step 102, a printing step 103, a sintering step 104, a repairing resistance Step 105 , a coating step 106 , a slitting step 107 , a connecting step 108 , a particle folding step 109 , and an electroplating step 110 . In this embodiment, it is taken as an example to make a chip resistor with a single-sided resistive layer 81 (shown in FIG. 5 ), and it can also be used to make a chip resistor with a double-sided resistive layer 81 (shown in FIG. 5 ). , is not limited to this.

As shown in FIG. 4 , the providing step 101 is to provide a rectangular substrate 1 with insulating properties, and the substrate 1 includes two process surfaces 11 respectively located on opposite sides.

The resistor forming step 102 is sputtering an adhesion layer 71 on at least one of the process surfaces 11 of the substrate 1 by magnetron sputtering. In this embodiment, the adhesion layer 71 is selected from metal titanium or titanium alloy, and the adhesion layer 71 has better adhesion with the substrate 1 and an alloy layer 72 and can withstand high temperature sintering. The characteristic can be used as a buffer between the substrate 1 and the alloy layer 72, so that the substrate 1 and the alloy layer 72 can be stacked firmly with each other.

Next, in a vacuum magnetron sputtering machine, first fill argon gas and input voltage to form argon ions, then neutralize the argon ions with the target material to output vacuum plasma, and sputter on the adhesion layer 71 to form The alloy layer 72 . Wherein, when sputtering the alloy layer 72 , the operator needs to set the parameters of the vacuum magnetron sputtering machine to improve the uniformity of the alloy layer 72 adhering to the adhesion layer 71 . Preferably, the sputtering power of the vacuum magnetron sputtering machine is 0.15KW to 15KW, which can be adjusted according to different actual production requirements, and is not limited thereto.

In order to make the alloy layer 72 form a preset pattern, a shielding layer 73 presenting a predetermined pattern is printed on the alloy layer 72, so that the alloy layer 72 is divided into a shielded portion covered by the shielding layer 73 721, and an unshielded portion 722 other than the shielded portion, and after removing the unshielded portion 722 of the alloy layer 72 and the adhesion layer 71 in the corresponding range in sequence, the shielding layer 73 is removed to leave the The alloy layer 72 is patterned in a predetermined manner. In this embodiment, the shielding layer 73 is easy to print and easy to remove, and can protect the alloy layer 72 to be kept from being polluted by subsequent processes and the external environment.

Wherein, when removing the unmasked portion 722 of the alloy layer 72 and the adhesion layer 71 in the corresponding range, the unmasked portion 722 of the alloy layer 72 is etched with ferric chloride solution or copper chloride solution, corresponding The adhesion layer 71 in the range is treated with titanium etchant. When the masking layer 73 is removed, alkaline cleaning is performed with alkaline liquid, which is a sodium hydroxide solution with a concentration of 1% to 10%. It should be added that when removing the shielding layer 73, because the shielding layer 73 is formed above the alloy layer 72, there will be no change in the thickness of the alloy layer 72, resulting in failure to remove the masking layer 73 smoothly. The complete removal of the shielding layer 73.

Referring to FIG. 5 and in conjunction with FIG. 3, the printing step 103 is to print two first copper paste layers 31 spaced apart from each other and located at both ends of the alloy layer 72, and two layers spaced apart from each other and connected to the alloy layer 72 respectively. The second copper paste layer 33 corresponding to the position of the first copper paste layer 31 is printed on one process surface 11 and the other process surface 11 of the substrate 1 .

The sintering step 104 is to carry out nitrogen sintering to the alloy layer 72, the first copper paste layers 31 and the second copper paste layers 33 to obtain a resistance layer 81, two first copper electrodes 32 and two copper paste layers respectively. A second copper electrode 34. In this embodiment, the operating temperature of the nitrogen sintering is preferably 850° C. to 950° C., and the sintering time is preferably 5 to 15 minutes. Among them, compared with the existing vacuum annealing method, the nitrogen sintering method takes 50 to 70 minutes from heating treatment to cooling to 25°C room temperature, while the existing annealing operation takes 50 to 70 minutes from heating treatment to cooling to 25°C room temperature The required time is 4HR, so the efficiency of the process is greatly improved.

It is worth noting that, after the alloy layer 72 exhibiting the predetermined pattern is sintered in the sintering step 104, the alloy layer 72 exhibiting the predetermined pattern will spread the internal alloy components evenly through the mechanism of high temperature diffusion to form a resistor layer 81, so that the resistive layer 81 presenting the predetermined pattern can have improved power withstand capability, stable temperature coefficient of resistance and heat dissipation capability. And each first copper electrode 32 and each second copper electrode 34 will also be sintered and formed a copper alloy interface with the resistance layer 81 that presents the predetermined pattern through high temperature diffusion, and can obtain a good performance. heat resistance and stability.

The resistance repairing step 105 is to modify the shape and area of the resistive layer 81 presenting the predetermined pattern by means of laser burning or cutter wheel grinding based on the principle that the resistance value is related to the physical structure parameters, so that Each chip resistance can meet the required resistance value.

In the coating step 106, an inner protection layer 74 covering the resistance layer 81 and a part of the first copper electrodes 32 is formed first, and then an outer protection layer 75 is coated on the inner protection layer 74 . In this embodiment, the inner protective layer 74 and the outer protective layer 75 are sprayed, but they can also be made by printing or photosensitive process, but it is not limited thereto.

Referring to Figures 5 and 6 together with Figure 3, in the stripping step 107, the substrate 1 is transported to a rolling device, and the substrate 1 is divided into several long strips by rolling and dividing. Shaped plate body 51. Next, the connecting step 108 is to respectively arrange the two third electrodes 35 on both sides of each plate body 51 by sputtering, and respectively make the first copper electrodes 32 and the second copper electrodes 32 opposite to each other After the electrodes 34 are electrically connected to each other, the particle folding step 109 is performed.

And the granulation step 109 is to use the rolling device again to roll and divide each plate body 51 to obtain several semi-finished products 52 . Finally, the electroplating step 110 is performed to form two inner electroplating layers 76 covering the first copper electrodes 32, the second copper electrodes 34 and the third electrodes 35 by electroplating on each semi-finished product 52. Afterwards, two outer electroplating layers 77 covering the inner electroplating layers 76 are formed to obtain several chip resistors.

In this embodiment, the first copper paste layers 31 and the second copper paste layers 33 are processed by printing, so that the working time can be shortened and the problem of contamination of the electroplating solution can be avoided. Only one sintering operation is required, that is, The resistive layer 81 , the first copper electrodes 32 and the second copper electrodes 34 can be closely attached to the process surface 11 , thereby reducing process time and production cost. In addition, by sputtering the adhesion layer 71 and the alloy layer 72 first, and then printing the shielding layer 73, the risk of the alloy layer 72 being exposed to the outside and being contaminated can be avoided, so as to improve the yield rate of the overall process.

Referring to Figures 7 and 8, it is a first embodiment of the chip resistance of the present invention, comprising a substrate 1, a resistance unit 2 arranged on the substrate 1, an electrode unit 3 arranged on the substrate 1, and an electrode unit covering the substrate 1. The covering unit 4 of the resistance unit 2 . The substrate 1 includes two process surfaces 11 on opposite sides, and two side surfaces 12 connected to the process surfaces 11 respectively. Wherein, the two different states shown in Fig. 7 and Fig. 8 are all described by taking the resistance unit 2 covered on one of the process surfaces 11 as an example, but Fig. 7 and Fig. 8 respectively make the resistance unit 2 The resistor units 2 are formed on two opposite sides of the substrate 1 .

Specifically, the shape of the substrate 1 is a rectangular block, and is made of aluminum oxide, or aluminum nitride, which can be selected according to actual needs, and is not limited thereto.

The resistance unit 2 includes a first adhesion layer 21 sputtered on one of the process surfaces 11 of the substrate 1 , and a first functional alloy layer 23 sputtered on the first adhesion layer 21 . In the first embodiment, the first adhesion layer 21 is a metal film of titanium alloy, which may also be made of metal titanium or titanium-tungsten alloy, which is not limited thereto.

The first functional alloy layer 23 is made of copper-nickel-manganese alloy, nickel-chromium alloy and nickel-chromium-silicon alloy. In the first embodiment, the first functional alloy layer 23 is an example of copper-nickel-manganese alloy, and based on the total weight of the first functional alloy layer 23 as 100%, it has a weight percentage of 40-60wt% copper , nickel with a weight percentage of 30-39 wt%, and manganese with a weight percentage of 1-3 wt%. In other applications, the first functional alloy layer 23 can also be exemplified by nickel-chromium alloy or nickel-chromium-silicon alloy. It should be added that the first functional alloy layer 23 is selected from the above materials, mainly because it can produce good adhesion with the first adhesion layer 21, and after the subsequent sintering process, the first functional alloy layer 23 can be Uniform and dense adhesion to the first adhesion layer 21, so that the finished product has a better temperature coefficient of resistance and withstand power. Taking the chip resistor model 2512 as an example, the rated withstand power can be increased from the original 2 watts to 3 watts, which is 1.5 times that of the traditional process.

The electrode unit 3 includes two first copper electrodes 32 spaced apart from each other on at least one process surface 11 and partially covering both ends of the first adhesion layer 21, and two spaced apart from each other on the other process surface 11. The second copper electrodes 34 on the surface 11 , and two third electrodes 35 respectively formed on the side surfaces 12 and electrically connecting the first copper electrodes 32 and the second copper electrodes 34 . In the first embodiment, each first copper electrode 32, each second copper electrode 34, and third electrode 35 are preferably copper paste with good conductivity, and are based on a solid content of 70-90% and Composed of glass paste.

The covering unit 4 includes a first inner protective layer 41 covered on the first functional alloy layer 23 and a part of the first copper electrodes 32 and made of glass material, and a first inner protective layer 41 covered on the first inner protective layer. Layer 41 is a first outer protective layer 42 made of epoxy resin or acrylic resin, two first electroplating layers 45 formed on the surfaces of the third electrodes 35 respectively, and two first electroplating layers 45 formed on the surfaces of the third electrodes 35 respectively. The second electroplating layer 46 of the first electroplating layers 45 . The first functional alloy layer 23 can be insulated and protected by the first inner protective layer 41 and the first outer protective layer 42, so that the first functional alloy layer 23 will not be affected by changes in external environmental conditions and can retain Good electrical properties.

It should be added that, as shown in FIG. 8, a third protective layer 47 is covered on the process surface 11 where the resistance unit 2 is not provided. The third protective layer 47 is a colored solder resist ink, mainly It is beneficial for the follow-up workers to identify and distinguish the two different aspects shown in Fig. 7 and Fig. 8 .

Specifically, the first electroplating layer 45 is made of metal nickel, and the second electroplating layer 46 is made of metal tin, through the first electroplating layer 45 and the second electroplating layer 46 as Solder joints, so that the first embodiment can be firmly welded to the soldering pads of the circuit board during the subsequent SMT (Surface Mount Technology) stamping operation, and has good stability.

The first embodiment can provide good adhesion through the first adhesion layer 21, so that the substrate 1, the first functional alloy layer 23 and the first adhesion layer 21 can be closely stacked, thereby improving the overall The temperature coefficient of resistance and withstand power.

Referring to Fig. 9, it is a second embodiment of the chip resistance of the present invention, and the difference with the first embodiment shown in Fig. 7 is that the resistance unit 2 of the second embodiment also includes a sputtered plate on the substrate 1 The second adhesion layer 22 of the other process surface 11, and a second functional alloy layer 24 sputtered on the second adhesion layer 22. The covering unit 4 also includes a second inner protection layer 43 covering the second functional alloy layer 24 and a part of the second copper electrodes 34, and a second inner protection layer 43 covering the second inner protection layer 43. Outer protective layer 44 . It is worth noting that, compared with the first embodiment, the second embodiment uses the second functional alloy layer 24 to be disposed on the other process surface 11 and is connected in parallel with the first functional alloy layer 23 to reduce resistance The effect of the value can be divided when the working current flows through the first functional alloy layer 23 and the second functional alloy layer 24 to effectively disperse the generated heat energy, thereby improving the overall power tolerance.

To sum up, the chip resistor and its manufacturing method of the present invention can shorten the working time and avoid contamination of the electroplating solution by virtue of the first copper paste layers 31 and the second copper paste layers 33 being processed by printing. problem, only one sintering operation is required to make the resistance layer 81, the first copper electrodes 32 and the second copper electrodes 34 tightly attached to the process surface 11, thereby reducing the process time and production costs. In addition, in the resistance forming step, the operation method of sputtering the adhesion layer 71 and the resistance layer 81 before printing the masking layer 73 can prevent the resistance layer 81 from being polluted by chemical substances in the subsequent process, so as to improve the overall process. yield. Therefore, can really reach the purpose of the present invention.

But what is described above is only an embodiment of the present invention, and should not limit the scope of the present invention. All simple equivalent changes and modifications made according to the patent scope of the present invention and the content of the patent specification are still within the scope of the present invention. Within the scope covered by the patent of the present invention.

1: Substrate 11: Process surface 12: side 2: Resistance unit 21: The first adhesion layer 22: Second adhesion layer 23: The first functional alloy layer 24: The second functional alloy layer 3: Electrode unit 31: The first copper paste layer 32: The first copper electrode 33: Second copper paste layer 34: The second copper electrode 35: The third electrode 4: Overlay unit 41: The first inner protective layer 42: The first outer protective layer 43: Second inner protective layer 44: Second outer protective layer 45: The first electroplating layer 46: Second electroplating layer 47: The third protective layer 51: board body 52:Semi-finished products 71: Adhesion layer 72: alloy layer 721: The covered part 722: unmasked part 73: masking layer 74: Inner protective layer 75: Outer protective layer 76: Inner electroplating layer 77: Outer plating 81: Resistance layer 101: Provide steps 102: Resistor forming steps 103: Printing step 104: Sintering step 105: Repair steps 106: coating step 107: Striping step 108: Connection steps 109: Grain breaking step 110: Electroplating step

Before the present invention is described in detail, it should be noted that in the following description, similar elements are denoted by the same numerals.

Other features and effects of the present invention will be clearly presented in the implementation manner with reference to the drawings, wherein: Fig. 1 is a sectional view, illustrates the preparation method of existing a kind of wafer resistance; Fig. 2 is a cross-sectional view illustrating a chip resistor made by the manufacturing method of the chip resistor; Fig. 3 is a block diagram, illustrates an embodiment of the manufacturing method of chip resistance of the present invention; Fig. 4 is a flow chart illustrating the operation flow of one of the providing steps and a resistance forming step of this embodiment; Fig. 5 is a flow chart illustrating the operation process of a printing step, a sintering step, a repairing step and a coating step of this embodiment; Fig. 6 is a flow chart, illustrates the operation process of one of stripping step, one connection step, one folding grain step and one electroplating step of this embodiment; Fig. 7 is a sectional view illustrating a first embodiment of the chip resistor of the present invention; Fig. 8 is a cross-sectional view illustrating another aspect of the first embodiment; and Fig. 9 is a cross-sectional view illustrating a second embodiment of the chip resistor of the present invention.

1: Substrate

11: Process surface

12: side

2: Resistance unit

21: The first adhesion layer

23: The first functional alloy layer

3: Electrode unit

32: The first copper electrode

34: The second copper electrode

35: The third electrode

4: Overlay unit

41: The first inner protective layer

42: The first outer protective layer

45: The first electroplating layer

46: Second electroplating layer

Claims (10)

A method of manufacturing a chip resistor, comprising: A providing step, providing a substrate, the substrate includes two process surfaces respectively located on opposite sides; A resistance forming step, sputtering an adhesion layer on at least one of the process surfaces of the substrate, and sputtering an alloy layer on the adhesion layer; A printing step, printing two first copper paste layers spaced apart from each other and located at both ends of the alloy layer on one of the process surfaces of the substrate, and printing two spaced apart first copper paste layers on the other process surface of the substrate And the second copper paste layer corresponding to the position of the first copper paste layer; and A sintering step, performing nitrogen sintering on the adhesion layer, the alloy layer, the first copper paste layers and the second copper paste layers to obtain a resistance layer, two first copper electrodes and two second copper electrodes respectively Two copper electrodes. The method for manufacturing chip resistors as claimed in claim 1, wherein, in the resistor forming step, a masking layer exhibiting a predetermined pattern is further formed on the alloy layer, so that the alloy layer is divided into a layer defined by the masking layer. The shielded portion, and an unshielded portion other than the shielded portion, and after removing the unshielded portion of the alloy layer and the adhesion layer in the corresponding range in sequence, the shielding layer is removed to leave the The alloy layer in the predetermined pattern. The method for manufacturing chip resistors as described in Claim 1 further includes a connecting step implemented after the sintering step, the connecting step is to respectively arrange two third electrodes on two of the process surfaces by sputtering side, and electrically connect the first copper electrodes and the second copper electrodes opposite to each other respectively. The method for manufacturing chip resistors as described in claim 3, further comprising a coating step before the connecting step, the coating step is to first form a layer covering the resistance layer and a part of the first copper electrodes After the inner protective layer, an outer protective layer is covered on the inner protective layer. According to the manufacturing method of chip resistor as claimed in item 1, the adhesion layer is selected from metal titanium, titanium alloy or titanium-tungsten alloy. A chip resistor comprising: A substrate, including two process surfaces located on opposite sides, and two side surfaces connected to the process surfaces respectively; A resistance unit is arranged on the substrate, and includes a first adhesion layer sputtered on one of the process surfaces of the substrate, and a first functional alloy layer sputtered on the first adhesion layer; and An electrode unit is arranged on the substrate, and includes two first copper electrodes spaced apart from each other on at least one of the process surfaces and partially covering both ends of the first adhesion layer, and two spaced apart from each other on the A second copper electrode on the other process surface, and two third electrodes respectively disposed on the side surfaces and electrically connected to the first copper electrodes and the second copper electrodes. The chip resistor as claimed in item 6, wherein the resistance unit further comprises a second adhesion layer sputtered on another process surface of the substrate, and a second functional alloy sputtered on the second adhesion layer Floor. The chip resistor as claimed in claim 6, further comprising a covering unit covering the resistance unit, the covering unit comprising a first functional alloy layer covering a part of the first copper electrodes An inner protection layer, and a first outer protection layer covering the first inner protection layer. The chip resistor as claimed in claim 7, further comprising a covering unit covering the resistance unit, the covering unit comprising a first covering part of the second functional alloy layer and the second copper electrodes Two inner protection layers, and a second outer protection layer covering the second inner protection layer. According to the chip resistor as claimed in item 7, the materials of the first adhesion layer and the second adhesion layer are selected from one of metal titanium or titanium alloy.

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