CN202423255U - Wafer circuit element with heat conduction layer - Google Patents
Wafer circuit element with heat conduction layer Download PDFInfo
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- CN202423255U CN202423255U CN2011204185085U CN201120418508U CN202423255U CN 202423255 U CN202423255 U CN 202423255U CN 2011204185085 U CN2011204185085 U CN 2011204185085U CN 201120418508 U CN201120418508 U CN 201120418508U CN 202423255 U CN202423255 U CN 202423255U
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Abstract
According to the wafer circuit element with a heat conduction layer provided in the utility model, a heat radiation layer is sputtered and electroplated on a substrate body firstly, an intermediary layer is attached to the heat radiation layer, then the intermediary layer is provided with a layer of an element portion with two conductive connecting end portions, and termination electrodes are sputtered and electroplated on two side surfaces of the substrate body for conductively connecting to two conductive connecting end portions. During the manufacture of the heat radiation layer, a gap for separating two ends of the heat radiation layer is preformed, the gap position can be the center of the set range deviated from the circuit element, in the electrifying process of the circuit element, the highest amount heat concentrated at the center between the two conductive connecting end portions can be effectively radiated by the heat radiation layer, the whole work efficiency is lifted, and the usage life is prolonged.
Description
[technical field]
The utility model is about a kind of wafer circuit element, refers in particular to a kind of wafer circuit element with heat-conducting layer.
[background technology]
The chip type circuit element is used in the various electronic equipments at present widely; Not only shared volume is little on circuit board; The needs that can meet surface mounting technology when especially installing; Be convenient to the automation assembling and be provided with, therefore for example circuit elements such as Chip-R, wafer electric capacity, wafer inductance, wafer voltage device or wafer fuse have been arranged now.
This type of chip type circuit element normally forms different circuit on substrate; And the common mode of shaping circuit generally can be divided into traditional thin film electrical circuit element and thick film circuit element; Wherein thin film electrical circuit element is on substrate, to make the circuit rete with the mode of lithography process, and thick film circuit element then is on substrate, to make the circuit rete with the mode of printing and sintering setting.The produced chip type circuit element of these two kinds of different process compares each other; Though can find that the cost of manufacture of thin film electrical circuit element is high; But precision and temperature variant stability at circuit layout all are superior to thick film circuit element; And constantly complicated in the function of electronic equipment, but under the more and more little situation in the space that can use, the thin film electrical circuit element that uses lithography process is a preferable solution at present.
Yet,, can't can portion of energy be converted into heat energy and cause temperature to rise with avoiding when elements such as Chip-R receive in electronic equipment in the electric operation; For the wafer circuit element, too high temperature will produce harmful effect, not only poor operation efficiency; Various different grading materials in the element also can be because of expansion coefficient difference each other, the expansion of rising and producing different size with temperature; Combination between each level is impaired thereupon, thereby obviously shortens useful life, further; If the wafer circuit element is a fuse, just the fuse that ambient temperature rises can be influenced as the usefulness of protection burns for no reason, opens circuit ahead of time.Unfortunately, in the time of within actual power still is in acceptable safe range, formerly should but, let this wafer fuse fuse in advance, add operation variable and increase puzzlement as the electrical fuse element of protection electronic equipment on the contrary because the heat of operating environment is accumulated.
Desire promotes heat-conducting effect, must consider the capacity of heat transmission of various materials again, and wherein, in the ceramic material of general Chang Zuowei substrate, aluminium oxide (alundum (Al) is though substrate is cheap, the conductive coefficient 20W/mK that only has an appointment, and heat-conducting effect is not good; The about 170W/mK of aluminium nitride substrate conductive coefficient; But price also exceeds nearly ten times than aluminum oxide substrate; Even have the part producer attempt with highly heat-conductive material for example copper metals such as (the about 380W/mK of conductive coefficient) be arranged at the opposite side of substrate, solving the element heating problem, but because the thickness of substrate itself has hundreds of microns (μ m); Element heating receives substrate obstruction and accumulation; Even the part heating is conducted to the element opposite sides and is derived, but the significantly lifting of the operating environment temperature of substrate, above-mentioned high heating problem still can not thoroughly solve.
Therefore, how to produce the heat that effective diversion chip element is produced by activation, reach and promote operating efficiency, make that to increase, reduce temperature useful life too high and the probability of forfeiture original function will become the solution with excellent product competitiveness undoubtedly.
[utility model content]
A purpose of the utility model is to provide a kind of and has one deck heat dissipating layer, order receives electricity to produce heat energy can be by the wafer circuit element with heat-conducting layer of effective diversion, to promote product operation stability.
Another purpose of the utility model is to provide a kind of wafer circuit element with heat-conducting layer that one deck forms gapped heat dissipating layer that has, and guarantees the unlikely initiation short circuit of heat dissipating layer, with holding circuit element electrical characteristic.
Another purpose of the utility model is to provide a kind of and has high cooling efficiency, increases the element wafer circuit element with heat-conducting layer in useful life.
A kind of wafer circuit element with heat-conducting layer according to the utility model discloses comprises: a slice substrate body, have two ora terminalis, and two connect aforementioned ora terminalis and side respect to one another respectively; One deck is formed at the heat-conducting layer of last, corresponding above-mentioned two ora terminalis in one of above-mentioned side; One deck is bonded to the intermediary layer on this heat-conducting layer; One deck is bonded to the impedance layer on this intermediary layer, comprises connecting the end, and connecting the aforementioned element portion that connects the end of two corresponding respectively above-mentioned two ora terminalis; And it is a pair of respectively to aforementioned two ora terminalis that should substrate body and connect aforementioned two termination electrodes that connect the end of this impedance layer respectively.
Because the wafer circuit element that the utility model disclosed with heat-conducting layer; Be the heat dissipating layer of elder generation in substrate body sputter and plating layer of metal material; And on heat dissipating layer, adhere to one deck intermediary layer; Then one deck is set on intermediary layer and has two element portion that connect the end, and be attached to heat dissipating layer, supply to connect two termination electrodes that connect the end in substrate body two sides sputter and plating again to element portion through intermediary layer; When making electric energy connect to termination electrode, the heat that element portion produced can be by heat dissipating layer diversion efficiently.
And this case heat dissipating layer more can form a gap between two ends, and lets gap digit in the center of departing from circuit element, that is; Even if in manufacturing process; Intermediary layer distributes and is formed with flaw and not evenly coating, or because of making insulation effect impaired for a long time, causes the insulation effect impairment between impedance layer and heat dissipating layer; Still can be by the gap that forms, the two ends of blocking impedance layer are short risk by heat dissipating layer.Especially the heat that when element portion receives activation, produces mainly concentrate on approximately slightly two connect between the end centre; In the heat dissipating layer of decentered distribution; Contain one of middle body and can bear main heat radiation responsibility, reach the lifting of radiating efficiency, and make element effectively prolong useful life; Especially to the for example product of wafer fuse class, the situation that more can avoid causing element to produce misoperation because temperature is too high takes place, and reaches above-mentioned all purposes.
[description of drawings]
Fig. 1 is the manufacturing flow chart of first preferred embodiment of the wafer circuit element with heat-conducting layer of the utility model;
Fig. 2 is the vertical view of substrate body of first preferred embodiment of the wafer circuit element with heat-conducting layer of the utility model;
Fig. 3 is the end view of the substrate body of Fig. 2;
Fig. 4 is the end view of side sputter layer of metal Seed Layer of the substrate body of Fig. 3;
Fig. 5 is the end view of impression one deck photoresistance film on the metal seed layer of Fig. 4;
Fig. 6 be the metal seed layer of Fig. 5 via electroplating and the etching operation, and after removing residue photoresistance film, form the end view of one deck heat-conducting layer;
Fig. 7 impresses one deck photoresistance film as intermediary layer on heat-conducting layer and the substrate body of Fig. 6 in addition, and on intermediary layer the end view of impression one deck impedance layer;
Fig. 8 is that the impedance layer of Fig. 7 makes public and develops and forms the vertical view of a predetermined pattern;
Fig. 9 is the end view that the substrate body of Fig. 7 is provided with impedance layer and packaging protection layer;
Figure 10 is that the substrate body slivering of Fig. 9 is piled up and exposed two ora terminalis, and sputter and plating synchronously thicken, and forms the end view of the termination electrode at two ends;
Figure 11 is that the substrate body of Figure 10 separates into particle one by one, accomplishes the end view of the wafer circuit element with heat-conducting layer of this example;
Figure 12 is the manufacturing flow chart of second preferred embodiment of the wafer circuit element with heat-conducting layer of the utility model;
Figure 13 is the end view of impression one deck intermediary layer on the heat-conducting layer of high heat-conducting chip circuit element of the utility model;
Figure 14 is a sputter layer of metal Seed Layer on the intermediary layer of Figure 13, and the end view of one deck photoresistance film is set on metal seed layer;
Figure 15 be the metal seed layer of Figure 14 via electroplating and the etching operation, and after removing residue photoresistance film, form the vertical view of a plurality of blown fuse portion;
Figure 16 is the end view of impression one deck packaging protection layer in the blown fuse portion of Figure 15;
Figure 17 is that the substrate body slivering of Figure 16 is piled up and exposed two ora terminalis, and sputter and plating synchronously thicken, and forms the end view of the termination electrode at two ends;
Figure 18 is that the substrate body of Figure 17 separates into particle one by one, accomplishes the end view of the wafer circuit element with heat-conducting layer of this example;
Figure 19 is the manufacturing flow chart of another execution mode of this routine heat-conducting layer;
Figure 20 is this another execution mode of routine heat-conducting layer, the end view of sputter layer of metal Seed Layer on one of them side of substrate body;
Figure 21 is the end view of impression one deck photoresistance film on the metal seed layer of Figure 20;
Figure 22 be the metal seed layer of Figure 20 via electroplating and the etching operation, and after removing residue photoresistance film, form the end view that one deck has the heat-conducting layer in gap;
Figure 23 forms the vertical view that one deck has the heat-conducting layer in gap on the substrate body of Figure 22;
Figure 24 is the manufacturing flow chart of the 3rd preferred embodiment of the wafer circuit element with heat-conducting layer of the utility model;
Figure 25 is the end view of impression one deck intermediary layer on the heat-conducting layer of the wafer circuit element with heat-conducting layer of the utility model;
Figure 26 is a sputter layer of metal Seed Layer on the intermediary layer of Figure 25, and is coated with one deck photoresistance film again in the end view of metal seed layer;
Figure 27 is that the metal seed layer of Figure 26 is electroplated and etching, removes remaining photoresistance film again, and forms the vertical view that presents spiral helicine inductance body;
Figure 28 be Figure 27 the inductance body two ends respectively routing connect to connecting the end and the end view of impression one deck packaging protection layer on the inductance body again;
Figure 29 is that the substrate body slivering of Figure 28 is piled up and exposed two ora terminalis, and sputter and plating synchronously thicken, and forms the end view of the termination electrode at two ends; And
Figure 30 is that the substrate body of Figure 29 separates into particle one by one, accomplishes the end view of the wafer circuit element with heat-conducting layer of this example.
[main element symbol description]
21,31,41 substrate body
211,311,411 ora terminalis
213,313 sides
210 frangible portion
231 metal seed layers
251,452,351,352 photoresistance films
23,33,43 heat-conducting layers
25,35 intermediary layers
26,37,47 termination electrodes
27 impedance layers
28 resistance bodies
29,39,49 packaging protection layers
331,432 metal seed layers
38 blown fuse portions
335 gaps
337,338 heat-conducting parts
45 inductance bodies
46 connect the end
[embodiment]
About the aforementioned of the utility model and other technology contents, characteristics and effect, in the detailed description of the preferred embodiment of following cooperation Figure of description, can clearly appear.
The utlity model has first preferred embodiment of the wafer circuit element of heat-conducting layer; Wherein the wafer circuit element is to be illustrated as a Chip-R in this example; The flow process of its making is as shown in Figure 1, at the beginning shown in step 101, with a slice such as Fig. 2 and shown in Figure 3 with the aluminium oxide of metal material or the substrate of aluminium nitride material; The precut substrate body 21 that pluralizes and link each other; And substrate body 21 has 213, two sides 213 of two ora terminalis 211 and two sides and is against each other and is connected to two ora terminalis 211 respectively and is formed with the frangible portion 210 of a V-type chase respectively 21 of each substrate body, supplies following usefulness of separating each substrate body 21.Certainly, can understand easily in this art as ripe, all elements on the substrate are separated, may not be confined in this step, form frangible portion, also can after roughly making completion, separate with modes such as for example laser cutting merely, not having can not.
Step 102 for another example, please in the lump with reference to as shown in Figure 4, sputter layer of metal Seed Layer 231 on each substrate body 21 one of them side 213; Next like step 103, and as shown in Figure 5, in metal seed layer 231 impression one deck photoresistance films 251; The light shield that photoresistance film 251 is covered and exposed to the open air to a part is set on photoresistance film 251 again; Photoresistance film 251 is made public and the development operation, the part that makes photoresistance film 251 do not covered by light shield changes phase structure and is retained on the metal seed layer 231, then like step 104 again; Metal seed layer 231 is electroplated and the etching operation; Just remaining photoresistance film 251 is removed subsequently, promptly form one deck heat-conducting layer as shown in Figure 6 23, and this routine heat-conducting layer 23 is two ora terminalis 211 directions of counterpart substrate body 21; But keep a segment distance setting with end, and the matter material that this routine heat-conducting layer 23 is selected to process can be selected from the set that copper, silver, gold, titanium, titanium alloy, nickel, nickel alloy, nichrome constitute.
Next like step 108,, on resistance body 28, impress one deck packaging protection layer 29 in the lump with reference to shown in Figure 9; Then like step 109,, along frangible portion 210 the full wafer substrate is separated into number along the vertical direction and arrange for example to knock or the mode of machine cuts; And be stacked into shown in figure 10; Make two ora terminalis 211 of each substrate body 21 be exposed to graphic about the outside, and slivering substrate body 21 two sides of sputter multiple-level stack synchronously, and electroplate and thicken; Formation exposes packaging protection layer 29 both sides and connects to the termination electrode 26 at the two ends of resistance body 28; Like step 110, each substrate body 21 is separated into particle one by one at last, just form Chip-R shown in figure 11.
The utlity model has second preferred embodiment of the wafer circuit element of heat-conducting layer, wherein the wafer circuit element is to be illustrated as a wafer fuse in this example, and different these the routine element portion that are with last embodiment of element portion are with sputter and electroplate metal materials such as one deck nickel or tin and process; The flow process of its making such as Figure 12 shown in step 201, please refer to Figure 13 at the beginning; Same impression one deck intermediary layer 35 next like step 202, carries out exposure operation and changes its phase structure intermediary layer 35 on the identical heat-conducting layer of processing 33 with last embodiment; Step 203 for another example, and shown in figure 14, sputter layer of metal Seed Layer 331 on intermediary layer 35; And one deck photoresistance film 352 is set on metal seed layer 331, the light shield that photoresistance film 352 is covered and exposed to the open air to a part is set on photoresistance film 352 again, again photoresistance film 352 is made public and the development operation; The part that makes photoresistance film 352 do not covered by light shield changes phase structure and is retained on the metal seed layer 331, then like step 204, metal seed layer 331 is electroplated and the etching operation; Just remaining photoresistance film 352 is removed subsequently, promptly form one deck element portion that is illustrated as blown fuse portion 38 shown in figure 15, for another example step 205; Shown in figure 16; Likewise in blown fuse portion 38, impress one deck packaging protection layer 39 with last embodiment, step 206 separates into number row along the vertical direction with the full wafer substrate for another example; And be stacked into shown in figure 17; Make two ora terminalis 311 of each substrate body 31 be exposed to graphic about the outside, again with sputter and electroplate and form a pair of connecting to the termination electrode 37 at the two ends of blown fuse portion 38, step 207 for another example at last; Each substrate body 31 is separated into particle one by one, just form wafer fuse shown in figure 18.
Because it is to select nickel or tin that this routine metal seed layer and plating thicken material; When the overcurrent situations that is higher than rated current takes place; Because predetermined reserved line zone has certain internal resistance, bear the circulation of this overcurrent and generate heat, yet receive the heat radiation influence of heat-conducting layer; But can make fuse can still not receive thermal cut too early, can increase the useful life of the electronic product that uses this routine wafer fuse because of overheated electric current in safe range.
Yet the production method of heat-conducting layer more can be shown in figure 19 in this example, at the beginning like step 301; Please refer to Figure 20, sputter layer of metal Seed Layer 331 on substrate body 31 one of them side 313 is next like step 302; And it is shown in figure 21; In metal seed layer 331 impression one deck photoresistance films 351, the light shield that photoresistance film 351 is covered and exposed to the open air to a part is set on photoresistance film 351 again, again photoresistance film 351 is made public and the development operation; The part that makes photoresistance film 351 do not covered by light shield changes phase structure and is retained on the metal seed layer 331; Then, metal seed layer 331 is electroplated and the etching operation, just subsequently remaining photoresistance film 351 is removed like step 303; Promptly form one deck such as Figure 22 and the heat-conducting layer that is formed with a gap 335 33 shown in Figure 23; And heat-conducting layer 33 is distinguished into the heat-conducting parts 337,338 of two different sizes, makes the scope of heat-conducting part 338 counter element portions greater than another heat-conducting part 337, makes this routine gap 335 be formed in and supplies to be provided with the off-centered position that blown fuse portion is provided with.
Because this routine heat-conducting layer is formed with a gap; Therefore in the middle of the manufacturing process of this routine wafer fuse; Intermediary layer takes place do not smear evenly, or long-time conducting electric energy makes the intermediary layer temperature influence and produces when rotten, the gap that still can see through formation contacts to heat-conducting layer and the safe disrupted configuration of electrification as two end in contact of blown fuse portion or little; And; After blown fuse portion two ends connect electric energy, be that heat produces highest point at the center position that connects two ends, the heat dissipating layer that therefore has the gap of off-center position can effectively carry out thermal conductance and leave; Make the center heat produce highest point and still can dispel the heat smoothly, increase the radiating efficiency of this routine wafer fuse.
The utlity model has the 3rd preferred embodiment of the wafer circuit element of heat-conducting layer, wherein the wafer circuit element is to be illustrated as a wafer inductance in this example, and production method is shown in figure 24; Like step 401, please refer to one deck intermediary layer 35 that on heat-conducting layer 43, impresses equally shown in Figure 25, next like step 402; Intermediary layer 35 is carried out exposure operation and changes its phase structure, then like step 403, and shown in figure 26; Another layer of sputter metal seed layer 432 on intermediary layer 35; And be coated with one deck photoresistance film 452 again, and and a light shield with predetermined pattern is covered in makes public on the photoresistance film 452 and the development operation, make part that photoresistance film 452 is not covered by light shield change phase structure and be retained on the metal seed layer 432; Next like step 404; Metal seed layer 432 is electroplated and the etching operation, just remaining photoresistance film 452 is removed subsequently, what form promptly that spiral inductance body 45 shown in figure 27 and two confessions connect connects end 46.
Next like step 405, in the lump with reference to shown in Figure 28, with the two ends of inductance body 45 respectively routing connect to connecting end 46; And on inductance body 45, impressing one deck packaging protection layer 49 again, step 406 separates into number row along the vertical direction with the full wafer substrate for another example; And be stacked into shown in figure 29; Make two ora terminalis 411 of each substrate body 41 be exposed to graphic about the outside, again with sputter and electroplate and form a pair of connecting to the termination electrode that connects end 46 47, step 407 for another example at last; Each substrate body 41 is separated into particle one by one, just form wafer inductance shown in figure 30.
Because the wafer circuit element with heat-conducting layer that the utility model disclosed not only can see through heat dissipating layer increase wafer circuit element and receive the electric thermal conductance that produces heat energy from efficient, and safety is in the use considered; More can on heat dissipating layer, form a gap; Connect when two end in contact of element portion or little contact to cause because of carelessness to heat-conducting layer, the gap of formation can be as the disrupted configuration of safety, moreover; The formed gap of the heat dissipating layer of the utility model more can be formed on the off-center position of the set scope of circuit element; Because the heat that element portion produces when receiving electricity is to concentrate on two centre that connect between the end, therefore have the gap and be formed on the heat that off-center position heat dissipating layer can be efficient connects the centre between the end with two of element portion and carry out diversion, reach the lifting of whole work efficiency; And make increase useful life; And, for wafer fuse, the reduction of ambient temperature; The situation that can avoid causing element to produce misoperation because temperature is too high takes place, and reaches above-mentioned all purposes.
The above is merely the preferred embodiment of the utility model; When not limiting the scope that the utility model is implemented with this; Be that all simple equivalent of doing according to the utility model application claims and description change and modify, all should still belong in the scope that the utility model patent contains.
Claims (7)
1. the wafer circuit element with heat-conducting layer is characterized in that, comprising:
A slice substrate body, have two ora terminalis, and two connect aforementioned ora terminalis and side respect to one another respectively;
One deck is formed at the heat-conducting layer of last, corresponding above-mentioned two ora terminalis in one of above-mentioned side;
One deck is bonded to the intermediary layer on this heat-conducting layer;
One deck is bonded to the impedance layer on this intermediary layer, comprise two corresponding respectively above-mentioned two ora terminalis connect the end, and one connect the aforementioned element portion that connects the end; And
A pair of respectively to aforementioned two ora terminalis that should substrate body and connect aforementioned two termination electrodes that connect the end that this connects impedance layer respectively.
2. wafer circuit element as claimed in claim 1 is characterized in that, wherein this heat-conducting layer more comprises two heat-conducting parts, reaches a gap that is formed between aforementioned heat-conducting part.
3. wafer circuit element as claimed in claim 2; It is characterized in that; Wherein above-mentioned two heat-conducting parts corresponding respectively above-mentioned two of this heat-conducting layer connect the end; And one of above-mentioned two heat-conducting parts greater than another person, make this gap be formed in the position of departing from this element portion center to scope that should element portion.
4. like claim 1,2 or 3 described wafer circuit elements, it is characterized in that, comprise that more one deck is arranged on this impedance layer and supplies above-mentioned termination electrode to being exposed to its outer packaging protection layer.
5. like claim 1,2 or 3 described wafer circuit elements, it is characterized in that wherein this heat-conducting layer is to be selected from the set that copper, silver, gold, titanium, titanium alloy, nickel, nickel alloy, nichrome constitute; And this substrate body is aluminium oxide or aluminium nitride material.
6. like claim 1,2 or 3 described wafer circuit elements, it is characterized in that wherein this element portion is a resistance body.
7. like claim 1,2 or 3 described wafer circuit elements, it is characterized in that wherein this element portion is an inductance body.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011204185085U CN202423255U (en) | 2011-10-28 | 2011-10-28 | Wafer circuit element with heat conduction layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011204185085U CN202423255U (en) | 2011-10-28 | 2011-10-28 | Wafer circuit element with heat conduction layer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202423255U true CN202423255U (en) | 2012-09-05 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011204185085U Expired - Fee Related CN202423255U (en) | 2011-10-28 | 2011-10-28 | Wafer circuit element with heat conduction layer |
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| Country | Link |
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| CN (1) | CN202423255U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109714916A (en) * | 2017-10-25 | 2019-05-03 | 日进材料股份有限公司 | Impact absorbing composite sheet |
| TWI779973B (en) * | 2021-12-22 | 2022-10-01 | 天二科技股份有限公司 | Chip resistor and method of making the same |
-
2011
- 2011-10-28 CN CN2011204185085U patent/CN202423255U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109714916A (en) * | 2017-10-25 | 2019-05-03 | 日进材料股份有限公司 | Impact absorbing composite sheet |
| TWI779973B (en) * | 2021-12-22 | 2022-10-01 | 天二科技股份有限公司 | Chip resistor and method of making the same |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120905 Termination date: 20191028 |