TWI776357B - Memory device - Google Patents

Abstract

A memory device includes a source element, a drain element, channel layers, control electrode layers, and a memory layer. The channel layers are individually electrically connected between the source element and the drain element. Memory cells are defined in the memory layer between the control electrode layers and the channel layers.

Description

memory device

The present invention relates to a memory device.

In recent years, the size of semiconductor devices has been gradually reduced. In semiconductor technology, feature size reduction, improvement in speed, performance, density, and cost per unit of integrated circuit are all important goals.

The present invention relates to a memory device with excellent operating performance.

According to an aspect of the present invention, a memory device is provided, which includes a source element, a drain element, a plurality of channel layers, a plurality of control electrode layers, and a memory layer. The channel layer is independently electrically connected between the source element and the drain element. Several memory cells are defined in the memory layer between the control electrode layer and the channel layer.

According to another aspect of the present invention, a memory device is provided, which includes a channel element, a plurality of control electrode layers and a memory layer. The channel element includes a plurality of thicker channel portions and a plurality of thinner channel portions that are electrically connected. Several memory cells are defined in the memory layer between the thicker channel portion and the control electrode layer.

According to yet another aspect of the present invention, a memory device is provided, which includes a plurality of control electrode layers, a plurality of channel layers and a memory layer. The channel layer is alternately arranged and overlapped with the control electrode layer in a first direction. Several memory cells are defined in the memory layer between the control electrode layer and the channel layer.

In order to have a better understanding of the above-mentioned and other aspects of the present invention, the following specific examples are given and described in detail in conjunction with the accompanying drawings as follows:

In a concept of the present disclosure, the channel layer of the memory device can overlap with the control electrode layer in different directions, so the active channel portion corresponding to the memory cell can have a larger effective channel width, thereby improving the operation performance of the memory device . In another concept of the present disclosure, the channel layer can be independently electrically connected between the source element and the drain element, thus avoiding interference between adjacent memory cells during operation. In yet another concept of the present disclosure, the channel element of the memory device includes a thicker channel portion and a thinner channel portion, wherein the thicker channel portion is an active channel portion corresponding to the memory cell, so the memory device can have a higher memory cell currents. The following embodiments take a 3D AND memory device as an example to illustrate, but the present disclosure is not limited thereto.

The following are some examples to illustrate. It should be noted that this disclosure does not show all possible embodiments, and other implementation aspects not proposed in this disclosure may also be applicable. Furthermore, the size ratios in the drawings are not drawn according to the actual product scale. Therefore, the contents of the description and illustrations are only used to describe the embodiments, rather than to limit the protection scope of the present disclosure. In addition, the descriptions in the embodiments, such as detailed structures, process steps, and material applications, etc., are for illustrative purposes only, and are not intended to limit the scope of protection of the present disclosure. The details of the steps and structures of the embodiments can be changed and modified according to the needs of the actual application process without departing from the spirit and scope of the present disclosure. In the following, the same/similar symbols are used to represent the same/similar elements for description.

1A to 1D are used to illustrate a memory device in one embodiment.

Please refer to Figures 1A to 1C. FIG. 1A and FIG. 1C are cross-sectional views respectively drawn along line AA and line CC in the perspective view of FIG. 1B .

The control electrode layer 100 and the insulating layer 200 are alternately arranged on the substrate 300 in the first direction D1 (eg, the vertical direction, or the Z direction, or the normal direction of the upper surface of the substrate 300 ). The control electrode layers 100 are separated from each other by the insulating layer 200 . The channel layer 400 and the insulating layer 200 are alternately arranged in the first direction D1.

The control electrode layer 100 includes a dry electrode 110 , a first branch electrode 120 and a second branch electrode 130 . The dry electrode 110 may be electrically connected between the first branch electrode 120 and the second branch electrode 130 . The control electrode layer 100 includes a first electrode surface 111 of the dry electrode 110 , a second electrode surface 122 of the first branch electrode 120 and a third electrode surface 133 of the second branch electrode 130 . The first electrode surface 111 is between the second electrode surface 122 and the third electrode surface 133 . The first electrode surface 111 is a longitudinal electrode surface or a sidewall electrode surface. The second electrode surface 122 and the third electrode surface 133 are lateral electrode surfaces facing each other. The second electrode surface 122 is the electrode surface facing toward the substrate 300 . The third electrode surface 133 is the electrode surface facing away from the substrate 300 . The control electrode layer 100 further includes a fourth electrode surface 124 of the first branch electrode 120 and a fifth electrode surface 135 of the second branch electrode 130 . The second electrode surface 122 of the first branch electrode 120 is between the first electrode surface 111 of the dry electrode 110 and the fourth electrode surface 124 of the first branch electrode 120 . The third electrode surface 133 of the second branch electrode 130 is between the first electrode surface 111 of the dry electrode 110 and the fifth electrode surface 135 of the second branch electrode 130 . In an embodiment, the control electrode layer 100 may be used as a word line.

The branch electrodes of the control electrode layer 100 (including the first branch electrode 120 and the second branch electrode 130 ) and the channel layer 400 are arranged alternately in the first direction D1 . The channel layer 400 is overlapped between the first branch electrode 120 and the second branch electrode 130 of the control electrode layer 100 . The dry electrode 110 of the control electrode layer 100 may overlap with the channel layer 400 in the second direction D2. The channel layer 400 is between the first electrode surface 111 of the dry electrode 110 , the second electrode surface 122 of the first branch electrode 120 and the third electrode surface 133 of the second branch electrode 130 . The second direction D2 may be a lateral direction substantially perpendicular to the first direction D1, such as a horizontal direction, an X direction, a Y direction, or any lateral direction on the X-Y plane.

The channel layer 400 includes a first channel surface 401 , a second channel surface 402 and a third channel surface 403 . The first channel surface 401 is between the second channel surface 402 and the third channel surface 403 . The first channel surface 401 is a longitudinal channel surface or a sidewall channel surface. The second channel surface 402 and the third channel surface 403 are transverse channel surfaces facing away from each other. The second channel surface 402 is the channel surface facing away from the substrate 300 . The third channel surface 403 is the channel surface facing towards the substrate 300 .

The first channel surface 401 and the first electrode surface 111 face each other and overlap in the second direction D2. The second channel surface 402 and the second electrode surface 122 face each other and overlap in the first direction D1. The third channel surface 403 and the third electrode surface 133 face each other and overlap in the first direction D1.

In this embodiment, the dimension CS of the channel layer 400 in the first direction D1 is smaller than the dimension ES1 of the dry electrode 110 of the control electrode layer 100 in the first direction D1, and also smaller than the dimension ES1 of the first electrode surface 111 of the dry electrode 110 in the first direction D1. Dimension ES2 in one direction D1.

The memory layer 500 may include a first memory layer part 510 , a second memory layer part 520 and a third memory layer part 530 . The first memory layer part 510 is between the second memory layer part 520 and the third memory layer part 530 . The first memory layer part 510 may be between the first channel surface 401 of the channel layer 400 and the first electrode surface 111 of the control electrode layer 100 . The second memory layer part 520 may be between the second channel surface 402 of the channel layer 400 and the second electrode surface 122 of the control electrode layer 100 . The third memory layer part 530 may be between the third channel surface 403 of the channel layer 400 and the third electrode surface 133 of the control electrode layer 100 . The memory layer 500 may further include a fourth memory layer part 540 . The fourth memory layer part 540 is connected between the second memory layer part 520 and the third memory layer part 530 . The fourth memory layer portion 540 is on the fourth electrode surface 124 of the first branch electrode 120 and on the fifth electrode surface 135 of the second branch electrode 130 . The channel layer 400 is separated from each other in the first direction D1 by the second memory layer part 520 , the third memory layer part 530 and the fourth memory layer part 540 of the memory layer 500 .

There is a first interface between the channel layer 400 and the memory layer 500 . In this embodiment, the first interface includes a first channel surface 401 , a second channel surface 402 and a third channel surface 403 . The first interface is a curved surface with an included angle (eg, 90 degrees, an acute angle or an obtuse angle) including the first channel surface 401 , the second channel surface 402 and the third channel surface 403 . There is a second interface between the control electrode layer 100 and the memory layer 500 . In this embodiment, the second interface includes a first electrode surface 111 , a second electrode surface 122 , a third electrode surface 133 , a fourth electrode surface 124 and a fifth electrode surface 135 . The second interface may be an interface having an included angle (eg, 90 degrees, an acute angle or an obtuse angle) including the first electrode surface 111 , the second electrode surface 122 , the third electrode surface 133 , the fourth electrode surface 124 and the fifth electrode surface 135 . Bend face. In this embodiment, the first interface and the second interface include bending surfaces with similar or identical bending profiles. The memory cells may be defined in the first memory layer part 510 , the second memory layer part 520 and the third memory layer part 530 of the memory layer 500 between the first interface and the second interface.

Please refer to Figures 1B to 1D. FIG. 1D only shows the source element 610 , the drain element 620 and the channel layer 400 . Source element 610 and drain element 620 may be separated from each other by insulating element 700 (FIGS. 1A-1C). The source element 610 and the drain element 620 may be electrode posts extending in the first direction D1. The channel layer 400 may be disposed outside the source element 610 , the drain element 620 and the insulating element 700 . The channel layer 400 is electrically connected between the source element 610 and the drain element 620 . In detail, in this embodiment, the channel layers 400 separated from each other are independently electrically connected between the source element 610 and the drain element 620 .

FIG. 14 shows a memory device of a comparative example, which has the channel film 470C extending in the first direction D1 and overlapping the control electrode layer 100 only in the second direction D2. Compared with the memory device of the comparative example, the memory device of the embodiment described with reference to FIGS. 1A to 1D can have at least the following advantages. In the embodiment, the channel layer 400 and the control electrode layer 100 are overlapped in the first direction D1 and the second direction D2 which are substantially perpendicular to each other, so the channel layer 400 corresponding to the memory cell can have a larger effective channel width, so that the memory The bulk device can have better operating performance, such as a faster programming rate. The memory device of the embodiment may have a larger incremental pulse programming (ISPP) slope and programming window (PGM window). In the embodiment, the channel layer 400 is electrically connected between the source element 610 and the drain element 620 independently, so that interference between adjacent memory cells can be avoided during operation. However, in the memory device of the comparative example of FIG. 14, the portion of the channel film 470C between the control electrode layers 100 may cause a leakage current path during the operation of the memory cell and cause interference.

2A to 2D are used to illustrate a memory device in another embodiment.

Please refer to FIG. 2A and FIG. 2C, which are cross-sectional views drawn along line AA and line CC in the perspective view of FIG. 2B, respectively. The control electrode layer 100 includes a first electrode surface 111 , a second electrode surface 122 and a third electrode surface 133 . The first electrode surface 111 is between the opposing second electrode surface 122 and the third electrode surface 133 . The first electrode surface 111 may be a longitudinal electrode surface or a sidewall electrode surface. The first electrode surface 111 may be a curved surface. The second electrode surface 122 and the third electrode surface 133 are lateral electrode surfaces facing away from each other. The second electrode surface 122 is the electrode surface facing away from the substrate 300 . The third electrode surface 133 is an electrode surface facing toward the substrate 300 .

The control electrode layer 100 includes a dry electrode 110 , a first branch electrode 120 and a second branch electrode 130 . The dry electrode 110 may be electrically connected between the first branch electrode 120 and the second branch electrode 130 . The first electrode surface 111 of the control electrode layer 100 includes the electrode surfaces of the dry electrode 110 , the first branch electrode 120 and the second branch electrode 130 .

Channel element 460 includes channel membrane 470 and channel layer 400 .

The channel membrane 470 may include a first channel membrane part 471 and a second channel membrane part 472 . The first channel membrane portion 471 has a first channel surface 4711 . The second channel membrane portion 472 has a second channel surface 4722 . The channel layer 400 may be on the first channel surface 4711 of the first channel membrane part 471 . The insulating layer 200 may be on the second channel surface 4722 of the second channel membrane portion 472 . The channel layers 400 are separated from each other in the first direction D1 , and may be electrically connected to each other via the adjacent first channel membrane portions 471 and the second channel membrane portions 472 connected between the first channel membrane portions 471 .

The channel layer 400 may be formed by deposition. In one embodiment, the channel layer 400 is formed by epitaxial growth from the first channel surface 4711 of the first channel film portion 471 . In one embodiment, the channel layer 400 may have a lens-like structure. The dimension of the channel layer 400 in the first direction D1 gradually decreases toward the second direction D2 of the control electrode layer 100 . For example, a portion of the channel layer 400 near the first channel membrane portion 471 has the largest dimension in the first direction D1. A portion of the channel layer 400 away from the first channel membrane portion 471 has the smallest dimension in the first direction D1. The channel surface 404 (the sidewall channel surface) of the channel layer 400 may be a curved surface and protrude toward the direction of the control electrode layer 100 . In the embodiment, the channel layer 400 is not limited to the outline as shown in the figure, but may include a first channel layer 471 formed on the first channel film portion 471 by deposition, or epitaxially grown from the first channel film portion 471 . Any possible contour formed by the channel surface 4711.

The branch electrodes of the control electrode layer 100 (including the first branch electrode 120 and the second branch electrode 130 ) and the channel layer 400 may be arranged alternately in the first direction D1 . The channel layer 400 may overlap between the first branch electrode 120 and the second branch electrode 130 of the control electrode layer 100 in the first direction D1. The dry electrode 110 of the control electrode layer 100 may overlap with the channel layer 400 in the second direction D2. However, the present disclosure is not limited thereto.

The channel element 460 includes a thicker channel portion 461 and a thinner channel portion 462 . The thicker channel portion 461 includes the channel layer 400 and the first channel film portion 471 of the channel film 470 . The thinner channel portion 462 includes, or consists of, the second channel membrane portion 472 of the channel membrane 470 . The dimension CS1 of the thicker channel portion 461 in the second direction D2 is greater than the dimension CS2 of the thinner channel portion 462 in the second direction D2.

The memory layer 500 may include a first memory layer part 510 , a second memory layer part 520 and a third memory layer part 530 . The first memory layer part 510 is between the second memory layer part 520 and the third memory layer part 530 . The first memory layer part 510 may be between the channel surface 404 of the channel layer 400 and the first electrode surface 111 of the control electrode layer 100 . The second memory layer part 520 may be between the second electrode surface 122 of the control electrode layer 100 and the lower insulating surface of the insulating layer 200 . The third memory layer part 530 may be between the third electrode surface 133 of the control electrode layer 100 and the upper insulating surface of the insulating layer 200 . The control electrode layer 100 is on the sidewall channel surface of the thicker channel portion 461 (or the channel surface 404 of the channel layer 400 ). The insulating layer 200 is on the sidewall channel surface of the thinner channel portion 462 (or the second channel membrane portion 472).

The channel surface 404 of the channel layer 400 may adjoin the memory layer 500, so the first interface between the channel layer 400 and the memory layer 500 may be a curved surface. The first electrode surface 111 of the control electrode layer 100 may be a curved surface with a complementary profile to the channel surface 404 . The first electrode surface 111 of the control electrode layer 100 may be adjacent to the first memory layer portion 510 of the memory layer 500 , so the second interface between the control electrode layer 100 and the first memory layer portion 510 may be a curved surface. The first interface and the second interface may have similar or the same bending direction. The memory cells may be defined in the first memory layer portion 510 of the memory layer 500 .

Please refer to Figures 2A to 2D. FIG. 2D only shows the source element 610 , the drain element 620 and the channel element 460 . The channel element 460 is outside the source element 610 and the drain element 620 and is electrically connected between the source element 610 and the drain element 620 .

FIG. 14 shows the memory device of the comparative example, which only has the channel film 470C extending in the first direction D1, and the channel film 470C has a uniform size (ie, uniform thickness) in the second direction D2. Compared with the memory device of the comparative example, the memory device of the embodiment described with reference to FIGS. 2A to 2D can have at least the following advantages. In the embodiment, the thicker channel portion 461 and the control electrode layer 100 are overlapped in the first direction D1 and the second direction D2 that are substantially perpendicular to each other, so the thicker channel portion 461 corresponding to the memory cell can have a larger effective channel. Therefore, the memory device can have better operating performance, such as a faster programming rate. In the embodiment, the active channel portion corresponding to the memory cell is the thicker channel portion 461 , and its thickness (or dimension in the second direction D2 ) is larger than that of the thinner channel portion 462 (or the channel membrane) between the control electrode layers 100 . 470/470C), so the memory device can have higher memory cell current.

3A to 9C illustrate a method of manufacturing a memory device in one embodiment.

Referring to FIG. 3A and FIG. 3B , the insulating layer 200 and the first material layer 810 can be alternately stacked on the substrate 300 by means of deposition to form a stacked structure. The substrate 300 may, for example, comprise silicon or other semiconductor materials. The material of the insulating layer 200 may be different from the first material layer 810 . In one embodiment, the insulating layer 200 may include oxide such as silicon oxide, and the first material layer 810 may include nitride such as silicon nitride. However, the present disclosure is not limited thereto. Openings 820 are formed in the stacked structure.

Referring to FIG. 4 , the part of the first material layer 810 exposed by the opening 820 can be removed by means of etch-back to form the cavity 830 between the insulating layers 200 .

Referring to FIG. 5, the second material layer 840 can be formed on the substrate 300 and the stacked structure by means of deposition. The second material layer 840 may be formed on the sidewall surface of the first material layer 810 exposed by the cavity 830 and the lower insulating surface and the upper insulating surface of the insulating layer 200 . The second material layer 840 may be formed on the sidewall insulating surface of the insulating layer 200 exposed by the opening 820 and the upper surface of the substrate 300 . Also, the second material layer 840 may be formed on the upper surface of the topmost insulating layer 200 . The material of the second material layer 840 may be the same as that of the first material layer 810 . In one embodiment, the second material layer 840 may include nitride such as silicon nitride. However, the present disclosure is not limited thereto.

Referring to FIG. 6 , the portion of the second material layer 840 in the opening 820 and the upper surface of the topmost insulating layer 200 can be removed by etching, and the portion in the cavity 830 is left.

Please refer to Figures 7A to 7C. FIGS. 7A and 7C are cross-sectional views taken along lines AA and CC in the perspective view of FIG. 7B, respectively. The memory layer 500 can be formed on the substrate 300 exposed by the opening 820 and on the insulating surface of the sidewall of the insulating layer 200 by using a deposition method, and on the second material layer 840 exposed by the cavity 830 . In one embodiment, the memory layer 500 may include an oxide-nitride-oxide (ONO) structure, such as an oxide layer 571 , a nitride layer 572 and an oxide layer 573 . However, the present disclosure is not limited thereto, and the memory layer 500 may include any charge trapping structure, such as an ONONO structure, an ONONONO structure, or a BE-SONOS structure. For example, the charge trapping layer can use nitride such as silicon nitride, or other similar high dielectric constant materials including metal oxides such as aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), etc. . The channel layer 400 may be formed on the memory layer 500 exposed by the cavity 830 using a deposition method. The channel layer 400 may include silicon, such as polysilicon or monocrystalline silicon, or other semiconductor materials. The insulating element 700 may be formed in the opening 820 using a deposition method. The insulating element 700 may include an oxide such as silicon oxide. However, the present disclosure is not limited thereto. The source element 610 and the drain element 620 may be formed in the insulating element 700 using a deposition method. The source element 610 and the drain element 620 may comprise silicon, such as polysilicon or monocrystalline silicon, or other semiconductor materials.

Please refer to Figures 8A to 8C. FIGS. 8A and 8C are cross-sectional views respectively drawn along lines AA and CC in the perspective view of FIG. 8B. The first material layer 810 and the second material layer 840 may be removed by an etching method to form slits 850 between the insulating layers 200 .

Please refer to Figures 9A to 9C. FIGS. 9A and 9C are cross-sectional views respectively drawn along lines AA and CC in the perspective view of FIG. 9B . The control electrode layer 100 may be formed to fill the slit 850 using a deposition method. The control electrode layer 100 may include metals such as tungsten, or other conductive materials.

FIGS. 10A to 13 illustrate a method for manufacturing a memory device in another embodiment. In one embodiment, the manufacturing steps described with reference to FIGS. 10A to 10B may be performed after the fabrication steps described with reference to FIGS. 3A and 3B are performed.

Please refer to Figures 10A to 10C. FIGS. 10A and 10C are cross-sectional views respectively drawn along lines AA and CC in the perspective view of FIG. 10B . The channel film 470 may be formed on the sidewall surface of the first material layer 810 exposed by the opening 820 and the sidewall insulating surface of the insulating layer 200 . The first channel film portion 471 of the channel film 470 may be on the first material layer 810 . The second channel film portion 472 of the channel film 470 may be on the insulating layer 200 . The channel film 470 may include silicon, such as polysilicon or monocrystalline silicon, or the like. The insulating element 700 may be formed in the opening 820 . Source element 610 and drain element 620 may be formed in insulating element 700 and on the sidewall channel surfaces of channel film 470 .

Please refer to Figure 11A and Figure 11B. Fig. 11A is a cross-sectional view taken along line AA in the perspective view of Fig. 11B. The first material layer 810 may be removed to form the slits 850 between the insulating layers 200 and expose the first channel surface 4711 of the first channel membrane portion 471 .

Please refer to Figure 12A and Figure 12B. Fig. 12A is a cross-sectional view taken along line AA in the perspective view of Fig. 12B. The channel layer 400 may be formed on the first channel film part 471 . The channel layer 400 may include silicon, such as polysilicon or monosilicon, or the like. The channel layer 400 may be formed by deposition. In one embodiment, the channel layer 400 adjacent to the first channel surface 4711 can be grown from the first channel surface 4711 of the first channel film portion 471 exposed by the slit 850 by using a selective epitaxy method. In one embodiment, the epitaxially formed channel layer 400 has a profile that is thinner at opposite ends and gradually thicker toward the middle. In the embodiment, the channel layer 400 is not limited to the outline as shown in the figure, but may include a first channel layer 471 formed on the first channel film portion 471 by deposition, or epitaxially grown from the first channel film portion 471 . Any possible contour formed by the channel surface 4711. For example, the channel surface 404 of the channel layer 400 may be a curved surface, a flat surface, or a non-flat surface.

Referring to FIG. 13 , the memory layer 500 can be formed on the channel surface 404 of the channel layer 400 exposed by the slit 850 and the upper and lower insulating surfaces of the insulating layer 200 . In one embodiment, the memory layer 500 may include an oxide-nitride-oxide (ONO) structure, such as an oxide layer 571 , a nitride layer 572 and an oxide layer 573 . However, the present disclosure is not limited thereto. The control electrode layer 100 may be formed on the memory layer 500 exposed by the slit 850 .

To sum up, although the present invention has been disclosed by the above embodiments, it is not intended to limit the present invention. Those skilled in the art to which the present invention pertains can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the appended patent application.

100: Control electrode layer 110: Cadre electrode 111: first electrode surface 120: The first branch electrode 122: second electrode surface 124: Fourth electrode surface 130: The second branch electrode 133: third electrode surface 135: Fifth electrode surface 200: Insulation layer 300: base 400: channel layer 401: First channel surface 402: Second channel surface 403: Third channel surface 404: Channel Surface 460: Channel Element 461: Thicker channel part 462: Thinner channel part 470, 470C: Channel membrane 471: The first channel membrane part 4711: First channel surface 472: Second channel membrane part 4722: Second channel surface 500: Memory Layer 510: The first memory layer 520: Second Memory Layer Department 530: The third memory layer 540: Fourth Memory Layer 571, 573: Oxide layer 572: Nitride layer 610: Source element 620: drain element 700: Insulation element 810: First Material Layer 820: Opening 830: Hole 840: Second Material Layer 850: Slit CS, CS1, CS2, ES1, ES2: Dimensions D1: first direction D2: Second direction

FIG. 1A shows a cross-sectional view of a memory device according to an embodiment. FIG. 1B is a perspective view of a memory device according to an embodiment. FIG. 1C is a cross-sectional view of a memory device according to an embodiment. FIG. 1D shows the source element, drain element and channel layer of the memory device of the embodiment. FIG. 2A shows a cross-sectional view of a memory device according to an embodiment. FIG. 2B is a perspective view of a memory device according to an embodiment. FIG. 2C is a cross-sectional view of a memory device according to an embodiment. FIG. 2D illustrates the source element, the drain element and the channel element of the memory device of the embodiment. 3A to 9C illustrate a method of manufacturing a memory device in one embodiment. FIGS. 10A to 13 illustrate a method for manufacturing a memory device in another embodiment. FIG. 14 shows a memory device of a comparative example.

400: channel layer 610: Source element 620: drain element

Claims (10)

A memory device comprising: a source element; a drain element; a plurality of channel layers independently electrically connected between the source element and the drain element; a plurality of control electrode layers; and a memory layer, wherein several memory cells are defined in the memory layer between the control electrode layers and the channel layers. The memory device of claim 1, wherein the channel layers are separated from each other in a vertical direction by the memory layer. The memory device of claim 1 , wherein each of the channel layers and the memory layer has a first interface, and the first interfaces include bending surfaces. A memory device comprising: a channel element, comprising a plurality of thicker channel portions and a plurality of thinner channel portions electrically connected; a plurality of control electrode layers; and a memory layer, wherein several memory cells are defined in the memory layer between the thicker channel portions and the control electrode layers. The memory device of claim 4, wherein the thicker channel portions and the thinner channel portions are interleaved. The memory device of claim 4, further comprising: a source element; and a drain element, wherein the channel element is electrically connected between the source element and the drain element. The memory device of claim 4, further comprising a plurality of insulating layers, wherein the control electrode layers are alternately arranged with the insulating layers, the control electrode layers are on the sidewall channel surfaces of the thicker channel portions, The insulating layers are on the sidewall channel surfaces where the thinner channel portions are. The memory device of claim 4, wherein each of the thicker channel portions and the memory layer has a first interface, and the first interfaces are curved surfaces. A memory device comprising: Several control electrode layers; a plurality of channel layers alternately arranged and overlapped with the control electrode layers in a first direction; and a memory layer, wherein several memory cells are defined in the memory layer between the control electrode layers and the channel layers. The memory device of claim 9, further comprising: a source element; and a drain element, wherein the channel layers are electrically connected between the source element and the drain element.

Images