TWI773495B - 晶片封裝結構及其形成方法 - Google Patents

晶片封裝結構及其形成方法 Download PDF

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TWI773495B
TWI773495B TW110131056A TW110131056A TWI773495B TW I773495 B TWI773495 B TW I773495B TW 110131056 A TW110131056 A TW 110131056A TW 110131056 A TW110131056 A TW 110131056A TW I773495 B TWI773495 B TW I773495B
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Taiwan
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chip package
thermally conductive
conductive structure
retaining ring
heat
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TW110131056A
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TW202234616A (zh
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林昱聖
林柏堯
葉書伸
汪金華
鄭心圃
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台灣積體電路製造股份有限公司
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Publication of TW202234616A publication Critical patent/TW202234616A/zh

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Abstract

提供晶片封裝結構的形成方法。所述方法包括設置晶片封裝於配線基板上。所述方法包括形成第一導熱結構及第二導熱結構於晶片封裝上。第一導熱結構及第二導熱結構被第一間隙分開。所述方法包括透過第一導熱結構及第二導熱結構接合散熱蓋至晶片封裝。在接合散熱蓋至晶片封裝期間，第一導熱結構及第二導熱結構朝向彼此延伸，直到第一導熱結構接觸第二導熱結構。

Description

晶片封裝結構及其形成方法
本發明實施例是關於晶片封裝結構，特別是關於具有的晶片封裝結構及其製造方法。
半導體裝置用於各種電子產品，例如：個人電腦、手機、數位相機及其他電子設備。半導體裝置的製造通常是透過在半導體基底上依序沉積絕緣或介電層、導電層及半導體層，並使用微影將各種材料層圖案化，以形成電路組件和元件。
通常在單一半導體晶圓上製造數十個或數百個積體電路。沿著劃線（scribe line）鋸割積體電路，使個別的晶粒單體化（singulated）。然後分別地封裝個別的晶粒。半導體產業持續地降低最小部件尺寸以繼續改善各種電子組件（例如，電晶體、二極體、電阻器、電容器等等）的積體密度（integration density），使更多組件得以整合至給定的面積。然而，更多的組件產生更多的熱。因此，如何改善晶片封裝結構的散熱效率成為目前的挑戰。
本發明實施例提供一種晶片封裝結構的形成方法，包括：設置晶片封裝於配線基板上；形成第一導熱結構及第二導熱結構於晶片封裝上，其中第一導熱結構及第二導熱結構被第一間隙分開；以及透過第一導熱結構及第二導熱結構接合散熱蓋至晶片封裝，其中在接合散熱蓋至晶片封裝期間，第一導熱結構及第二導熱結構朝向彼此延伸，直到第一導熱結構接觸第二導熱結構。
本發明實施例提供一種晶片封裝結構的形成方法，包括：設置晶片封裝於配線基板上；形成導熱結構及擋環於晶片封裝上，其中擋環圍繞導熱結構，擋環及導熱結構被第一間隙分開，且擋環具有連通第一間隙的第二間隙；以及透過導熱結構及擋環接合散熱蓋至晶片封裝，其中在接合散熱蓋至晶片封裝期間，導熱結構及擋環朝向彼此延伸，直到導熱結構接觸擋環。
本發明實施例提供一種晶片封裝結構，包括：配線基板；晶片封裝，位於配線基板上；第一導熱結構，位於晶片封裝上；擋環，位於晶片封裝上且圍繞第一導熱結構，其中擋環具有間隙；以及散熱蓋，位於第一導熱結構及擋環上。
以下揭露提供了許多的實施例或範例，用於實施本發明實施例之不同元件。各元件及其的具體範例描述如下，以簡化本發明實施例之說明。當然，這些僅僅是範例，並非用以限定本發明實施例。舉例而言，敘述中若提及第一元件形成在第二元件之上，可能包含第一及第二元件直接接觸的實施例，也可能包含額外的元件形成在第一及第二元件之間，使得它們不直接接觸的實施例。此外，本發明實施例可能在各種範例中重複參考符號以及/或字母。如此重複是為了簡明及清楚之目的，而非用以表示所討論的不同實施例及/或配置之間的關係。
此外，其中可能用到與空間相對用詞，例如「在……之下」、「下方」、「較低的」、「上方」、「較高的」等類似用詞，是為了便於描述圖式中一個（些）部件或特徵與另一個（些）部件或特徵之間的關係。空間相對用詞用以包括使用中或操作中的裝置之不同方位，以及圖式中所描述的方位。當裝置被轉向不同方位時（旋轉90度或其他方位），其中所使用的空間相對形容詞也將依轉向後的方位來解釋。
本發明所屬技術領域中具有通常知識者應理解說明書中的用語「實質上」，例如「實質上平坦」或「實質上共平面」等等。在一些實施例中，可以移除用於形容的實質上。在適用的情況下，用語「實質上」還可以包括具有「完全地（entirely）」、「完全地（completely）」、「全部（all）」等等的實施例。在不同技術中，用語「實質上」可以不同且在本發明所屬技術領域中具有通常知識者理解的偏差範圍內。舉例而言，用語「實質上」也可關於所敘述的90%或更高，例如所敘述的95%或更高，特別是所敘述的99%或更高，包括所敘述的100%，但本發明不限於此。此外，用語如「實質上平行」或「實質上垂直」可解釋為不排除從特定設置的非顯著偏差且可包括，例如，10°的偏差。「實質上」一詞不排除「完全」，例如，「實質上不包含（substantially free）」Y的組成可能完全不包含Y。
在不同技術中，用語「大約（about）」可以不同且在本發明所屬技術領域中具有通常知識者理解的偏差範圍內。用語「大約」結合特定距離或尺寸解釋為不排除從所述特定距離或尺寸的非顯著偏差。舉例而言，用語「大約」可包括所敘述的10%的偏差，但本發明不限於此。與數值x相關的用語「大約」可表示所敘述的x ±5％或10％，但本發明不限於此。
以下敘述一些本發明實施例。在這些實施例中所述的多個階段之前、期間及/或之後，可提供額外的步驟。一些所述階段在不同實施例中可被替換或刪去。半導體裝置結構可增加額外部件。一些所述部件在不同實施例中可被替換或刪去。儘管所討論的一些實施例以特定順序的步驟執行，這些步驟仍可以另一合乎邏輯的順序執行。
第1A-1D圖是根據一些實施例，繪示出形成晶片封裝結構的製程的各種步驟的剖面圖。如第1A圖所示，根據一些實施例，提供晶片封裝P。根據一些實施例，晶片封裝P包括重佈基板（redistribution substrate）110、晶片結構122、導電柱124、底部填充層（underfill layer）130及模造層140。
根據一些實施例，重佈基板110包括配線層112、導電通孔114、以及介電層116。根據一些實施例，配線層112及導電通孔114形成在介電層116中。如第1A圖所示，根據一些實施例，導電通孔114電性連接不同配線層112。為了簡單起見，根據一些實施例，第1A圖僅繪示出配線層112中的兩個。
根據一些實施例，介電層116由絕緣材料形成，例如聚合物材料（例如，聚苯并噁唑（polybenzoxazole）、聚醯亞胺（polyimide）、或感光材料）、氮化物（例如，氮化矽）、氧化物（例如，氧化矽）、氮氧化矽、或類似材料。
根據一些實施例，使用沉積製程（例如化學氣相沉積製程或物理氣相沉積製程）、微影製程及蝕刻製程形成介電層116。根據一些實施例，配線層112及導電通孔114由導電材料形成，例如金屬（例如，銅、鋁或鎢）或前述之合金。
根據一些實施例，透過導電柱124接合晶片結構122至重佈基板110。根據一些實施例，導電柱124物理上及電性上連接晶片結構122及重佈基板110。根據一些實施例，晶片結構122包括高性能計算（high-performance-computing，HPC）晶片、系統晶片（SoC）、系統積體電路（system on integrated circuit，SOIC）裝置、基板上晶圓上晶片（chip on wafer on substrate，CoWoS）裝置或類似裝置。
根據一些實施例，晶片結構122包括基板。在一些實施例中，基板由元素半導體材料形成，包括單晶結構、多晶結構（polycrystal structure）或非晶結構的矽或鍺。在一些其他實施例中，基板由化合物半導體形成，例如碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、合金半導體，例如矽鍺（SiGe）或磷砷化鎵（GaAsP）、或前述之組合。基板還可包括多層半導體、絕緣體上覆半導體（SOI）（例如絕緣體上覆矽或絕緣體上覆鍺）或前述之組合。
在一些實施例中，基板包括各種裝置元件。在一些實施例中，所述各種裝置元件形成於基板之中及/或之上。為了簡明及清楚的目的，所述裝置元件未在圖式中繪示。所述各種裝置元件的示例包括：主動裝置、被動裝置、其他合適的元件或前述之組合。主動裝置可以包括形成於基板表面的電晶體或二極體（未繪示）。被動裝置包括：電阻器、電容器、或其他合適的被動裝置。
舉例而言，電晶體可以是金屬氧化物半導體場效電晶體 （MOSFET）、互補金屬氧化物半導體 （CMOS） 電晶體、雙極性接面電晶體 （bipolar junction transistor，BJT）、高壓電晶體、高頻電晶體、p型通道及/或n型通道場效電晶體（PFET/NFET）等等。執行各種製程，例如前段（front-end-of-line，FEOL）半導體製造製程，以形成各種裝置元件。前段半導體製造製程可包括沉積、蝕刻、佈植、微影、退火、平坦化、一或多種其他適合的製程、或前述之組合。
在一些實施例中，隔離部件（未繪示）形成在基板中。隔離部件用於圍繞主動區並且電性隔離在主動區中的基板1022中及/或上方形成的各種裝置元件。在一些實施例中，隔離部件包括淺溝槽隔離（STI）部件、矽局部氧化（LOCOS）部件、其他合適的隔離部件或前述之組合。
在一些其他實施例中，晶片結構122包括晶片封裝結構。在一些實施例中，晶片封裝結構包括一個晶片。在一些其他實施例中，晶片封裝結構包括多個晶片，這些晶片並排設置或彼此堆疊（例如，三維（3D）封裝或三維積體電路（3DIC）裝置）。
根據一些實施例，導電柱124是由導電材料形成，例如銅（Cu）、鋁（Al）、鎢（W）、鈷（Co）、鎳（Ni）、或錫（Sn）。根據一些實施例，使用鍍製程（plating process）形成導電柱124，例如電鍍製程（electroplating process）。
如第1A圖所示，根據一些實施例，底部填充層130位於晶片結構122及重佈基板110之間。根據一些實施例，底部填充層130圍繞導電柱124及晶片結構122。根據一些實施例，底部填充層130由絕緣材料形成，例如聚合物材料。
如第1A圖所示，根據一些實施例，模造層140形成在重佈基板110及底部填充層130上方。根據一些實施例，模造層140圍繞晶片結構122、導電柱124及底部填充層130。根據一些實施例，模造層140由絕緣材料形成，例如聚合物材料（例如，環氧樹脂（epoxy））。
如第1A圖所示，根據一些實施例，導電柱108形成在重佈基板110的底表面111上。根據一些實施例，導電柱108由導電材料形成，例如銅（Cu）、鋁（Al）、鎢（W）、鈷（Co）、鎳（Ni）、或錫（Sn）。根據一些實施例，使用鍍製程（plating process）形成導電柱108，例如電鍍製程（electroplating process）。
如第1A圖所示，根據一些實施例，焊料凸塊（solder bump）150形成於導電柱108上。根據一些實施例，焊料凸塊150由錫（Sn）或熔點低於導電柱108的熔點的其他合適的導電材料形成。根據一些實施例，使用鍍製程形成焊料凸塊150，例如電鍍製程。
第1B-1圖是根據一些實施例，繪示出第1B圖的結構的上視圖。第1B圖是根據一些實施例，繪示出所述結構沿第1B-1圖的剖面線1B-1B’的剖面圖。為了簡單起見，第1B-1圖省略了底部填充層170。相似地，第1C-1、1D-1、1D-3、2A、3A、4A、5A-1、5B-1、6A-1、6B-1、7A-1及7B-1圖省略了底部填充層170。
如第1B及1B-1圖所示，根據一些實施例，透過焊料凸塊150接合晶片封裝P至配線基板160。根據一些實施例，配線基板160包括介電層162、導電墊164、配線層166及導電通孔168。
根據一些實施例，導電墊164嵌入於介電層162。根據一些實施例，焊料凸塊150接合至導電墊164。根據一些實施例，配線層166及導電通孔168形成在介電層162中。
根據一些實施例，導電通孔168電性連接不同配線層166且電性連接配線層166及導電墊164。根據一些實施例，為了簡單起見，第1B圖僅繪示出了配線層166中的兩個。
根據一些實施例，介電層162由絕緣材料形成，例如聚合物材料（例如，聚苯并噁唑或聚醯亞胺）、氮化物（例如，氮化矽）、氧化物（例如，氧化矽）、氮氧化矽、或類似材料。根據一些實施例，使用層壓製程（lamination process）（或沉積製程）、微影製程及蝕刻製程形成介電層162。
根據一些實施例，導電墊164由導電材料形成，例如金屬（例如銅、鋁或鎢）或前述的合金。根據一些實施例，配線層166由導電材料形成，例如金屬（例如銅、鋁或鎢）或前述的合金。根據一些實施例，導電通孔168由導電材料形成，例如金屬（例如銅、鋁或鎢）或前述的合金。
在一些實施例中，導電墊164、配線層166及導電通孔168由相同的材料形成。在一些其他實施例中，導電墊164、配線層166及導電通孔168由不同材料形成。
如第1B及1B-1圖所示，根據一些實施例，底部填充層170形成在晶片封裝P及配線基板160之間。根據一些實施例，底部填充層170圍繞導電柱108、焊料凸塊150及晶片封裝P。根據一些實施例，底部填充層170由絕緣材料形成，例如聚合物材料。
在一些實施例中，透過，例如，表面裝置技術（surface mount technology，SMT），將裝置（未繪示）接合到配線基板160。裝置包括被動裝置、其他合適的裝置或前述之組合。被動裝置包括電阻器、電容器、電感器、或其他合適的被動裝置。
如第1B及1B-1圖所示，根據一些實施例，在配線基板160上方形成黏著層180。根據一些實施例，黏著層180具有開口182。根據一些實施例，晶片封裝P在開口182中。根據一些實施例，黏著層180由聚合物材料形成，例如環氧樹脂或矽膠（silicone）。
第1C-1圖是根據一些實施例，繪示出第1C圖的結構的上視圖。第1C圖是根據一些實施例，繪示出所述結構沿第1C-1圖的剖面線1C-1C’的剖面圖。如第1C及1C-1圖所示，根據一些實施例，環形結構210設置在黏著層180上方。根據一些實施例，環形結構210由剛性材料形成，例如金屬（例如，銅或鐵）、前述的合金（例如，不銹鋼）、或其他比配線基板160更硬的合適材料。
參照第1C及1C-1圖，根據一些實施例，在環形結構210上方形成黏著層220，並且在晶片封裝P的頂面P1上方形成擋環230及導熱結構240。根據一些實施例，黏著層220由聚合物及金屬（例如，銀膠（silver paste））的組合或聚合物（例如，環氧樹脂或矽膠）形成。
根據一些實施例，擋環230形成在模造層140上。根據一些實施例，擋環230不連續地圍繞導熱結構240。根據一些實施例，在隨後的蓋接合製程期間，擋環230用於防止導熱結構240被擠出頂面P1。
根據一些實施例，在晶片結構122運作時，擋環230還用於防止導熱結構240被擠出頂面P1。根據一些實施例，由於晶片結構122的熱膨脹係數（CTE）小於散熱蓋（其在隨後的製程中接合到晶片結構122）的熱膨脹係數，所以在晶片結構122運作時（亦即，溫度升高），晶片結構122與散熱蓋之間的空間變得較小。
根據一些實施例，晶片結構122的熱膨脹係數範圍從大約1 ppm/℃到大約5 ppm/℃。根據一些實施例，散熱蓋的熱膨脹係數範圍從約15 ppm/℃至約20 ppm/℃。
如第1C-1圖所示，根據一些實施例，擋環230具有間隙232。根據一些實施例，擋環230被間隙232分成環段234。根據一些實施例，環段234被間隙232分開。根據一些實施例，環段234具有長度L234及寬度W234。
根據一些實施例，長度L234或寬度W234的範圍從約15 μm至約60 μm。根據一些實施例，長度L234大於導熱結構240的長度L240。根據一些實施例，寬度W234比大於導熱結構240的寬度W240。根據一些實施例，長度L240或寬度W240的範圍從約10 μm至約50 μm。
根據一些實施例，晶片結構122具有矩形形狀。根據一些實施例，間隙232的寬度W232與環段234的寬度W234的兩倍的和大於寬度W232與環段234的長度L234的兩倍的和。
根據一些實施例，間隙232的寬度W232與環段234的寬度W234的兩倍的和大於寬度W232的一百倍。根據一些實施例，寬度W232與環段234的長度 L234的兩倍的和大於寬度W232的一百倍。在一些實施例中，間隙232具有相同的寬度W232。在其他實施例中，根據不同的需求，間隙232具有不同的寬度。根據一些實施例，被整個擋環230圍繞的面積範圍從大約700 mm 2到大約1000 mm 2。
根據一些實施例，擋環230的厚度T230大於或等於導熱結構240的厚度T240。因此，根據一些實施例，在隨後的蓋接合製程期間，擋環230能夠防止導熱結構240外流。根據一些實施例，厚度T230的範圍從約50 μm至約300 μm。根據一些實施例，厚度T240的範圍從約50 μm至約300 μm。根據一些實施例，晶片結構122的厚度T122大於厚度T230或T240。
根據一些實施例，導熱結構240形成在晶片結構122及模造層140上。根據一些實施例，導熱結構240延伸跨過晶片結構122的邊緣122E。根據一些實施例，導熱結構240被間隙242分開。根據一些實施例，導熱結構240及擋環230被間隙244分開。
如第1C-1圖所示，在一些實施例中，間隙242的其中一個在擋環230的間隙232的其中兩個之間。根據一些實施例，間隙242的其中一個朝向間隙232的其中兩個延伸。根據一些實施例，間隙232連通間隙242及244。根據一些實施例，擋環230的間隙232鄰近導熱結構240的角落246。
在一些實施例中，兩個鄰近的導熱結構240的其中一個具有側壁241，且這兩個相鄰的導熱結構240的另一個具有側壁243。根據一些實施例，側壁241及243朝向彼此。根據一些實施例，側壁241平行於側壁243。
間隙232的寬度W232小於間隙242的寬度W242，這可以防止導熱結構240從間隙232流出或減少導熱結構240從間隙232流出的量。在一些實施例中，導熱結構240彼此間隔開實質上相同的距離D242。在一些其他實施例中，根據不同的需求，導熱結構240彼此間隔開不同的距離。
根據一些實施例，導熱結構240及擋環230彼此間隔開距離D244。根據一些實施例，擋環230及晶片封裝P的邊緣P2彼此間隔開距離D1。在一些實施例中，距離D244實質上等於距離D1與距離D242的二分之一的和。
根據一些實施例，擋環230及導熱結構240由不同的材料形成。根據一些實施例，擋環230由彈性材料及/或黏合材料形成，例如聚合物材料或聚合物及金屬（例如，銀膠）的組合。根據一些實施例，聚合物材料包括環氧樹脂、聚醯亞胺（PI）、聚乙烯（PE）、橡膠或矽膠。根據一些實施例，使用點膠製程（dispensing process）形成擋環230。
根據一些實施例，導熱結構240包括金屬箔。根據一些實施例，導熱結構240由導熱材料形成，例如銦（In）、錫（Sn）、或具有良好的熱導率（thermal conductivity）及熱擴散的合適材料。根據一些實施例，導熱結構240的材料具有大於或等於50 W/(m·K)的熱導率。根據一些實施例，導熱結構240的材料的熱導率大於擋環230的材料的熱導率。
第1D-1圖是根據一些實施例，繪示出第1D圖的結構的上視圖。第1D圖是根據一些實施例，繪示出晶片封裝結構沿第1D-1圖的剖面線I-I’的剖面圖。第1D-2圖是根據一些實施例，繪示出晶片封裝結構沿第1D-1圖的剖面線II-II’的剖面圖。第1D-3圖是根據一些實施例，繪示出第1D圖的結構的上視圖，差別在於散熱蓋。
如第1D及1D-1圖所示，根據一些實施例，散熱蓋250設置在導熱結構240、擋環230及黏著層220上，且執行退火製程以軟化導熱結構240、擋環230及黏著層220。
根據一些實施例，透過導熱結構240、擋環230及黏著層220接合散熱蓋250到晶片封裝P。在一些實施例中，在退火製程後，擋環230的厚度T230實質上等於導熱結構240的厚度T240。根據一些實施例，在此步驟中，實質上形成晶片封裝結構100P。根據一些實施例，退火製程的溫度範圍從約100℃到約150℃。
如第1D及1D-3圖所示，根據一些實施例，在退火製程期間，導熱結構240朝向彼此延伸，直到導熱結構240彼此接觸，且導熱結構240與擋環230朝向彼此延伸，直到導熱結構240接觸擋環230。
因此，根據一些實施例，在退火製程之後，導熱結構240及擋環230的尺寸（例如，寬度及長度）變得較大。如第1C-1及1D-3圖所示，擋環230的線寬WL230在退火製程後變得較大。
根據一些實施例，導熱結構240共同形成導熱層240’。根據一些實施例，導熱層240’覆蓋晶片結構122的整個頂面122a。
如第1C-1及1D-3圖所示，根據一些實施例，在退火製程期間，導熱結構240及擋環230之間的間隙242及244的尺寸逐漸縮小，直到間隙242及244實質上消失。類似地，根據一些實施例，間隙232的寬度W232在退火製程之後變得較小。
根據一些實施例，原先在間隙242及244中的空氣經由擋環230的間隙232流出。因此，根據一些實施例，間隙232能夠防止在退火的導熱結構240中形成空隙，這提高晶片封裝結構100P的散熱效率。由此，根據一些實施例，增加了晶片封裝結構100P的壽命。
根據一些實施例，在導熱結構240之間存在邊界B240。根據一些實施例，邊界B240也稱為導熱結構240的邊緣。根據一些實施例，邊界B240朝向擋環230的間隙232延伸。
根據一些實施例，散熱蓋250由高導熱率材料形成，例如金屬材料（鋁或銅）、合金材料（例如，不銹鋼）、或碳化鋁-矽（aluminum-silicon carbide，AlSiC）。
第2A圖是根據一些實施例，繪示出晶片封裝結構200P的上視圖。根據一些實施例，為了簡單起見，第2A圖省略了晶片封裝結構200P的散熱蓋。第2B圖是根據一些實施例，繪示出晶片封裝結構200P沿第2A圖的剖面線2B-2B’的剖面圖。第2C圖是根據一些實施例，繪示出晶片封裝結構200P沿第2A圖的剖面線2C-2C’的剖面圖。
根據一些實施例，如第2A、2B及2C圖所示，晶片封裝結構200P類似於第1D圖的晶片封裝結構100P，差別在於導熱結構240的部分247延伸至擋環230的間隙232中且擋環230的部分236從散熱蓋250與晶片封裝P之間的間隙G1突出。
如第2A及2B圖所示，根據一些實施例，部分236具有彎曲的側壁236a。根據一些實施例，如第2A及2C圖所示，部分247具有彎曲的側壁247a。
第3A圖是根據一些實施例，繪示出晶片封裝結構300P的上視圖。根據一些實施例，為了簡單起見，第3A圖中省略了晶片封裝結構300P的散熱蓋。第3B圖是根據一些實施例，繪示出晶片封裝結構300P沿第3A圖的剖面線3B-3B’的剖面圖。
根據一些實施例，如第3A及3B圖所示，晶片封裝結構300P相似於第2A圖的晶片封裝結構200P，差別在於擋環230的間隙232被導熱結構240的部分247填滿。
第4A圖是根據一些實施例，繪示出晶片封裝結構400P的上視圖。為了簡單起見，第4A圖中省略了晶片封裝結構400P的散熱蓋。第4B圖是根據一些實施例，繪示出晶片封裝結構沿第4A圖的剖面線4B-4B’的剖面圖。如第4A及4B圖所示，根據一些實施例，晶片封裝結構400P相似於第3A圖的晶片封裝結構300P，差別在於導熱結構240的部分247延伸出擋環230的間隙232外。
第5A-5B圖是根據一些實施例，繪示出形成晶片封裝結構的製程的各種步驟的剖面圖。第5A-1圖是根據一些實施例，繪示出第5A圖的結構的上視圖。第5A圖是根據一些實施例，繪示所述結構沿第5A-1圖的剖面線5A-5A’的剖面圖。
如第5A及5A-1圖所示，根據一些實施例，在第1B圖的步驟之後，設置環形結構210在黏著層180上，黏著層220形成在環形結構210上，且擋環230及導熱結構240形成在晶片封裝P的頂面P1上。
根據一些實施例，導熱結構240中具有正方形形狀。根據一些實施例，導熱結構240設置在一個陣列中。根據一些實施例，擋環230具有間隙232。根據一些實施例，導熱結構240被間隙242分開。根據一些實施例，間隙242朝向間隙232延伸。
第5B-1圖是根據一些實施例，繪示出第5B圖的結構的上視圖。為了簡單起見，第5B-1圖省略了第5B圖的結構的散熱蓋。第5B圖是根據一些實施例，繪示出所述結構沿第5B-1圖的剖面線5B-5B’的剖面圖。
如第5B及5B-1圖所示，根據一些實施例，散熱蓋250設置在導熱結構240、擋環230及黏著層220上方，並且執行退火製程以軟化導熱結構240、擋環230、及黏著層220。根據一些實施例，透過導熱結構240、擋環230及黏著層220接合散熱蓋250到晶片封裝P。根據一些實施例，在此步驟中，實質上形成晶片封裝結構500P。
第6A-6B圖是根據一些實施例，繪示出形成晶片封裝結構的製程的各種步驟的剖面圖。第6A-1圖是根據一些實施例，繪示出第6A圖的結構的上視圖。第6A圖是根據一些實施例，繪示所述結構沿第6A-1圖的剖面線6A-6A’的剖面圖。
根據一些實施例，如第6A及6A-1圖所示，在第1B圖的步驟之後，設置環形結構210在黏著層180上，黏著層220形成在環形結構210上，擋環230及導熱結構240形成在晶片封裝P的頂面P1上。
根據一些實施例，導熱結構240中具有矩形形狀。根據一些實施例，導熱結構240中設置在一個陣列中。根據一些實施例，擋環230具有間隙232及238。根據一些實施例，導熱結構240被間隙242分開。根據一些實施例，間隙242朝向間隙232延伸。根據一些實施例，間隙238在擋環230的角落部分230c中。
第6B-1圖是根據一些實施例，繪示出第6B圖的結構的上視圖。為了簡單起見，第6B-1圖省略了第6B圖的結構的散熱蓋。第6B圖是根據一些實施例，繪示所述結構沿第6B-1圖的剖面線6B-6B’的剖面圖。
如第6B及6B-1圖所示，根據一些實施例，散熱蓋250設置在導熱結構240、擋環230及黏著層220上方，並且執行退火製程以軟化導熱結構240、擋環230、及黏著層220。
根據一些實施例，透過導熱結構240、擋環230及黏著層220接合散熱蓋250至晶片封裝P。根據一些實施例，在此步驟中，實質上形成晶片封裝結構600P。
第7A-7B圖是根據一些實施例，繪示出形成晶片封裝結構的製程的各種步驟的剖面圖。第7A-1圖是根據一些實施例，繪示出第7A圖的結構的上視圖。第7A圖是根據一些實施例，繪示所述結構沿第7A-1圖的剖面線7A-7A’的剖面圖。
根據一些實施例，如第7A及第7A-1圖所示，在第1B圖的步驟之後，設置環形結構210在黏著層180上方，黏著層220形成在環形結構210上方，且擋環230及導熱結構240A、240B及240C形成在晶片封裝P的頂面P1之上。
根據一些實施例，導熱結構240A的形狀不同於導熱結構240B及240C的形狀。舉例而言，導熱結構240A具有正方形形狀，且導熱結構240B及240C具有矩形形狀。根據一些實施例，導熱結構240A、240B、及240C及具有不同的尺寸。舉例而言，根據一些實施例，導熱結構240A比導熱結構240B或240C寬。
根據一些實施例，擋環230具有間隙232及238。根據一些實施例，導熱結構240A、240B及240C被間隙242分開。根據一些實施例，間隙242朝向間隙232延伸。根據一些實施例，間隙238在擋環230的角落部分230c中。
第7B-1圖是根據一些實施例，繪示出第7B圖的結構的上視圖。為了簡單起見，第7B-1圖省略了第7B圖的結構的散熱蓋。第7B圖是根據一些實施例，繪示所述結構沿第7B-1圖的剖面線7B-7B’的剖面圖。
根據一些實施例，如第7B及第7B-1圖所示，散熱蓋250設置在導熱結構240A、240B及240C、擋環230、及黏著層220上，且進行退火製程以軟化導熱結構240A、240B及240C、擋環230、及黏著層220。
根據一些實施例，透過導熱結構240A、240B及240C、擋環230、及黏著層220接合散熱蓋250到晶片封裝P。根據一些實施例，在此步驟中，實質上形成晶片封裝結構700P。
第8圖是根據一些實施例，繪示出接合至電路基板的晶片封裝結構的剖面圖。如第8圖所示，根據一些實施例，使用退火製程，透過焊料凸塊820接合第1D圖的晶片封裝結構100P到電路基板810。根據一些實施例，晶片封裝結構100P也稱為球格陣列（ball grid array，BGA）封裝結構。
根據一些實施例，由於晶片封裝結構100P的擋環230能夠將大部分導熱結構240限制在散熱蓋250及晶片封裝P之間的間隙G1中，所以晶片封裝結構100P能夠承受退火過程。
根據一些實施例，電路基板810包括介電層812、導電墊814、配線層816及導電通孔818。根據一些實施例，導電墊814嵌入於介電層812中。根據一些實施例，焊料凸塊820連接導電墊814與晶片封裝結構100P的配線基板160的導電墊（未繪示）。
根據一些實施例，配線層816及導電通孔818形成在介電層812中。根據一些實施例，導電通孔818電性連接不同的配線層816以及電性連接配線層816及導電墊814。根據一些實施例，為了簡單起見，第8圖僅繪示出了配線層816中的兩個。
根據一些實施例，介電層812由絕緣材料形成，例如聚合物材料（例如，聚苯并噁唑或聚醯亞胺）、氮化物（例如，氮化矽）、氧化物（例如，氧化矽）、氮氧化矽、或類似材料。
根據一些實施例，導電墊814由導電材料形成，例如金屬（例如銅、鋁或鎢）或前述的合金。根據一些實施例，配線層816由導電材料形成，例如金屬（例如銅、鋁或鎢）或前述的合金。根據一些實施例，導電通孔818由導電材料形成，例如金屬（例如銅、鋁或鎢）或前述的合金。
在一些實施例中，導電墊814、配線層816及導電通孔818由相同的材料形成。在一些其他實施例中，導電墊814、配線層816及導電通孔818由不同材料形成。
第9圖是根據一些實施例，繪示出接合至電路基板的晶片封裝結構的剖面圖。如第9圖所示，根據一些實施例，透過導電銷910接合第1D圖的晶片封裝結構100P到電路基板810。根據一些實施例，晶片封裝結構100P稱為柵格陣列（land grid array ，LGA）封裝結構。
根據一些實施例，導電銷910連接導電墊814與晶片封裝結構100P的配線基板160的導電墊（未繪示）。根據一些實施例，導電銷910由導電材料形成，例如金屬（例如金或銅）或前述的合金。
第10圖是根據一些實施例，繪示出晶片封裝結構1000P的剖面圖。如第10圖所示，根據一些實施例，晶片封裝結構1000P是第1D圖的晶片封裝結構100P的一種。根據一些實施例，晶片結構122是系統積體電路（system on integrated circuit，SOIC）裝置。
根據一些實施例，晶片結構122包括晶片1010及1020、介電層1030、及重佈層1040。根據一些實施例，晶片1010包括基板1012及基板1012下方的互連結構1014。
在一些實施例中，基板1012由元素半導體材料形成，包括單晶結構、多晶結構或非晶結構的矽或鍺。在一些其他實施例中，基板1012由化合物半導體形成，例如碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、合金半導體，例如矽鍺（SiGe）或磷砷化鎵（GaAsP）、或前述之組合。基板1012還可包括多層半導體、絕緣體上覆半導體（SOI）（例如絕緣體上覆矽或絕緣體上覆鍺）或前述之組合。
在一些實施例中，基板1012是包括各種裝置元件的裝置晶圓。在一些實施例中，所述各種裝置元件形成於基板1012之中及/或之上。為了簡明及清楚的目的，所述裝置元件未在圖式中繪示。所述各種裝置元件的示例包括：主動裝置、被動裝置、其他合適的元件或前述之組合。主動裝置可以包括形成於基板1012表面的電晶體或二極體（未繪示）。被動裝置包括：電阻器、電容器、或其他合適的被動裝置。
舉例而言，電晶體可以是金屬氧化物半導體場效電晶體 （MOSFET）、互補金屬氧化物半導體 （CMOS） 電晶體、雙極性接面電晶體 （bipolar junction transistor，BJT）、高壓電晶體、高頻電晶體、p型通道及/或n型通道場效電晶體（PFET/NFET）等等。執行各種製程，例如前段（front-end-of-line，FEOL）半導體製造製程，以形成各種裝置元件。前段半導體製造製程可包括沉積、蝕刻、佈植、微影、退火、平坦化、一或多種其他適合的製程、或前述之組合。
在一些實施例中，隔離部件（未繪示）形成在基板1012中。隔離部件用於圍繞主動區並且電性隔離在主動區中的基板1012中及/或上方形成的各種裝置元件。在一些實施例中，隔離部件包括淺溝槽隔離（STI）部件、矽局部氧化（LOCOS）部件、其他合適的隔離部件或前述之組合。
根據一些實施例，互連結構1014包括介電層1014a、配線層（未繪示）、導電通孔（未繪示）及導電墊1014b。根據一些實施例，配線層、導電通孔及導電墊1014b在介電層1014a中。根據一些實施例，導電通孔電性連接配線層、電性連接配線層與導電墊1014b、以及電性連接配線層與裝置元件。
根據一些實施例，介電層1014a由介電材料形成，例如氧化物材料（例如，氧化矽）。根據一些實施例，配線層、導電通孔、及導電墊1014b由導電材料形成，例如金屬（例如，銅、鋁、或鎢）或前述之合金。
根據一些實施例，每個晶片1020包括基板1022、互連結構1024及基板通孔1026。根據一些實施例，互連結構1024在基板1022上方。根據一些實施例，基板通孔1026穿過基板1022。
在一些實施例中，基板1022由元素半導體材料形成，包括單晶結構、多晶結構或非晶結構的矽或鍺。在一些其他實施例中，基板1022由化合物半導體形成，例如碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、合金半導體，例如矽鍺（SiGe）或磷砷化鎵（GaAsP）、或前述之組合。基板1022還可包括多層半導體、絕緣體上覆半導體（SOI）（例如絕緣體上覆矽或絕緣體上覆鍺）或前述之組合。
在一些實施例中，基板1022是包括各種裝置元件的裝置晶圓。在一些實施例中，所述各種裝置元件形成於基板1022之中及/或之上。為了簡明及清楚的目的，所述裝置元件未在圖式中繪示。所述各種裝置元件的示例包括：主動裝置、被動裝置、其他合適的元件或前述之組合。主動裝置可以包括形成於基板1022表面的電晶體或二極體（未繪示）。被動裝置包括：電阻器、電容器、或其他合適的被動裝置。
舉例而言，電晶體可以是金屬氧化物半導體場效電晶體 （MOSFET）、互補金屬氧化物半導體 （CMOS） 電晶體、雙極性接面電晶體 （BJT）、高壓電晶體、高頻電晶體、p型通道及/或n型通道場效電晶體（PFET/NFET）等等。執行各種製程，例如前段（FEOL）半導體製造製程，以形成各種裝置元件。前段半導體製造製程可包括沉積、蝕刻、佈植、微影、退火、平坦化、一或多種其他適合的製程、或前述之組合。
在一些實施例中，隔離部件（未繪示）形成在基板1022中。隔離部件用於圍繞主動區並且電性隔離在主動區中的基板1022中及/或上方形成的各種裝置元件。在一些實施例中，隔離部件包括淺溝槽隔離（STI）部件、矽局部氧化（LOCOS）部件、其他合適的隔離部件或前述之組合。
根據一些實施例，互連結構1024包括介電層1024a、配線層（未繪示）、導電通孔（未繪示）及導電墊1024b。根據一些實施例，配線層、導電通孔及導電墊1024b在介電層1024a中。根據一些實施例，導電通孔電性連接配線層、電性連接配線層與導電墊1024b、以及電性連接配線層與基板通孔1026。
根據一些實施例，介電層1024a由介電材料形成，例如氧化物材料（例如，氧化矽）。根據一些實施例，配線層、導電通孔、導電墊1024b、及基板通孔1026由導電材料形成，例如金屬（例如，銅、鋁或鎢）或前述的合金。
根據一些實施例，晶片1020的導電墊1024b接合晶片1010的導電墊1014b。根據一些實施例，導電墊1024b直接接觸導電墊1014b。
根據一些實施例，介電層1030圍繞晶片1020。根據一些實施例，介電層1030由絕緣材料形成，例如聚合物材料（例如，聚苯并噁唑或聚醯亞胺）、氮化物（例如，氮化矽）、氧化物（例如，氧化矽）、氮氧化矽、或類似材料。
根據一些實施例，重佈層1040在介電層1030及晶片1020下方。根據一些實施例，重佈層1040包括介電層1040a、配線層（未繪示）、導電通孔（未繪示）、及導電墊（未繪示）。根據一些實施例，配線層、導電通孔及導電墊在介電層1040a中。
根據一些實施例，導電通孔電性連接配線層、電性連接配線層與導電墊、以及電性連接配線層與裝置元件。根據一些實施例，導電墊電性連接至其下方的導電柱124。
根據一些實施例，介電層1040a是由介電材料形成，例如氧化物材料（例如，氧化矽）。根據一些實施例，配線層、導電通孔及導電墊由導電材料形成，例如金屬（例如，銅、鋁或鎢）或前述之合金。
形成晶片封裝結構200P、300P、400P、500P、600P、700P、及1000P的製程及材料可以相似於或相同於上述形成晶片封裝結構100P的製程及材料。
根據一些實施例，提供晶片封裝結構及其形成方法。所述方法（用於形成晶片封裝結構）形成導熱結構及擋環於晶片封裝上，然後透過導熱結構及擋環接合散熱蓋至晶片封裝。在接合散熱蓋至晶片封裝之前，導熱結構被第一間隙分開，第一間隙朝擋環的第二間隙延伸。在接合製程期間，導熱結構朝向彼此延伸，直到導熱結構彼此接觸，且第一間隙中的空氣通過擋環的第二間隙流出，這防止在導熱結構形成中空隙。擋環能夠將導熱結構限制在散熱蓋及晶片封裝之間的間隙中。因此，提升晶片封裝結構的散熱效率。由此，增加晶片封裝結構的壽命。
根據一些實施例，提供晶片封裝結構的形成方法。所述方法包括設置晶片封裝於配線基板上。所述方法包括形成第一導熱結構及第二導熱結構於晶片封裝上。第一導熱結構及第二導熱結構被第一間隙分開。所述方法包括透過第一導熱結構及第二導熱結構接合散熱蓋至晶片封裝。在接合散熱蓋至晶片封裝期間，第一導熱結構及第二導熱結構朝向彼此延伸，直到第一導熱結構接觸第二導熱結構。
在一些實施例中，接合散熱蓋至晶片封裝包括： 設置散熱蓋於第一導熱結構及第二導熱結構上；以及執行退火製程以軟化第一導熱結構及第二導熱結構。在一些實施例中，第一導熱結構的第一側壁及第二導熱結構的第二側壁朝向彼此，且第一側壁平行於第二側壁。一些實施例中，所述方法更包括： 在接合散熱蓋至晶片封裝之前，形成擋環於晶片封裝上，其中擋環圍繞第一導熱結構及第二導熱結構。在一些實施例中，擋環的第一材料不同於第一導熱結構的第二材料及第二導熱結構的第三材料。在一些實施例中，擋環具有第二間隙。在一些實施例中，第一導熱結構及第二導熱結構之間的第一間隙朝向第二間隙延伸。在一些實施例中，擋環還具有第三間隙，且第一間隙位於第二間隙及第三間隙之間。在一些實施例中，在接合散熱蓋至晶片封裝之前，第一導熱結構及第二導熱結構之間的第一間隙比擋環的第二間隙寬。在一些實施例中，在接合散熱蓋至晶片封裝之後，第一導熱結構延伸至擋環的第二間隙中。在一些實施例中，在接合散熱蓋至晶片封裝之後，第一導熱結構延伸出擋環的第二間隙。在一些實施例中，所述方法更包括：形成第三導熱結構於晶片封裝上，其中第二導熱結構位於第一導熱結構及第三導熱結構之間，在接合散熱蓋至晶片封裝之前，第一導熱結構及第二導熱結構之間的第一距離實質上等於第二導熱結構及第三導熱結構之間的第二距離。
根據一些實施例，提供晶片封裝結構的形成方法。所述方法包括設置晶片封裝於配線基板上。所述方法包括形成導熱結構及擋環於晶片封裝上。擋環圍繞導熱結構，擋環及導熱結構被第一間隙分開，且擋環具有連通第一間隙的第二間隙。所述方法包括透過導熱結構及擋環接合散熱蓋至晶片封裝。在接合散熱蓋至晶片封裝期間，導熱結構及擋環朝向彼此延伸，直到導熱結構接觸擋環。
在一些實施例中，擋環的第二間隙鄰近導熱結構的角落。在一些實施例中，在接合散熱蓋至晶片封裝之前，擋環的第一厚度大於或等於導熱結構的第二厚度。
根據一些實施例，提供晶片封裝結構。晶片封裝結構包括配線基板。晶片封裝結構包括晶片封裝，位於配線基板上。晶片封裝結構包括第一導熱結構，位於晶片封裝上。晶片封裝結構包括擋環，位於晶片封裝上且圍繞第一導熱結構。擋環具有間隙。晶片封裝結構包括散熱蓋，位於第一導熱結構及擋環上。
在一些實施例中，第一導熱結構的邊緣朝向間隙延伸。在一些實施例中，晶片封裝結構更包括：第二導熱結構，位於晶片封裝上，其中第二導熱結構直接接觸第一導熱結構且被擋環圍繞。在一些實施例中，第一導熱結構的一部分在間隙中。在一些實施例中，晶片封裝包括：基板；晶片結構，位於基板上，其中第一導熱結構位於晶片結構上；以及模造層，位於基板上且圍繞晶片結構，其中擋環位於模造層上。
以上概述數個實施例之特徵，以便在本發明所屬技術領域中具有通常知識者可更易理解本發明實施例的觀點。在本發明所屬技術領域中具有通常知識者應理解，他們能以本發明實施例為基礎，設計或修改其他製程及結構，以達到與在此介紹的實施例相同之目的及/或優勢。在本發明所屬技術領域中具有通常知識者也應理解到，此類等效的製程及結構並無悖離本發明的精神與範圍，且他們能在不違背本發明之精神及範圍之下，做各式各樣的改變、取代及替換。
100P:晶片封裝結構 108:導電柱 110:重佈基板 112:配線層 114:導電通孔 116:介電層 122:晶片結構 122a:頂面 122E:邊緣 124:導電柱 130:底部填充層 140:模造層 150:焊料凸塊 160:配線基板 162:介電層 164:導電墊 166:配線層 168:導電通孔 170:底部填充層 180:黏著層 182:開口 1B-1B’,1C-1C’:剖面線 200P:晶片封裝結構 210:環形結構 220:黏著層 230:擋環 230c:部分 232:間隙 234:環段 236:部分 236a:側壁 238:間隙 240:導熱結構 240A,240B,240C:導熱結構 240’:導熱層 241:側壁 242:間隙 243:側壁 244:間隙 246:角落 247:部分 247a:側壁 250:散熱蓋 2B-2B’,2C-2C’:剖面線 300P,400P,500P,600P,700P:晶片封裝結構 3B-3B’,4B-4B’,5A-5A’,5B-5B’:剖面線 6A-6A’,6B-6B’,7A-7A’,7B-7B’:剖面線 810:電路基板 812:介電層 814:導電墊 816:配線層 818:導電通孔 820:焊料凸塊 910:導電銷 1000P:晶片封裝結構 1010:晶片 1012:基板 1014:互連結構 1014a:介電層 1014b:導電墊 1020:晶片 1022:基板 1024:互連結構 1024a:介電層 1024b:導電墊 1026:基板通孔 1030:介電層 1040:重佈層 1040a:介電層 B240:邊界 D1:距離 D242,D244:距離 G1:間隙 I-I’,II-II’:剖面線 L234:長度 P:晶片封裝 P1:頂面 P2:邊緣 T122:厚度 T230:厚度 T240:厚度 W232:寬度 W234:寬度 WL230:線寬
由以下的詳細敘述配合所附圖式，可最好地理解本發明實施例。應注意的是，依據在業界的標準做法，各種特徵並未按照比例繪製。事實上，可任意地放大或縮小各種元件的尺寸，以清楚地表現出本發明實施例之特徵。 第1A-1D圖是根據一些實施例，繪示出形成晶片封裝結構的製程的各種步驟的剖面圖。 第1B-1圖是根據一些實施例，繪示出第1B圖的結構的上視圖。 第1C-1圖是根據一些實施例，繪示出第1C圖的結構的上視圖。 第1D-1圖是根據一些實施例，繪示出第1D圖的結構的上視圖。 第1D-2圖是根據一些實施例，繪示出晶片封裝結構沿第1D-1圖的剖面線II-II’的剖面圖。 第1D-3圖是根據一些實施例，繪示出第1D圖的結構的上視圖，差別在於散熱蓋。 第2A圖是根據一些實施例，繪示出晶片封裝結構的上視圖。 第2B圖是根據一些實施例，繪示出晶片封裝結構沿第2A圖的剖面線2B-2B’的剖面圖。 第2C圖是根據一些實施例，繪示出晶片封裝結構沿第2A圖的剖面線2C-2C’的剖面圖。 第3A圖是根據一些實施例，繪示出晶片封裝結構的上視圖。 第3B圖是根據一些實施例，繪示出晶片封裝結構沿第3A圖的剖面線3B-3B’的剖面圖。 第4A圖是根據一些實施例，繪示出晶片封裝結構的上視圖。 第4B圖是根據一些實施例，繪示出晶片封裝結構沿第4A圖的剖面線4B-4B’的剖面圖。 第5A-5B圖是根據一些實施例，繪示出形成晶片封裝結構的製程的各種步驟的剖面圖。 第5A-1圖是根據一些實施例，繪示出第5A圖的結構的上視圖。 第5B-1圖是根據一些實施例，繪示出第5B圖的結構的上視圖。 第6A-6B圖是根據一些實施例，繪示出形成晶片封裝結構的製程的各種步驟的剖面圖。 第6A-1圖是根據一些實施例，繪示出第6A圖的結構的上視圖。 第6B-1圖是根據一些實施例，繪示出第6B圖的結構的上視圖。 第7A-7B圖是根據一些實施例，繪示出形成晶片封裝結構的製程的各種步驟的剖面圖。 第7A-1圖是根據一些實施例，繪示出第7A圖的結構的上視圖。 第7B-1圖是根據一些實施例，繪示出第7B圖的結構的上視圖。 第8圖是根據一些實施例，繪示出接合至電路基板的晶片封裝結構的剖面圖。 第9圖是根據一些實施例，繪示出接合至電路基板的晶片封裝結構的剖面圖。 第10圖是根據一些實施例，繪示出晶片封裝結構1000P的剖面圖。
100P:晶片封裝結構
122:晶片結構
220:黏著層
230:擋環
232:間隙
234:環段
240:導熱結構
240’:導熱層
250:散熱蓋
B240:邊界
I-I’,II-II’:剖面線
P:晶片封裝

Claims (9)

  1. 一種晶片封裝結構的形成方法，包括：設置一晶片封裝於一配線基板上；形成一第一導熱結構及一第二導熱結構於該晶片封裝上，其中該第一導熱結構及該第二導熱結構被一第一間隙分開；透過該第一導熱結構及該第二導熱結構接合一散熱蓋至該晶片封裝，其中在接合該散熱蓋至該晶片封裝期間，該第一導熱結構及該第二導熱結構朝向彼此延伸，直到該第一導熱結構接觸該第二導熱結構；以及在接合該散熱蓋至該晶片封裝之前，形成一擋環(ring dam)於該晶片封裝上，其中該擋環圍繞該第一導熱結構及該第二導熱結構，其中該擋環具有一第二間隙。
  2. 如請求項1之晶片封裝結構的形成方法，其中接合該散熱蓋至該晶片封裝包括：設置該散熱蓋於該第一導熱結構及該第二導熱結構上；以及執行一退火製程以軟化該第一導熱結構及該第二導熱結構。
  3. 如請求項1之晶片封裝結構的形成方法，其中在接合該散熱蓋至該晶片封裝之後，該第一導熱結構延伸至該擋環的該第二間隙中或延伸出該擋環的該第二間隙。
  4. 如請求項1或2之晶片封裝結構的形成方法，更包括：形成一第三導熱結構於該晶片封裝上，其中該第二導熱結構位於該第一導熱結構及該第三導熱結構之間，在接合該散熱蓋至該晶片封裝之前，該第一導熱結構及該第二導熱結構之間的一第一距離實質上等於該第二導熱結構及該第三導熱結構之間的一第二距離。
  5. 一種晶片封裝結構的形成方法，包括： 設置一晶片封裝於一配線基板上；形成一導熱結構及一擋環於該晶片封裝上，其中該擋環圍繞該導熱結構，該擋環及該導熱結構被一第一間隙分開，且該擋環具有連通該第一間隙的一第二間隙；以及透過該導熱結構及該擋環接合一散熱蓋至該晶片封裝，其中在接合該散熱蓋至該晶片封裝期間，該導熱結構及該擋環朝向彼此延伸，直到該導熱結構接觸該擋環。
  6. 如請求項5之晶片封裝結構的形成方法，其中該擋環的該第二間隙鄰近該導熱結構的一角落。
  7. 一種晶片封裝結構，包括：一配線基板；一晶片封裝，位於該配線基板上；一第一導熱結構，位於該晶片封裝上；一擋環，位於該晶片封裝上且圍繞該第一導熱結構，其中該擋環具有一間隙；以及一散熱蓋，位於該第一導熱結構及該擋環上。
  8. 如請求項7之晶片封裝結構，更包括：一第二導熱結構，位於該晶片封裝上，其中該第二導熱結構直接接觸該第一導熱結構且被該擋環圍繞。
  9. 如請求項7或8之晶片封裝結構，其中該晶片封裝包括：一基板；一晶片結構，位於該基板上，其中該第一導熱結構位於該晶片結構上；以及一模造層(molding layer)，位於該基板上且圍繞該晶片結構，其中該擋環位於模造層上。
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