TWI771977B - Method for cleaning deposition chamber - Google Patents

Abstract

A method for cleaning a deposition chamber includes transferring a substrate over a substrate supporter in a semiconductor processing chamber; performing a deposition process to deposit a material layer over the substrate; transferring the substrate out of the semiconductor processing chamber; performing a first cleaning process, in which performing the first cleaning process includes supplying a first gas into the semiconductor processing chamber from a first pipe in the substrate supporter, and turning on an RF power to generate a plasma of the first gas to clean a surface of the substrate supporter; and performing a second cleaning process, in which performing the second cleaning process includes supplying a second gas into the semiconductor processing chamber from a second pipe in a sidewall of the semiconductor processing chamber, and turning on the RF power to generate a plasma of the second gas to clean the surface of the substrate supporter.

Description

Cleaning methods for deposition chambers

The present disclosure is related to a method of cleaning a deposition chamber.

Physical vapor deposition (PVD) or sputtering is a process used to manufacture electronic components. PVD is a plasma process performed in a vacuum chamber in which a negatively biased target is exposed to a plasma of an inert gas having relatively heavy atoms (eg, argon (Ar)) or a gas mixture comprising such an inert gas . The bombardment of the target by ions of the noble gas results in the ejection of atoms of the target material. The ejected atoms are accumulated as a deposited film on a substrate, which is placed on a substrate support base provided in the chamber.

An embodiment of the present disclosure is a method of cleaning a deposition chamber, including moving a substrate onto a substrate support of a semiconductor processing chamber; performing a deposition process to deposit a material layer on the substrate; moving the substrate out of the semiconductor processing chamber; performing a first cleaning process, wherein performing the first cleaning process includes providing a first gas into the semiconductor processing chamber through a first conduit in the substrate support, and turning on a radio frequency source to generate a plasma of the first gas to clean the surface of the substrate support and performing a second cleaning process, wherein performing the second cleaning process includes providing a second gas into the semiconductor processing chamber through a second conduit disposed on a sidewall of the semiconductor processing chamber, and turning on a radio frequency source to generate a plasma of the second gas to clean the surface of the substrate support.

An embodiment of the present disclosure is a method for cleaning a deposition chamber, including moving a substrate onto a substrate support of a semiconductor processing chamber; performing a deposition process to deposit a material layer on the substrate; and moving the substrate out of the semiconductor processing chamber a chamber; performing a first cleaning process, wherein performing the first cleaning process includes generating a first plasma within the semiconductor processing chamber to clean the surface of the substrate support, the first plasma cleaning at a central portion of the surface of the substrate support at a rate greater than a cleaning rate at a peripheral portion of the surface; and performing a second cleaning process, wherein performing the second cleaning process includes generating a second plasma within the semiconductor processing chamber to clean the surface of the substrate support, the second plasma at the surface of the substrate support The cleaning rate of the peripheral portion of the surface is greater than the cleaning rate of the central portion of the surface.

An embodiment of the present disclosure is a method of cleaning a deposition chamber, including performing a deposition process in a semiconductor processing chamber to deposit a material layer on a substrate above a substrate support; confirming a bias voltage between the substrate and the substrate support Whether it is normal; if the bias voltage is abnormal, perform a first cleaning process, wherein performing the first cleaning process includes generating a first plasma in the semiconductor processing chamber to clean the surface of the substrate support, and the first plasma is in the substrate support. a central portion of the surface has a greater concentration than a peripheral portion of the surface; and performing a second cleaning process, wherein performing the second cleaning process includes generating a second plasma within the semiconductor processing chamber to clean the surface of the substrate support, the first The concentration of the second plasma is greater in the peripheral portion of the surface of the substrate support than in the central portion of the surface.

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the description that follows, the formation of a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include additional features that may be formed on the first feature. Embodiments in which the first and second features may not be in direct contact with the second feature. Furthermore, in various instances, the present disclosure may repeat reference numbers and/or letters. This repetition is for the purpose of simplicity and clarity, and does not in itself prescribe the relationship between the various embodiments and/or configurations discussed.

In addition, for ease of description, such as "beneath", "below", "lower", "above" and "upper" ” and similar spatially relative terms may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. In addition to the orientation depicted in the figures, these spatially relative terms are intended to encompass different orientations of the elements in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and likewise the spatially relative descriptors used herein interpreted accordingly.

Embodiments of the present disclosure generally provide a processing chamber. In some embodiments, an embodiment of the present disclosure is a substrate processing method for performing a physical vapor deposition (PVD) process. The processing chamber is a vacuum chamber that includes an electrostatic chuck (E-chuck) to support and hold the substrates on which atoms ejected by bombardment of the target are deposited during PVD processing. The electrostatic chuck includes a ceramic ball having one or more electrodes therein. A clamping voltage is applied to the electrodes to electrostatically hold the substrate to the electrostatic chuck.

The cover ring, deposition ring, and ground shield are disposed in the vacuum chamber to define the processing area relative to the substrate within the vacuum chamber. Ground shields are interleaved with cover rings to confine plasma. The confinement of the plasma and ejected atoms to the processing area limits the deposition of the target material on other components in the chamber and facilitates more efficient use of the target material because a relatively high percentage of the ejected atoms are deposited on the substrate.

An electrostatic chuck (ESC) supports the deposition ring and is coupled to the bottom of the vacuum chamber by a lift mechanism for moving the electrostatic chuck (ESC) and deposition ring between upper and lower positions. During operation, the cover ring is also raised and lowered. When raised, the cover ring separates vertically from the ground shield. When lowered, the portion of the cover ring is received within the portion of the ground shield. When the electrostatic chuck is in the raised position, the cover ring and ground shield are vertically separated from each other. During processing operations, deposition material from the target is also deposited on the deposition ring.

FIG. 1 shows a semiconductor processing chamber 100 including a one-piece grounded shield 160 and a cover ring 170 . Ground shield 160 and cover ring 170 include a processing kit for processing substrates 105 disposed in processing zone 110 or plasma zone, which also includes deposition ring 180 supported on base assembly 120 . In some embodiments, semiconductor processing chamber 100 includes a sputtering chamber, also known as a physical vapor deposition or PVD chamber, for depositing single-component or multi-component materials from target 132 on substrate 105 . The semiconductor processing chamber 100 can also be used to deposit aluminum, copper, nickel, platinum, hafnium, silver, chromium, gold, molybdenum, silicon, ruthenium, tantalum, tantalum nitride, tantalum carbide, titanium nitride, tungsten, tungsten nitride, Lanthanum, alumina, lanthanum oxide, nickel-platinum alloys, and titanium, and/or combinations thereof. It is contemplated that other processing chambers may also be suitable to benefit from the disclosed embodiments. The deposition ring 180 has an annular shape surrounding the substrate support 126 and will be discussed in greater detail later. In some embodiments, the deposition ring 180 may be made of a ceramic or metallic material, such as quartz, alumina, stainless steel, titanium, or other suitable materials. The cover ring 170 is made of a material that is resistant to erosion by sputtering plasma, such as a metallic material or a ceramic material.

The semiconductor processing chamber 100 includes a chamber body 101 having sidewalls 104 enclosing a processing area 110 , a bottom wall 106 and an upper processing assembly 108 . Processing area 110 is defined as the area above substrate support 126 during processing (eg, between target 132 and substrate support 126 when in processing position). The chamber body 101 is fabricated by machining and welding stainless steel plates or by machining a single block of aluminum. In one embodiment, the side wall 104 comprises or is plated with aluminum, and the bottom wall 106 comprises or is plated with stainless steel. Sidewalls 104 typically contain slit valves to provide access to substrates 105 from semiconductor processing chamber 100 . Components in the upper processing assembly 108 of the semiconductor processing chamber 100 in cooperation with the ground shield 160 , the base assembly 120 and the cover ring 170 confine the plasma formed in the processing area 110 to the area above the substrate 105 .

The base assembly 120 is supported from the bottom wall 106 of the semiconductor processing chamber 100 . Base assembly 120 supports deposition ring 180 along with substrate 105 during processing. The base assembly 120 is coupled to the bottom wall 106 of the semiconductor processing chamber 100 by a lift mechanism 122 for the upper processing position of the target on the substrate 105 during deposition and the substrate 105 is transferred to the base The base assembly 120 is raised and lowered between the lower transfer positions on the assembly 120 . Additionally, at the lower transfer position, lift pins 123 move past base assembly 120 to separate substrate 105 from base assembly 120 for ease by a substrate transfer mechanism disposed outside semiconductor processing chamber 100 (eg, single-chip robot) to exchange the substrate 105. A bellows 124 is typically disposed between the base assembly 120 and the bottom wall 106 to isolate the processing region 110 of the chamber body 101 from the interior of the base assembly 120 and the exterior of the chamber.

The base assembly 120 includes a substrate support 126 sealingly coupled to the platform housing 128 . The platform housing 128 is typically made of a metallic material, such as stainless steel or aluminum. A cooling plate is typically disposed within the platform housing 128 to thermally condition the substrate support 126 . The substrate support 126 is made of aluminum or ceramic. The substrate support 126 has a substrate receiving surface 127 that receives and supports the substrate 105 during processing, the substrate receiving surface 127 being generally parallel to the sputtering surface 133 of the target 132 . The substrate support 126 also has a peripheral edge 129 that terminates before the protruding edge of the substrate 105 .

In some embodiments, the substrate support 126 is an electrostatic chuck, a ceramic body, a heater, or a combination thereof. In one embodiment, the substrate support 126 is an electrostatic chuck comprising a dielectric body having electrodes 126A or conductive layers embedded therein. The dielectric body is made of a high thermal conductivity dielectric material such as pyrolytic boron nitride, aluminum nitride, silicon nitride, aluminum oxide, or equivalent. In some embodiments, the electrodes 126A are configured such that when a DC voltage is applied to the electrodes 126A by the electrostatic chuck power supply 143, the substrates 105 disposed on the substrate receiving surface 127 will be electrostatically clamped to such electrodes 126A to Heat transfer between the substrate 105 and the substrate support 126 is improved. In other embodiments, impedance controller 141 is also coupled to electrode (conductive layer) 126A so that a voltage on the substrate can be maintained during processing to affect plasmonic interactions with the surface of substrate 105 .

In some embodiments, the substrate support 126 has a conduit 137 therein, one end of the conduit 137 is exposed through the surface of the substrate support 126 , and the other end of the conduit 137 is connected to the gas source 138 . In some embodiments, the conduit 137 is provided with a valve V1 configured to restrict the flow of gas from the gas source 138 through the conduit 137 into the processing region 110 . For example, when valve V1 is in the "open" state, gas is allowed to flow from gas source 138 through conduit 137 into processing region 110 . If the valve V1 is in the "closed" state, the gas will be restricted by the valve V1 and cannot enter the processing area 110 .

In some embodiments, the platform housing 128 includes a material having thermal properties that are appropriately matched to the thermal properties of the overlying substrate support 126 . For example, the platform housing 128 includes a composite of ceramic and metal (eg, alumino-silicon carbide), which provides improved strength and durability compared to ceramic, and also has improved heat transfer properties. The composite material has a coefficient of thermal expansion that matches the material of the substrate support 126 to reduce thermal expansion mismatch. In some embodiments, the composite material comprises a ceramic having pores infiltrated by a metal that at least partially fills the pores to form the composite material. Ceramics include, for example, at least one of silicon carbide, aluminum nitride, aluminum oxide, or cordierite. The ceramic contains from about 20 vol% to about 80 vol% pore volume of the total volume, with the remaining volume belonging to the infiltrated metal. The infiltrated metal contains silicon-added aluminum, and also contains copper. In some embodiments, the composite includes different compositions of ceramic and metal, such as metal with dispersed ceramic particles, or the platform housing 128 may be made of only metal, such as stainless steel or aluminum. A cooling plate is disposed within the platform housing 128 to thermally condition the substrate support 126 .

The semiconductor processing chamber 100 is controlled by a system controller 190, which facilitates the control and automation of the semiconductor processing chamber 100, and typically includes a central processing unit (CPU), memory, and support circuits (or I/O). A CPU may be one of any form of computer processor used in an industrial setting for controlling various system functions, substrate movement, chamber processing, and supporting hardware (eg, sensors, robots, motors, etc.) and Monitor the process (eg, substrate support temperature, power supply variables, chamber process time, I/O signals, etc.). The memory is connected to the CPU and can be one or more of readily available memory, such as random access memory (RAM), read only memory (ROM), floppy disk, hard disk, or any other A form of digital storage, local or remote. Software instructions and data can be encoded and stored in memory for instructing the CPU. Support circuitry is also connected to the CPU for supporting the processor in a conventional manner. Supporting circuits include cache memory, power supplies, clock circuits, input/output circuitry, subsystems, and the like. Programs (or computer instructions) readable by the system controller 190 determine which tasks are performed on the substrate. This program is software readable by the system controller 190 and contains code to perform tasks related to the monitoring, execution, and control of motion, and various process recipe tasks and recipe steps to be performed in the semiconductor processing chamber 100 . For example, the system controller 190 includes code including: a set of substrate positioning instructions to operate the base assembly 120 and a set of gas flow control instructions to operate the gas flow control valve to set the splash to the semiconductor processing chamber 100 The flow rate of the injected gas; the gas pressure control command set to operate the throttle valve or gate valve to maintain the pressure in the semiconductor processing chamber 100; the temperature control command set to control the temperature control system in the base assembly 120 or the side wall 104 The temperature of the substrate or the sidewall 104 is respectively set; and the process monitoring command set is used to monitor the process in the semiconductor processing chamber 100 .

The upper processing assembly 108 includes a radio frequency (RF) source 181 , a direct current (DC) source 182 , an adapter 102 , a motor 193 and a cover assembly 130 . The cover assembly 130 includes a target 132 , a magnetron system 189 and a cover shell 191 . As shown in FIG. 1 , the upper processing assembly 108 is supported by the side walls 104 when in the closed position. A ceramic target spacer 136 is disposed between the target 132 and the adapter 102 of the cap assembly 130 to limit vacuum leakage therebetween. Adapter 102 is sealingly coupled to sidewall 104 and is used to facilitate removal of upper processing assembly 108 .

The target 132 is positioned adjacent the adapter and exposed to the processing region 110 of the semiconductor processing chamber 100 . Target 132 provides the material deposited on the substrate during the PVD process.

During processing, target 132 is biased with RF and/or DC power relative to ground (eg, chamber body 101 ) by power source 140 disposed in RF source 181 and/or DC source 182 . In one embodiment, RF source 181 includes RF power source 181A and RF matcher 181B, which are used to efficiently deliver RF energy to target 132 .

During processing, a gas (eg, argon) is supplied to processing region 110 from gas source 142 via conduit 144 . In some embodiments, gas source 142 includes a non-reactive gas, such as argon or xenon, which can energetically impinge on target 132 and sputter material from target 132 . The gas source 142 also includes a reactive gas (eg, one or more of an oxygen-containing gas, a nitrogen-containing gas, a methane-containing gas) that reacts with the sputtered material to form a layer on the substrate. Waste process gases and by-products are exhausted from the semiconductor processing chamber 100 via exhaust ports 146 that receive the waste process gases and direct the waste process gases to exhaust conduits 148 that have adjustable The gate valve 147 is positioned to control the pressure in the processing region 110 in the semiconductor processing chamber 100 . The exhaust conduit 148 is connected to one or more exhaust pumps 149 . Typically, the pressure of the sputtering gas in the semiconductor processing chamber 100 is set to a sub-atmospheric pressure level (eg, a vacuum environment), eg, a pressure of about 0.6 mTorr to about 400 mTorr. Plasma is formed from the gas between the substrate 105 and the target 132 . The ions within the plasma are accelerated towards the target 132 and cause material to fall off the target 132 . The exfoliated target material is deposited on the substrate 105 . In some embodiments, the conduit 144 is provided with a valve V2 configured to restrict the flow of gas from the gas source 142 through the conduit 144 into the processing region 110 . For example, when valve V2 is in the "open" state, gas is allowed to flow from gas source 142 through conduit 144 into processing region 110 . If the valve V2 is in the "closed" state, the gas will be restricted by the valve V2 and cannot enter the processing area 110 .

Cover 191 includes conductive walls 185 , center feed 184 and shield 186 . In this configuration, conductive walls 185 , center feed 184 , target 132 and a portion of motor 193 enclose and form backside region 134 . The backside region 134 is a sealed area disposed on the backside of the target 132 and is typically filled with a flowing liquid during processing to remove heat generated at the target 132 during processing. In one embodiment, conductive wall 185 and center feed 184 are used to support motor 193 and magnetron system 189 so that motor 193 can rotate magnetron system 189 during processing. In some embodiments, the motor 193 is electrically isolated from RF or DC power delivered from the power source. Shield 186 contains one or more dielectric materials positioned to enclose and limit RF energy delivered to target 132 so as not to interfere with and affect other processing chambers disposed in cluster tool 103 .

A ground shield 160 is supported by the chamber body 101 and surrounds the sputter surface 133 of the sputter target 132 facing the substrate support 126 . The ground shield 160 also surrounds the peripheral edge 129 of the substrate support 126 . Ground shield 160 covers sidewalls 104 of semiconductor processing chamber 100 to reduce deposition of sputter deposits from sputter surface 133 of sputter target 132 onto components and surfaces behind ground shield 160 .

When the substrate support 126 is in the lower loading position (as shown in FIG. 1 ), the cover ring 170 rests on the ground shield 160 . When the substrate support 126 is in the upper (raised) deposition position, the cover ring 170 is adjacent to and separated from the deposition ring 180 . At the deposition location, the cover ring 170 protects the substrate support 126 from sputter deposition.

FIG. 2 is a top view of a substrate support member according to some embodiments of the disclosure. In detail, FIG. 2 is a top view of the substrate support 126 of FIG. 1 , and some elements in FIG. 2 are not drawn in FIG. 1 . In the embodiment of FIG. 2, the substrate support 126 may be an electrostatic chuck (E-chuck).

As shown, one end of the conduit 137 is exposed through the surface of the substrate support 126 . In more detail, the conduit 137 is substantially exposed at the center portion of the surface of the substrate support 126 . On the other hand, the substrate support 126 may have openings to allow passage of the lift pins 123 . When the lift pin 123 is lifted, the lift pin 123 can pass through the opening of the substrate support 126 and extend upward to receive the substrate 105 (please refer to FIG. 1 ). The lift pins 123 can then be lowered further to move the substrate 105 to the surface of the substrate support 126 . Electrode 126A is also exposed to the surface of substrate support 126 . In some embodiments, the electrodes 126A are dot-like structures evenly distributed on the surface of the substrate support 126 to uniformly provide static electricity to clamp the substrate 105 to the electrodes 126A.

The substrate support 126 also includes the bias sensor 202 . Bias sensor 202 is used to sense the voltage between the surface of substrate support 126 and the backside of substrate 105 during the deposition process. In some embodiments, the bias sensor 202 is embedded in the substrate support 126 . In some embodiments, the bias sensor 202 is "C" shaped and surrounds the conduit 137 . It should be understood, however, that the bias sensor 202 may have other shapes and configurations.

FIGS. 3A to 3D are cross-sectional views at different stages of manufacturing a semiconductor structure according to some embodiments of the present disclosure. Referring to FIG. 3A , FIG. 3A illustrates a substrate 302 . Here, the substrate 302 may be similar to the substrate 105 shown in FIG. 1 . However, the substrate 302 is not limited to the conventional above-meaning substrate. In some embodiments, the substrate 302 may comprise a single semiconductor material, such as silicon, and is used to support semiconductor elements, such as transistors. In other embodiments, the substrate 302 may include a wide range of structures. For example, substrate 302 may include one or more interlayer dielectric layers separating interconnect layers. Alternatively, the substrate 302 may include several layers of previously formed interconnects and/or metal vias/contacts for connection to other layers below or interconnects of semiconductor devices.

Next, an etch stop layer 304 is formed on the substrate 302 . The etch stop layer 304 may be used to prevent diffusion of copper interconnects formed thereon into the dielectric material of the underlying substrate, or to stop etching. Etch stop layer 304 may be any non-conductive material for those purposes, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium silicon nitride (TiSiN), or tantalum silicon nitride (TaSiN), Silicon Carbide (SiC), Silicon Nitride (SiN), NDC (Nitrogen Doped Carbide) or ODC (Oxygen Doped Carbide).

Next, an insulating layer 306 is formed over the etch stop layer 304 . In some embodiments, the insulating layer 306 may be a dielectric material. In some embodiments, the dielectric material may be a low-k (dielectric constant) material with a k value less than 3.9, such as fluorinated silica glass (FSG, k = 2.8), hydrogen silsesquioxane (HSQ, k = 2.9) ), carbon-doped silicon, oxides, etc. In other embodiments, the dielectric material may be typical undoped and doped silicon dioxide (SiO ₂ ), silicon oxynitride (SiON), and silicon nitride (Si ₃ N ₄ ). The low-k dielectric material may be deposited by spin-on or spin-on dielectric processes, CVD, or any other suitable deposition process. After deposition, in one embodiment, the upper portion of the deposited dielectric layer may be removed by a CMP process. In some embodiments, the insulating layer may include more than one layer of different dielectric materials.

Next, a hard mask 308 is formed over the insulating layer 306 . In some embodiments, the material of the hard mask 308 may be titanium nitride (TiN), or other suitable materials. In some embodiments, titanium nitride may be deposited using the deposition chamber shown in FIG. 1 . Please also refer to FIG. 1. For example, during the process operation, the material of the target 132 may be titanium (Ti). At the same time, the gas source 142 includes a non-reactive gas such as argon or xenon, which can energetically impinge on the target 132 and sputter material from the target 132 . The gas source 142 also includes a reactive gas, such as nitrogen, to provide a nitrogen source. The sputtered titanium can react with nitrogen to form titanium nitride and fall on the substrate 302 to form the hard mask 308 .

Next, a photoresist layer 310 is formed over the hard mask 308 . The photoresist may be a suitable material used in the art, such as poly(methyl methacrylate) (PMMA), poly(methyl glutarate) (PMGI), phenol formaldehyde resin, and may be positive or negative photoresist. The photoresist layer 310 can be formed by a deposition process and patterned by a photolithography process.

Referring to FIG. 3B , a spacer layer 320 is deposited over the photoresist layer 310 . In some embodiments, the spacer layer 320 may be SiO ₂ , SiC, or Si ₃ N ₄ , or other suitable dielectric materials. The spacer layer 320 may be formed by a suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or molecular beam epitaxy (MBE).

Referring to FIG. 3C , an etching process is performed to remove the horizontal portion of the spacer layer 320 , so that the vertical portion of the spacer layer 320 remains on the side surface of the photoresist layer 310 . Next, after the etching process, the photoresist layer 310 is removed so that the vertical portion of the spacer layer 320 remains on the upper surface of the hard mask 308 . In some embodiments, the horizontal portions of the spacer layer 320 may be removed using known etching processes, such as wet etching or dry etching. In some embodiments, the photoresist layer 310 may be removed using a suitable method, such as lift-off or ashing.

Referring to FIG. 3D , the insulating layer 306 is etched using the spacer layer 320 as an etch mask to form trenches 325 in the insulating layer 306 . Likewise, suitable etching processes, such as wet etching or dry etching, can be used. Etchants that may be used may include, but are not limited to, wet etchants such as potassium hydroxide (KOH), ethylenediamine and catechol (EDP), or tetramethylammonium hydroxide (TMAH), or plasma etchants, For example Cl2, _CCl4 , _SiCl2 , _BCl3 , _CCl2F2 , _CF4 , _SF6 or _{NF3 .} After the insulating layer 306 is etched, the spacer layer 320 may be removed by another etching process.

FIG. 4 is a method M1 of operating a semiconductor processing chamber according to some embodiments of the present disclosure. Although method M1 is shown and/or described as a series of acts or events, it is to be understood that the method is not limited to the order or acts shown. Thus, in some embodiments, the actions may be performed in a different order than shown, and/or may be performed concurrently. Additionally, in some embodiments, the illustrated actions or events may be divided into multiple actions or events, such actions or events may be performed multiple times or concurrently with other actions or sub-actions. In some embodiments, some actions or events shown may be omitted, and other actions or events not shown may be included.

Please refer to Figure 4 and Figure 5. The method M1 begins with operation S101 , performing a deposition process. As shown in FIG. 5 , the substrate 105 is moved over the substrate support 126 of the semiconductor processing chamber 100 and a layer of material is deposited over the substrate 105 . In some embodiments, the substrate 105 may be the substrate 302 shown in FIG. 3A. In addition, the material layer can be, for example, the hard mask 308 shown in FIG. 3A.

Please continue to refer to Figures 4 and 5. The method M1 proceeds to operation S102 to confirm whether the bias voltage between the substrate supporter and the substrate is normal. In some embodiments, the bias voltage between the substrate support 126 and the substrate 105 can be measured by the bias voltage sensor 202 shown in FIG. 2 , and the system controller 190 can determine whether the bias voltage is normal . The reason for the abnormal bias voltage is that the surface of the substrate support 126 is dirty or organic substances are attached, and the bias voltage is too high and unstable. In some embodiments, operation S102 is performed during the deposition process of operation S101.

If the bias voltage between the substrate supporter and the substrate is normal, the method M1 proceeds to operation S103 to continue the deposition process. In some embodiments, if the bias voltage between the substrate supporter and the substrate is normal, the conditions of the deposition process are determined to be stable, and thus the deposition process will continue to execute until the material layer reaches a desired thickness and then stops. Next, the substrate 105 may be removed from the semiconductor processing chamber 100 for other processes, or an additional layer of material may be deposited outside the semiconductor processing chamber 100 .

If the bias voltage between the substrate supporter and the substrate is abnormal, the method M1 proceeds to operation S104 to issue an alarm and stop the deposition process. In some embodiments, if the bias voltage between the substrate support member and the substrate is abnormal, it means that the surface of the substrate support member 126 may be too dirty, so that the bias voltage between the substrate support member and the substrate is abnormal, thereby causing Poor quality of deposition. In some embodiments, raising the alarm and stopping the deposition process may be performed by the system controller 190 .

Please refer to Figure 4, Figure 6A, and Figure 6B. The method M1 proceeds to operation S105 to perform the first cleaning process. In detail, the first cleaning process is used to clean the upper surface of the substrate supporter 126 . In some embodiments, the substrate 105 is moved out of the semiconductor processing chamber 100 before performing the first cleaning process, thereby exposing the upper surface of the substrate support 126 .

Performing the first cleaning process includes opening the valve V1 connected to the gas source 138 so that a gas, such as argon (Ar), enters the processing region 110 of the semiconductor processing chamber 100 through the upper surface of the substrate support 126 through the conduit 137 . . Next, the RF source 181 is turned on to generate plasma within the semiconductor processing chamber 100 . When the RF source 181 is applied, the cover housing 191 contains conductive walls 185 that can act as anodes and substrate support 126 that can act as cathodes. Positively charged gas ions (eg, argon ions) are attracted to the negatively charged substrate support 126 so that the ions can bombard the surface of the substrate support 126 and thereby clean, or etch away contamination on the surface of the substrate support 126 .

In some embodiments, the first cleaning process is performed under the following conditions: RF energy is about 90W to about 110W; gas flow is about 16 seem to about 20 seem; gas pressure is about 6.5 mtorr to about 8.5 mtorr; cleaning time is About 8 min to about 12 min (eg, about 10 min). In some embodiments, the cleaning time may be regarded as the time interval between turning on the RF source 181 and turning off the RF source 181 during the first cleaning process.

Referring to FIG. 6B, in the first cleaning process, the cleaning gas enters the semiconductor processing chamber 100 through the center of the substrate support 126 through the conduit 137 (as indicated by the dotted arrow in FIG. 6A). . Therefore, the concentration of the gas in the central portion 126C of the substrate support 126 will be greater than the concentration in the peripheral portion 126P of the substrate support 126 . Since the concentration in the central portion 126C is higher, and the gas ions generated are higher, the rate at which the contamination of the central portion 126C of the substrate support 126 is cleaned (or etched) during the first cleaning process will be The rate at which the contamination is cleaned (or the rate at which it is etched) may be higher than that of the peripheral portion 126P of the substrate support 126 . Here, the "central portion" of the substrate support 126 can be considered as a range from the center of the substrate support 126 to about 1/2 of the radius. On the other hand, the "peripheral portion" of the substrate support 126 may be considered to extend at 1/2 the radius of the substrate support 126 to the extent covered by the circumference of the substrate support 126 . In some embodiments, peripheral portion 126P surrounds central portion 126C.

Please refer to Figure 4, Figure 7A, and Figure 7B. The method M1 proceeds to operation S106 to perform the second cleaning process. Performing the second cleaning process includes opening the valve V2 connected to the gas source 142 so that a gas, such as argon (Ar), enters the processing region 110 of the semiconductor processing chamber 100 . Next, the RF source 181 is turned on to generate plasma within the semiconductor processing chamber 100 . When the RF source 181 is applied, the cover housing 191 contains conductive walls 185 that can act as anodes and substrate support 126 that can act as cathodes. Positively charged gas ions (eg, argon ions) are attracted to the negatively charged substrate support 126 so that the ions can bombard the surface of the substrate support 126 and thereby clean, or etch away contamination on the surface of the substrate support 126 .

In some embodiments, the second cleaning process is performed under the following conditions: RF energy is about 90W to about 110W; gas flow is about 7.5 sccm to about 9.5 sccm; gas pressure is about 3.5 mtorr to about 4.5 mtorr; cleaning The time is about 55 minutes to about 65 minutes (eg, about 60 minutes). In some embodiments, the cleaning time may be regarded as the time interval between turning on the RF source 181 and turning off the RF source 181 during the second cleaning process.

Referring to FIG. 7B , in the first cleaning process, the gas for cleaning enters the semiconductor processing chamber 100 through the sidewall 104 of the semiconductor processing chamber 100 through the conduit 144 . Then, the gas will gradually diffuse from the gap between the substrate support 126 and the ground shield 160 and/or cover ring 170 to above the substrate support 126 (as indicated by the dashed arrows in FIG. 7A ). Therefore, the concentration of the gas in the peripheral portion 126P of the substrate support 126 will be greater than the concentration in the central portion 126C of the substrate support 126 . Since the concentration of the peripheral portion 126P is higher, the generated gas ions are also more, so during the second cleaning process, the rate at which the contamination of the peripheral portion 126P of the substrate support 126 is cleaned (or etched) will be The rate at which the contamination is cleaned (or the rate at which it is etched) may be higher than the central portion 126C of the substrate support 126 .

In some embodiments, the gas flow rate of the first cleaning process may be greater than the gas flow rate of the second cleaning process. For example, during the first cleaning process, the flow rate of gas flowing in via conduit 137 may be greater than the flow rate of gas flowing in via conduit 144 during the second cleaning process. On the other hand, the gas pressure in the first cleaning process may be greater than the gas pressure in the second cleaning process. For example, during the first cleaning process, the pressure of the gas flowing through the conduit 137 may be greater than the pressure of the gas flowing through the conduit 144 during the second cleaning process. This is because dirt is more likely to accumulate on the central portion 126C of the substrate support 126 , so the inflow of a higher flow of gas through the conduit 137 during the first cleaning process will help to quickly clean the central portion 126C of the substrate support 126 . In some embodiments, the duration of the first cleaning process may be shorter than the duration of the second cleaning process. As mentioned above, due to the high gas flow rate during the first cleaning process, the duration of the first cleaning process is too long (eg, longer than that of the second cleaning process), which may affect other parts of the semiconductor processing chamber 100 . Components cause unnecessary etching or damage.

In some embodiments, during the first cleaning process, the valve V2 may be closed first to prevent gas from flowing into the semiconductor processing chamber 100 from the conduit 144 . That is, during the first cleaning process, the gas flows into the semiconductor processing chamber 100 only through the conduit 137 in the substrate support 126 . On the other hand, during the second cleaning process, the valve V1 may be closed first to prevent the gas from flowing into the semiconductor processing chamber 100 from the conduit 137 . That is, when the second cleaning process is performed, the gas flows into the semiconductor processing chamber 100 only through the conduit 144 of the side wall 104 of the semiconductor processing chamber 100 .

In the embodiment of FIG. 4, operation S105 is performed before operation 106, that is, the first cleaning process is performed before the second cleaning process. In other embodiments, operation S106 may be performed before operation 105, that is, the second cleaning process is performed before the first cleaning process.

FIG. 8A is a schematic diagram of a computer system used as a controller (eg, system controller 190 ) for performing tasks related to the monitoring, execution, and control of motion, as well as various tasks performed in semiconductor processing chamber 100 Process recipe tasks and recipe steps. The foregoing embodiments can be implemented using computer hardware and computer programs executing thereon. In FIG. 8A, a computer system 600 includes a computer 601 that includes a CD-ROM (eg, CD-ROM or DVD-ROM) drive (optical disk drive) 605 and a disk drive (disk drive) 606, Keyboard 602 , mouse 603 and display 604 .

FIG. 8B is a diagram showing the internal configuration of the computer system 600 . In FIG. 8B, in addition to the optical disk drive 605 and the disk drive 606, the computer 601 also has one or more processors 611, such as a micro processing unit (MPU); a ROM 612, which stores A program such as a startup program; a random access memory (RAM) 613, which is connected to the MPU 611 and which temporarily stores the commands of the application program and provides a temporary storage area; the hard disk 614, which stores the application program, system programs and data; and bus bar 615, which connects MPU 611, ROM 612, and the like. It should be noted that the computer 601 may include a network card (not shown) for providing connection to the LAN.

The code for causing the computer system 600 to perform the operations/tasks discussed in the previous embodiments may be stored on an optical disk 621 or a disk 622, which is inserted into the optical disk drive 605 or the disk drive 606 and transferred to the hard disk Dish 614. Alternatively, the program can be transferred to the computer 601 via a network (not shown) and stored in the hard disk 614 . At execution time, programs are loaded into RAM 613 . Programs can be loaded from CD 621 or disk 622 or directly from the network.

In the program, the functions implemented by the program do not include functions that can be implemented only by hardware in some embodiments. For example, the functions implemented by the above programs do not include functions that can be implemented only by hardware (eg, a network interface) in an acquisition unit for acquiring information or an output unit for outputting information. In addition, the computer executing the program may be a single computer or may be multiple computers.

An embodiment of the present disclosure is a method of cleaning a deposition chamber, including moving a substrate onto a substrate support of a semiconductor processing chamber; performing a deposition process to deposit a material layer on the substrate; moving the substrate out of the semiconductor processing chamber; performing a first cleaning process, wherein performing the first cleaning process includes providing a first gas into the semiconductor processing chamber through a first conduit in the substrate support, and turning on a radio frequency source to generate a plasma of the first gas to clean the surface of the substrate support and performing a second cleaning process, wherein performing the second cleaning process includes providing a second gas into the semiconductor processing chamber through a second conduit disposed on a sidewall of the semiconductor processing chamber, and turning on a radio frequency source to generate a plasma of the second gas to clean the surface of the substrate support.

According to some embodiments, the method further includes stopping supplying the first gas into the semiconductor processing chamber before performing the second cleaning process.

According to some embodiments, the flow rate of the first gas is greater than the flow rate of the second gas.

According to some embodiments, wherein the second cleaning process is performed before the first cleaning process.

An embodiment of the present disclosure is a method for cleaning a deposition chamber, including moving a substrate onto a substrate support of a semiconductor processing chamber; performing a deposition process to deposit a material layer on the substrate; and moving the substrate out of the semiconductor processing chamber a chamber; performing a first cleaning process, wherein performing the first cleaning process includes generating a first plasma within the semiconductor processing chamber to clean the surface of the substrate support, the first plasma cleaning at a central portion of the surface of the substrate support at a rate greater than a cleaning rate at a peripheral portion of the surface; and performing a second cleaning process, wherein performing the second cleaning process includes generating a second plasma within the semiconductor processing chamber to clean the surface of the substrate support, the second plasma at the surface of the substrate support The cleaning rate of the peripheral portion of the surface is greater than the cleaning rate of the central portion of the surface.

According to some embodiments, wherein generating the first plasma includes introducing a first gas from a first conduit of the substrate support into the semiconductor processing chamber, and generating the second plasma includes introducing a second gas from a sidewall of the semiconductor processing chamber through a second conduit. Two gases into the semiconductor processing chamber.

According to some embodiments, the pressure of the first gas is greater than the pressure of the second gas.

An embodiment of the present disclosure is a method of cleaning a deposition chamber, including performing a deposition process in a semiconductor processing chamber to deposit a material layer on a substrate above a substrate support; confirming a bias voltage between the substrate and the substrate support Whether it is normal; if the bias voltage is abnormal, perform a first cleaning process, wherein performing the first cleaning process includes generating a first plasma in the semiconductor processing chamber to clean the surface of the substrate support, and the first plasma is in the substrate support. a central portion of the surface has a greater concentration than a peripheral portion of the surface; and performing a second cleaning process, wherein performing the second cleaning process includes generating a second plasma within the semiconductor processing chamber to clean the surface of the substrate support, the first The concentration of the second plasma is greater in the peripheral portion of the surface of the substrate support than in the central portion of the surface.

According to some embodiments, wherein generating the first plasma includes feeding a first gas into the semiconductor processing chamber from a first conduit of the substrate support, and generating the second plasma includes feeding a second gas from a second conduit in a sidewall of the semiconductor processing chamber gas into the semiconductor processing chamber.

According to some embodiments, during the execution of the first cleaning process, the valve of the second conduit is closed to stop the input of the second gas into the semiconductor processing chamber, and during the execution of the second process, the valve of the first conduit is closed to stop the input of the second gas. A gas is injected into the semiconductor processing chamber.

The foregoing summarizes features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments presented herein. Those skilled in the art should also realize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions and alterations may be made therein without departing from the spirit and scope of the present disclosure.

100: Semiconductor processing chamber 101: Chamber body 102: Adapter 103: Cluster Tools 104: Sidewall 105: Substrate 106: Bottom Wall 108: Upper processing assembly 110: Processing area 120: Base assembly 122: Lifting mechanism 123: Lifting Pin 124: Bellows 126: substrate support 126A: Electrode 126C: Center Section 126P: Peripheral part 127: Substrate receiving surface 128: Platform Shell 129: Perimeter Edge 130: Cover assembly 132: Target 133: Sputtering Surface 134: Back area 136: Ceramic target spacer 137: Catheter 138: Air source 140: Power source 141: Impedance Controller 142: Air source 143: Electrostatic chuck power supply 144: Catheter 146: exhaust port 147: Gate valve 148: Exhaust duct 149: Exhaust pump 151: inner ring 152: Outer Ring 154: Block 156: Tapered part 157: End of inner circumference 159: Outer circumference surface 160: Ground Shield 162: Internal Surface 170: Staggered Cover Rings 171: Lips 173: Coating 180: Deposition Ring 181: RF Source 181A: RF Power Source 181B: RF Matcher 182: DC source 182A: DC power 184: Center Feed 185: Conductive Wall 186: Shield 189: Magnetic Control System 190: System Controller 191: cover shell 193: Motor 202: Bias sensor 302: Substrate 304: etch stop layer 306: Insulation layer 308: hard mask 310: photoresist layer 320: Spacer Layer 325: Groove 600: Computer System 601: Computer 602: Keyboard 603: Mouse 604: Display 605: CD player 606: Disk Drive 611: MPU 612: ROM 613: RAM 614: Hard Disk 615: Busbar 621: CD 622: Disk M1: Method S101, S102, S103, S104, S105, S106: Operation

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. Note that in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. FIG. 1 is a schematic diagram of a semiconductor processing chamber according to some embodiments of the disclosure. FIG. 2 is a top view of a substrate support member according to some embodiments of the disclosure. FIGS. 3A to 3D are cross-sectional views at different stages of manufacturing a semiconductor structure according to some embodiments of the present disclosure. FIG. 4 is a method of operating a semiconductor processing chamber according to some embodiments of the present disclosure. FIGS. 5-7B are schematic views at different stages of a method of operating a semiconductor processing chamber according to some embodiments of the present disclosure. 8A and 8B are schematic diagrams of computer systems according to some embodiments of the present disclosure.

Domestic storage information (please note in the order of storage institution, date and number) none Foreign deposit information (please note in the order of deposit country, institution, date and number) none

M1: Method

S101, S102, S103, S104, S105, S106: Operation

Claims (10)

A method for cleaning a deposition chamber, comprising: moving a substrate onto a substrate support of a semiconductor processing chamber; performing a deposition process to deposit a material layer on the substrate; moving the substrate out of the semiconductor processing chamber ; performing a first cleaning process, wherein performing the first cleaning process includes providing a first gas to the semiconductor process through a first conduit located within the substrate support and having an end exposed from a surface of the substrate support inside the chamber, and turning on a radio frequency source to generate a plasma of the first gas to clean the surface of the substrate support; and performing a second cleaning process, wherein performing the second cleaning process includes configuring the semiconductor process A second conduit in a sidewall of the chamber provides a second gas into the semiconductor processing chamber, and the RF source is turned on to generate a plasma of the second gas to clean the surface of the substrate support. The method of claim 1, further comprising stopping supplying the first gas into the semiconductor processing chamber before performing the second cleaning process. The method of claim 1, wherein the flow rate of the first gas is greater than the flow rate of the second gas. The method of claim 1, wherein the second cleaning process is performed before the first cleaning process. A method for cleaning a deposition chamber, comprising: moving a substrate onto a substrate support of a semiconductor processing chamber; performing a deposition process to deposit a material layer on the substrate; moving the substrate out of the semiconductor processing chamber ; performing a first cleaning process, wherein performing the first cleaning process includes generating a first plasma in the semiconductor processing chamber to clean a surface of the substrate support, the first plasma in the substrate support cleaning a central portion of the surface at a rate greater than a cleaning rate at a peripheral portion of the surface; and performing a second cleaning process, wherein performing the second cleaning process includes generating a second plasma within the semiconductor processing chamber to clean The surface of the substrate support, the cleaning rate of the second plasma at the peripheral portion of the surface of the substrate support is greater than the cleaning rate at the central portion of the surface. 6. The method of claim 5, wherein generating the first plasma includes feeding a first gas into the semiconductor processing chamber from a first conduit of the substrate support, and generating the second plasma includes generating the second plasma from the semiconductor A side wall of the processing chamber and a second conduit input a second gas into the semiconductor processing chamber. The method of claim 6, wherein the pressure of the first gas is greater than the pressure of the second gas. A method for cleaning a deposition chamber, comprising: performing a deposition process in a semiconductor processing chamber to deposit a material layer on a substrate above a substrate support; confirming whether a bias voltage between the substrate and the substrate support is Normal; if the bias voltage is abnormal, perform a first cleaning process, wherein performing the first cleaning process includes generating a first plasma in the semiconductor processing chamber to clean a surface of the substrate support, the first cleaning process a concentration of plasma in a central portion of the surface of the substrate support is greater than a concentration in a peripheral portion of the surface; and performing a second cleaning process, wherein performing the second cleaning process includes generating within the semiconductor processing chamber A second plasma to clean the surface of the substrate support, the concentration of the second plasma at the peripheral portion of the surface of the substrate support being greater than the concentration at the central portion of the surface. 8. The method of claim 8, wherein generating the first plasma includes feeding a first gas into the semiconductor processing chamber from a first conduit of the substrate support, and generating the second plasma includes generating the second plasma from the semiconductor A side wall of the processing chamber and a second conduit input a second gas into the semiconductor processing chamber. The method of claim 9, wherein during the execution of the first cleaning process, a valve of the second conduit is closed to stop the input of the second gas into the semiconductor processing chamber, and during the execution of the second process, closing a valve of the first conduit to stop the input of the first gas to the semiconductor inside the processing chamber.

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