TWI769486B - Distributed synchronization system - Google Patents

Distributed synchronization system Download PDF

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TWI769486B
TWI769486B TW109123927A TW109123927A TWI769486B TW I769486 B TWI769486 B TW I769486B TW 109123927 A TW109123927 A TW 109123927A TW 109123927 A TW109123927 A TW 109123927A TW I769486 B TWI769486 B TW I769486B
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signal
synchronization
ended
tod
control signal
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TW109123927A
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TW202205037A (en
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張智欽
王育民
張海劍
楊凱宇
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優達科技股份有限公司
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Abstract

The invention provides a distributed synchronization system, which includes a management device and a plurality of synchronization devices. The management device includes a network output interface. The network output interface includes multiple first output pins, multiple second output pins, multiple 1 pulse per second (PPS) signal output pins, and multiple time-of-day signal output pins. The first output pins are used to send a reference frequency signal to a first synchronization device. The second output pins are used to send the reference control signal to the first synchronization device. The 1PPS signal output pins are used to send the reference 1PPS signal to the first synchronization device. The time-of-day signal output pins are used to send reference time-of-day information to the first synchronization device.

Description

分散式同步系統Decentralized Synchronization System

本發明是有關於一種通訊同步機制，且特別是有關於一種分散式同步系統。The present invention relates to a communication synchronization mechanism, and in particular, to a distributed synchronization system.

請參照圖1A，其是傳統框架交換器（chassis switch）的示意圖。如圖1A所示，在傳統框架交換器110中，各個線卡（line card，LC）112係獨立連接於控制平面（control plane，CP）111上，以進行時間、相位及頻率的同步。Please refer to FIG. 1A , which is a schematic diagram of a conventional chassis switch. As shown in FIG. 1A , in the conventional frame switch 110 , each line card (LC) 112 is independently connected to a control plane (CP) 111 for synchronization of time, phase and frequency.

請參照圖1B，其是分散式分解框架（distributed disaggregated chassis，DDC）系統的示意圖。有別於圖1A的傳統框架交換器110，在圖1B中的DDC系統120中，CP 121與LC 122之間係採用交織連接（fabric）的方式連接。然而，此種連接方式並不支精確時間協定（precision time protocol，PTP）時間戳記、SyncE或其他硬體時鐘信號傳輸功能，而習知技術中一般會另設置連接於DDC系統的管理交換器，以解決上述問題。Please refer to FIG. 1B , which is a schematic diagram of a distributed disaggregated chassis (DDC) system. Different from the conventional frame switch 110 in FIG. 1A , in the DDC system 120 in FIG. 1B , the CP 121 and the LC 122 are connected by a fabric connection. However, this connection method does not support precision time protocol (PTP) time stamping, SyncE or other hardware clock signal transmission functions, and a management switch connected to the DDC system is generally provided in the prior art to Solve the above problem.

請參照圖2，其是設置有管理交換器的DDC系統的示意圖。如圖2所示，DDC系統200可包括管理交換器201、多個CP及LC（各LC例如可視為一個電信邊界時鐘（telecom boundary clock，T-BC）），而其個別可透過10吉位元乙太網路介面（以下略稱為10G介面）連接於管理交換器201。在圖2中，管理交換器201例如是具備IEEE 1588及同步乙太網路（Synchronous Ethernet，SyncE）能力的管理裝置，並可作為邊界時鐘（boundary clock，BC）以同步於DDC系統200中的LC。Please refer to FIG. 2 , which is a schematic diagram of a DDC system provided with a management switch. As shown in FIG. 2 , the DDC system 200 may include a management switch 201 , a plurality of CPs and LCs (each LC can be regarded as a telecom boundary clock (T-BC), for example), and each of them can transmit 10 gigabits The Meta-Ethernet interface (hereinafter abbreviated as 10G interface) is connected to the management switch 201 . In FIG. 2 , the management switch 201 is, for example, a management device with IEEE 1588 and Synchronous Ethernet (SyncE) capabilities, and can be used as a boundary clock (BC) to synchronize with the DDC system 200 . LC.

在此情況下，管理交換器201可經配置以基於主時鐘（grandmaster，GM）202所提供的PTP封包來讓DDC系統200中的各個LC進行同步，進而讓其他後端的裝置（例如所示的電信時間僕時鐘（Telecom Time Slave Clock，T-TSC）、eNodeB等）進行同步。In this case, the management switch 201 may be configured to synchronize the various LCs in the DDC system 200 based on the PTP packets provided by the grandmaster (GM) 202 , thereby allowing other back-end devices (such as the shown Telecom Time Slave Clock (T-TSC), eNodeB, etc.) for synchronization.

然而，圖2所示的二層式DDC架構（即，一層為管理交換器201，另一層為DDC系統200中的多個LC）中，由於管理交換器201的運作一般將會有5~10ns的時間誤差，而DDC系統200中的各LC在進行同步時亦會有5~10ns的時間誤差，因此將相應地影響同步時的準確性。However, in the two-layer DDC architecture shown in FIG. 2 (ie, one layer is the management switch 201 and the other layer is multiple LCs in the DDC system 200 ), the operation of the management switch 201 will generally take 5-10 ns The time error of each LC in the DDC system 200 will also have a time error of 5-10 ns when synchronizing, so the synchronization accuracy will be affected accordingly.

有鑑於此，本發明提供一種分散式同步系統，其可用於解決上述技術問題。In view of this, the present invention provides a distributed synchronization system, which can be used to solve the above technical problems.

本發明提供一種分散式同步系統，其包括彼此串接的多個同步裝置，其中前述同步裝置中的第i個同步裝置包括網路輸入介面、同步模組及網路輸出介面。網路輸入介面包括多個第一輸入腳位、多個第二輸入腳、位多個1秒脈衝（pulse per second，PPS）信號輸入腳位及多個日時間信號輸入腳位。前述第一輸入腳位用以從前述同步裝置中的第i-1個同步裝置接收

Figure 02_image001
，其中
Figure 02_image003
，N為前述同步裝置的總數，
Figure 02_image001
為所述第i-1個同步裝置產生的頻率信號。前述第二輸入腳位用以從所述第i-1個同步裝置接收一控制信號，其中控制信號要求所述第i個同步裝置同步於所述第i-1個同步裝置。前述1PPS信號輸入腳位用以從所述第i-1個同步裝置接收
Figure 02_image005
，其中
Figure 02_image005
為所述第i-1個同步裝置產生的1PPS信號。前述日時間信號輸入腳位用以從所述第i-1個同步裝置接收
Figure 02_image007
，其中
Figure 02_image007
為所述第i-1個同步裝置產生的日時間資訊。同步模組耦接於網路輸入介面及網路輸出介面之間，並經配置以：基於控制信號、
Figure 02_image005
、
Figure 02_image001
、
Figure 02_image007
執行與所述第i-1個同步裝置的一同步操作，並相應地產生另一同步信號及另一控制信號；以及透過網路輸出介面發送所述另一同步信號及所述另一控制信號。The present invention provides a distributed synchronization system, which includes a plurality of synchronization devices connected in series, wherein the i-th synchronization device in the synchronization devices includes a network input interface, a synchronization module and a network output interface. The network input interface includes a plurality of first input pins, a plurality of second input pins, a plurality of pulse per second (PPS) signal input pins and a plurality of time-of-day signal input pins. The aforementioned first input pin is used for receiving from the i-1 th synchronizing device in the aforementioned synchronizing devices
Figure 02_image001
,in
Figure 02_image003
, N is the total number of the aforementioned synchronization devices,
Figure 02_image001
The frequency signal generated for the i-1th synchronization device. The second input pin is used for receiving a control signal from the i-1 th synchronization device, wherein the control signal requires the i-th synchronization device to synchronize with the i-1 th synchronization device. The aforementioned 1PPS signal input pin is used to receive from the i-1th synchronization device
Figure 02_image005
,in
Figure 02_image005
1PPS signal generated for the i-1th synchronization device. The aforementioned time-of-day signal input pin is used to receive from the i-1th synchronizing device
Figure 02_image007
,in
Figure 02_image007
The time-of-day information generated for the i-1 th synchronization device. The synchronization module is coupled between the network input interface and the network output interface, and is configured to: based on the control signal,
Figure 02_image005
,
Figure 02_image001
,
Figure 02_image007
performing a synchronization operation with the i-1th synchronization device, and correspondingly generating another synchronization signal and another control signal; and sending the other synchronization signal and the another control signal through the network output interface .

本發明提供一種分散式同步系統，其包括彼此串接的多個同步裝置，其中前述同步裝置中的第1個同步裝置包括網路輸入介面、同步模組及網路輸出介面。網路輸入介面包括多個第一輸入腳位、多個第二輸入腳位、多個1PPS信號輸入腳位及多個日時間信號輸入腳位。前述第一輸入腳位用以從一管理裝置接收

Figure 02_image009
，其中
Figure 02_image009
為一管理裝置經解譯一精確時間協定封包而取得的一參考頻率信號。前述第二輸入腳位用以從管理裝置接收一參考控制信號，其中參考控制信號要求所述第1個同步裝置同步於管理裝置。前述1PPS信號輸入腳位，其用以從管理裝置接收
Figure 02_image011
，其中
Figure 02_image011
為管理裝置經解譯精確時間協定封包而取得的一參考1秒脈衝信號。前述日時間信號輸入腳位用以從管理裝置接收
Figure 02_image013
，其中
Figure 02_image013
為管理裝置經解譯精確時間協定封包而取得的一參考日時間資訊。同步模組耦接於網路輸入介面及網路輸出介面之間，並經配置以：基於參考控制信號、
Figure 02_image011
、
Figure 02_image009
、
Figure 02_image013
執行與管理裝置的一同步操作，並相應地產生一第一同步信號及一第一控制信號；以及透過網路輸出介面發送第一同步信號及第一控制信號至前述同步裝置中的第2個同步裝置。The present invention provides a distributed synchronization system, which includes a plurality of synchronization devices connected in series, wherein the first synchronization device in the synchronization devices includes a network input interface, a synchronization module and a network output interface. The network input interface includes a plurality of first input pins, a plurality of second input pins, a plurality of 1PPS signal input pins and a plurality of time-of-day signal input pins. The aforementioned first input pin is used for receiving from a management device
Figure 02_image009
,in
Figure 02_image009
A reference frequency signal obtained by deciphering a PTA packet for a management device. The second input pin is used for receiving a reference control signal from the management device, wherein the reference control signal requires the first synchronization device to be synchronized with the management device. The aforementioned 1PPS signal input pin, which is used to receive from the management device
Figure 02_image011
,in
Figure 02_image011
A reference 1-second pulse signal obtained by the management device by deciphering the PTA packet. The aforementioned time-of-day signal input pin is used to receive from the management device
Figure 02_image013
,in
Figure 02_image013
A reference date and time information obtained by the management device by interpreting the PTA packet. The synchronization module is coupled between the network input interface and the network output interface, and is configured to: based on the reference control signal,
Figure 02_image011
,
Figure 02_image009
,
Figure 02_image013
performing a synchronization operation with the management device, and correspondingly generating a first synchronization signal and a first control signal; and sending the first synchronization signal and the first control signal to the second one of the synchronization devices through the network output interface Synchronization device.

本發明提供一種分散式同步系統，其包括一管理裝置，管理裝置包括處理模組及網路輸出介面。處理模組經配置以提供一參考同步信號及一參考控制信號，其中參考同步信號包括

Figure 02_image011
、
Figure 02_image009
、
Figure 02_image013
，
Figure 02_image011
為一參考1PPS信號，
Figure 02_image009
為一參考頻率信號，
Figure 02_image013
為一參考日時間資訊，且參考控制信號要求彼此串接的多個同步裝置中的第1個同步裝置同步於管理裝置。網路輸出介面耦接於處理模組並接收參考同步信號及參考控制信號，其中網路輸出介面包括：多個第一輸出腳位、多個第二輸出腳位、多個1PPS信號輸出腳位及多個日時間信號輸出腳位。前述第一輸出腳位用以發送
Figure 02_image009
至所述第1個同步裝置。前述第二輸出腳位用以發送參考控制信號至所述第1個同步裝置。前述1PPS信號輸出腳位用以發送
Figure 02_image011
至所述第1個同步裝置。前述日時間信號輸出腳位用以發送
Figure 02_image013
至所述第1個同步裝置。The invention provides a distributed synchronization system, which includes a management device, and the management device includes a processing module and a network output interface. The processing module is configured to provide a reference synchronization signal and a reference control signal, wherein the reference synchronization signal includes
Figure 02_image011
,
Figure 02_image009
,
Figure 02_image013
,
Figure 02_image011
is a reference 1PPS signal,
Figure 02_image009
is a reference frequency signal,
Figure 02_image013
It is a reference date and time information, and the reference control signal requires that the first synchronization device among the plurality of synchronization devices connected in series is synchronized with the management device. The network output interface is coupled to the processing module and receives the reference synchronization signal and the reference control signal, wherein the network output interface includes: a plurality of first output pins, a plurality of second output pins, and a plurality of 1PPS signal output pins And multiple time-of-day signal output pins. The aforementioned first output pin is used to send
Figure 02_image009
to the first synchronization device. The second output pin is used for sending a reference control signal to the first synchronization device. The aforementioned 1PPS signal output pin is used to send
Figure 02_image011
to the first synchronization device. The aforementioned time-of-day signal output pin is used to send
Figure 02_image013
to the first synchronization device.

請參照圖3，其是依據本發明之一實施例繪示的分散式同步系統示意圖。在圖3中，分散式同步系統300例如是一DDC系統，其可包括管理裝置MM及彼此串接的N個同步裝置D1~DN（N為正整數），其中管理裝置MM例如是一管理交換器，而同步裝置D1~DN個別可為一線卡，但可不限於此。Please refer to FIG. 3 , which is a schematic diagram of a distributed synchronization system according to an embodiment of the present invention. In FIG. 3, the distributed synchronization system 300 is, for example, a DDC system, which may include a management device MM and N synchronization devices D1-DN (N is a positive integer) connected in series with each other, wherein the management device MM is, for example, a management switch The synchronizing devices D1 to DN can be one-line cards individually, but not limited to this.

在本發明的實施例中，管理裝置MM可包括網路輸入介面IM及網路輸出介面OM，其可分別為RJ45輸入介面及RJ45輸出介面，但可不限於此。相似地，各同步裝置D1~DN亦可具有網路輸入介面及網路輸出介面。舉例而言，同步裝置D1（其可視為同步裝置D1~DN中的第1個同步裝置）可包括網路輸入介面I1及網路輸出介面O1，同步裝置D2（其可視為同步裝置D1~DN中的第2個同步裝置）可包括網路輸入介面I2及網路輸出介面O2，而同步裝置DN（其可視為同步裝置D1~DN中的第N個同步裝置）可包括網路輸入介面IN及網路輸出介面ON。In the embodiment of the present invention, the management device MM may include a network input interface IM and a network output interface OM, which may be an RJ45 input interface and an RJ45 output interface, respectively, but not limited thereto. Similarly, each of the synchronization devices D1 to DN can also have a network input interface and a network output interface. For example, the synchronizing device D1 (which can be regarded as the first synchronizing device among the synchronizing devices D1-DN) may include the network input interface I1 and the network output interface O1, and the synchronizing device D2 (which can be regarded as the synchronizing devices D1-DN) The second synchronization device in D1-DN may include the network input interface I2 and the network output interface O2, and the synchronization device DN (which can be regarded as the Nth synchronization device among the synchronization devices D1~DN) may include the network input interface IN and network output interface ON.

為便於說明，以下將同步裝置D1~DN中的第i個（

Figure 02_image015
）同步裝置略稱為同步裝置Di，而其可包括網路輸入介面Ii及網路輸出介面Oi，但可不限於此。此外，相似於管理裝置MM，同步裝置Di的網路輸入介面Ii及網路輸出介面Oi亦可分別為RJ45輸入介面及RJ45輸出介面，但可不限於此。For the convenience of description, the following will synchronize the i-th (
Figure 02_image015
) synchronization device is abbreviated as synchronization device Di, which may include a network input interface Ii and a network output interface Oi, but is not limited thereto. In addition, similar to the management device MM, the network input interface Ii and the network output interface Oi of the synchronization device Di can also be an RJ45 input interface and an RJ45 output interface, respectively, but not limited thereto.

簡言之，管理裝置MM及同步裝置D1~DN可依序透過RJ45輸入/輸出介面串接而形成如圖3所示的環狀結構，而管理裝置MM及同步裝置D1~DN兩兩之間可採用習知的RJ45線材連接即可。另外，為了在管理裝置MM及同步裝置D1~DN之間傳遞信號，圖3中的各個網路輸入介面及網路輸出介面的腳位可具有與習知技術不同的定義，而相關細節將在之後另行說明。In short, the management device MM and the synchronization devices D1~DN can be serially connected in series through the RJ45 input/output interface to form a ring structure as shown in FIG. 3, and the management device MM and the synchronization devices D1~DN are connected between two The conventional RJ45 wire can be used for connection. In addition, in order to transmit signals between the management device MM and the synchronization devices D1 to DN, the pins of each network input interface and network output interface in FIG. 3 may have different definitions from those of the prior art, and the relevant details will be described in It will be explained later.

在本發明的實施例中，管理裝置MM、同步裝置D1、同步裝置Di（

Figure 02_image017
）及同步裝置DN可個別用於執行本發明提出的分散式同步方法，但其個別執行的操作皆有所不同，以下將輔以第一至第四實施例作進一步說明。In the embodiment of the present invention, the management device MM, the synchronization device D1, the synchronization device Di (
Figure 02_image017
) and the synchronization device DN can be individually used to execute the distributed synchronization method proposed by the present invention, but the operations performed individually are different, and the following will be further described with the aid of the first to fourth embodiments.

在本發明的第一實施例中，管理裝置MM還可包括處理模組，而此處理模組可包括一處理器（其例如是微處理器、控制器、微控制器、現場可程式閘陣列電路（Field Programmable Gate Array，FPGA）及/或中央處理單元（central processing unit，CPU））及一數位鎖相迴路（digital phase lock loop，DPLL），其中所述處理器可載入特定的軟體、程式碼、應用程式，以協同所述DPLL來實現本發明提出的分散式同步方法，其細節詳述如下。In the first embodiment of the present invention, the management device MM may further include a processing module, and the processing module may include a processor (eg, a microprocessor, a controller, a microcontroller, a field programmable gate array) circuit (Field Programmable Gate Array, FPGA) and/or central processing unit (CPU)) and a digital phase lock loop (DPLL), wherein the processor can be loaded with specific software, The program code and application program can cooperate with the DPLL to realize the distributed synchronization method proposed by the present invention, and the details are described below.

請參照圖4A，其是依據本發明第一實施例繪示的分散式同步方法流程圖。本實施例的方法可由圖3的管理裝置MM執行，以下即搭配圖3所示的元件說明圖4A各步驟的細節。Please refer to FIG. 4A , which is a flowchart of a distributed synchronization method according to the first embodiment of the present invention. The method of this embodiment can be executed by the management device MM in FIG. 3 , and the details of each step in FIG. 4A will be described below in conjunction with the elements shown in FIG. 3 .

首先，在步驟S411中，管理裝置MM可接收PTP封包P1，並解譯PTP封包P1以取得參考1PPS信號（以下以

Figure 02_image011
代稱）、參考頻率信號（以下以
Figure 02_image009
代稱）及參考日時間資訊（以下以
Figure 02_image013
代稱）。First, in step S411, the management device MM can receive the PTP packet P1, and decode the PTP packet P1 to obtain the reference 1PPS signal (hereinafter referred to as the
Figure 02_image011
code name), reference frequency signal (hereinafter referred to as
Figure 02_image009
name) and reference date and time information (below
Figure 02_image013
name).

在一實施例中，管理裝置MM例如可透過網路而從圖2所示的GM取得上述PTP封包P1，並可相應地對其進行解譯以取得

Figure 02_image011
、
Figure 02_image009
、
Figure 02_image013
，但可不限於此。在一實施例中，
Figure 02_image009
例如是具有一預設頻率（例如10MHz）的信號，但可不限於此。In one embodiment, the management device MM can obtain the above-mentioned PTP packet P1 from the GM shown in FIG. 2 through the network, for example, and can interpret it accordingly to obtain the PTP packet P1.
Figure 02_image011
,
Figure 02_image009
,
Figure 02_image013
, but not limited to this. In one embodiment,
Figure 02_image009
For example, it is a signal with a predetermined frequency (eg, 10 MHz), but it is not limited to this.

接著，在步驟S412中，管理裝置MM可透過管理裝置MM的網路輸出介面OM發送參考同步信號

Figure 02_image019
及參考控制信號
Figure 02_image021
至同步裝置D1（即，同步裝置D1~DN中的第1個同步裝置），其中參考同步信號
Figure 02_image019
可包括
Figure 02_image011
、
Figure 02_image009
、
Figure 02_image013
，且參考控制信號
Figure 02_image021
可用於要求同步裝置D1基於參考同步信號
Figure 02_image019
同步於管理裝置MM。在本發明的實施例中，參考控制信號
Figure 02_image021
例如是一種通用非同步收發器（Universal Asynchronous Receiver Transmitter，UART）信號，但可不限於此。Next, in step S412, the management device MM can send the reference synchronization signal through the network output interface OM of the management device MM
Figure 02_image019
and reference control signal
Figure 02_image021
To the synchronizing device D1 (ie, the first synchronizing device among the synchronizing devices D1~DN), wherein the reference synchronization signal
Figure 02_image019
can include
Figure 02_image011
,
Figure 02_image009
,
Figure 02_image013
, and the reference control signal
Figure 02_image021
Can be used to request synchronization device D1 based on a reference synchronization signal
Figure 02_image019
Synchronized with the management device MM. In an embodiment of the present invention, the reference control signal
Figure 02_image021
For example, it is a universal asynchronous receiver (Universal Asynchronous Receiver Transmitter, UART) signal, but it is not limited to this.

在一實施例中，管理裝置MM的數位鎖相迴路可將

Figure 02_image011
進行一回送（loopback）操作，而經回收操作後的
Figure 02_image011
可用於與同步裝置DN所傳來的資訊進行比較，以作為管理裝置MM要求同步裝置D1~DN的至少其中之一進行時間/相位校正操作的依據。相關細節將在之後輔以第五實施例另行說明。In one embodiment, the digital phase locked loop of the management device MM can
Figure 02_image011
A loopback operation is performed, and the
Figure 02_image011
It can be used for comparison with the information sent by the synchronization device DN, and used as a basis for the management device MM to request at least one of the synchronization devices D1 to DN to perform a time/phase correction operation. Relevant details will be described later with the help of the fifth embodiment.

在本發明的第二實施例中，同步裝置D1還可包括同步模組，而此同步模組可包括處理器（其例如是微處理器、控制器、微控制器、FPGA及/或CPU）及數位鎖相迴路，其中所述處理器可載入特定的軟體、程式碼、應用程式，以協同所述數位鎖相迴路來實現本發明提出的分散式同步方法，其細節詳述如下。In the second embodiment of the present invention, the synchronization device D1 may further include a synchronization module, and the synchronization module may include a processor (eg, a microprocessor, a controller, a microcontroller, an FPGA and/or a CPU) and a digital phase-locked loop, wherein the processor can load specific software, code, and application programs to cooperate with the digital phase-locked loop to implement the distributed synchronization method proposed by the present invention, the details of which are described in detail below.

請參照圖4B，其是依據本發明第二實施例繪示的分散式同步方法流程圖。本實施例的方法可由圖3的同步裝置D1執行，以下即搭配圖3所示的元件說明圖4B各步驟的細節。Please refer to FIG. 4B , which is a flowchart of a distributed synchronization method according to the second embodiment of the present invention. The method of this embodiment can be executed by the synchronization device D1 in FIG. 3 , and the details of each step in FIG. 4B will be described below in conjunction with the elements shown in FIG. 3 .

首先，在步驟S421中，同步裝置D1可透過同步裝置D1的網路輸入介面I1從管理裝置MM接收參考同步信號

Figure 02_image019
及參考控制信號
Figure 02_image021
。First, in step S421, the synchronization device D1 can receive the reference synchronization signal from the management device MM through the network input interface I1 of the synchronization device D1
Figure 02_image019
and reference control signal
Figure 02_image021
.

之後，在步驟S422中，同步裝置D1可基於參考同步信號

Figure 02_image019
及參考控制信號
Figure 02_image021
執行與管理裝置MM的同步操作，並相應地產生同步信號
Figure 02_image023
。具體而言，由於參考控制信號
Figure 02_image021
係要求同步裝置D1參考同步信號
Figure 02_image019
同步於管理裝置MM，因此當同步裝置D1接收到參考控制信號
Figure 02_image021
之後，可相應地將管理裝置MM視為主（master）裝置，並以僕（slave）裝置的身分與將自身的頻率、時間、相位同步於管理裝置MM，但可不限於此。Then, in step S422, the synchronization device D1 may be based on the reference synchronization signal
Figure 02_image019
and reference control signal
Figure 02_image021
Performs a synchronization operation with the management device MM and generates a synchronization signal accordingly
Figure 02_image023
. Specifically, since the reference control signal
Figure 02_image021
The system requires the synchronization device D1 to refer to the synchronization signal
Figure 02_image019
Synchronized with the management device MM, so when the synchronization device D1 receives the reference control signal
Figure 02_image021
Afterwards, the management device MM can be regarded as a master device accordingly, and can synchronize its own frequency, time and phase with the management device MM as a slave device, but it is not limited to this.

因此，在第二實施例中，步驟S422中的同步操作可包括時間同步操作、頻率同步操作及相位同步操作。在一實施例中，同步裝置D1可基於參考同步信號

Figure 02_image019
中的
Figure 02_image009
與管理裝置MM進行頻率同步操作，以相應地產生
Figure 02_image025
（即，同步裝置D1產生的頻率信號，其亦可對應於上述預設頻率（例如10MHz））。再者，同步裝置D1可基於參考同步信號
Figure 02_image019
中的
Figure 02_image013
與管理裝置MM進行時間同步操作，以相應地產生
Figure 02_image027
（即，同步裝置D1產生的日時間資訊）。Therefore, in the second embodiment, the synchronization operation in step S422 may include a time synchronization operation, a frequency synchronization operation, and a phase synchronization operation. In one embodiment, the synchronization device D1 may be based on a reference synchronization signal
Figure 02_image019
middle
Figure 02_image009
Frequency synchronisation with the management means MM to generate accordingly
Figure 02_image025
(That is, the frequency signal generated by the synchronization device D1 may also correspond to the above-mentioned preset frequency (eg, 10 MHz)). Furthermore, the synchronization device D1 may be based on a reference synchronization signal
Figure 02_image019
middle
Figure 02_image013
A time synchronization operation with the management device MM to generate accordingly
Figure 02_image027
(that is, the time-of-day information generated by the synchronization device D1).

此外，在第二實施例中，同步裝置D1可基於參考同步信號

Figure 02_image019
中的
Figure 02_image011
與管理裝置MM進行相位同步操作，以相應地產生一特定1PPS信號。之後，同步裝置D1的數位鎖相迴路例如可對此特定1PPS信號執行一回送操作，而同步裝置D1可估計
Figure 02_image011
與（經回送操作後的）特定1PPS信號之間的特定偏移量，並基於此特定偏移量將所述特定1PPS信號校正為
Figure 02_image029
，但本發明可不限於此。在一實施例中，同步裝置D1可另透過10G介面連接於管理裝置MM，並可透過此10G介面將上述特定偏移量回報至管理裝置MM，但可不限於此。Furthermore, in the second embodiment, the synchronization device D1 may be based on a reference synchronization signal
Figure 02_image019
middle
Figure 02_image011
A phase synchronization operation is performed with the management device MM to generate a specific 1PPS signal accordingly. Afterwards, the digital phase-locked loop of the synchronization device D1 can, for example, perform a loopback operation on the specific 1PPS signal, and the synchronization device D1 can estimate
Figure 02_image011
A specific offset from a specific 1PPS signal (after loopback operation), and based on this specific offset, the specific 1PPS signal is corrected to
Figure 02_image029
, but the present invention may not be limited to this. In one embodiment, the synchronization device D1 can be further connected to the management device MM through the 10G interface, and can report the above-mentioned specific offset to the management device MM through the 10G interface, but it is not limited thereto.

接著，在步驟S423中，同步裝置D1可透過同步裝置D1的網路輸出介面O1發送同步信號

Figure 02_image023
及控制信號
Figure 02_image031
至同步裝置D2，其中同步信號
Figure 02_image023
可包括
Figure 02_image029
、
Figure 02_image025
、
Figure 02_image027
，而控制信號
Figure 02_image031
可由同步裝置D1所產生，並用於要求同步裝置D2基於同步信號
Figure 02_image023
同步於同步裝置D1。在本發明的實施例中，控制信號
Figure 02_image031
例如是一種UART信號，但可不限於此。Next, in step S423, the synchronization device D1 can send a synchronization signal through the network output interface O1 of the synchronization device D1
Figure 02_image023
and control signals
Figure 02_image031
to synchronizing device D2, where the synchronizing signal
Figure 02_image023
can include
Figure 02_image029
,
Figure 02_image025
,
Figure 02_image027
, while the control signal
Figure 02_image031
Can be generated by synchronizing device D1 and used to request synchronizing device D2 based on the synchronizing signal
Figure 02_image023
Synchronized with synchronization device D1. In an embodiment of the invention, the control signal
Figure 02_image031
For example, it is a UART signal, but not limited to this.

在本發明的第三實施例中，當

Figure 02_image017
時，同步裝置Di還可包括同步模組，而此同步模組可包括處理器及數位鎖相迴路，其中所述處理器可載入特定的軟體、程式碼、應用程式，以協同所述數位鎖相迴路來實現本發明提出的分散式同步方法，其細節詳述如下。In the third embodiment of the present invention, when
Figure 02_image017
At the same time, the synchronization device Di may also include a synchronization module, and the synchronization module may include a processor and a digital phase-locked loop, wherein the processor may be loaded with specific software, code, and applications to cooperate with the digital The phase-locked loop is used to realize the distributed synchronization method proposed by the present invention, and the details are described as follows.

請參照圖4C，其是依據本發明第三實施例繪示的分散式同步方法流程圖。本實施例的方法可由圖3的同步裝置Di（

Figure 02_image017
）執行，以下即搭配圖3所示的元件說明圖4C各步驟的細節。Please refer to FIG. 4C , which is a flowchart of a distributed synchronization method according to the third embodiment of the present invention. The method of this embodiment can be implemented by the synchronization device Di (
Figure 02_image017
) is executed, and the details of each step in FIG. 4C will be described below with the components shown in FIG. 3 .

首先，在步驟S431中，同步裝置Di可透過同步裝置Di的網路輸入介面Ii從第i-1個同步裝置接收同步信號

Figure 02_image033
及控制信號
Figure 02_image035
，其中控制信號
Figure 02_image035
可由所述第i-1個同步裝置所產生，並用於要求同步裝置Di基於同步信號
Figure 02_image033
同步於所述第i-1個同步裝置。在本發明的實施例中，控制信號
Figure 02_image035
例如是一種UART信號，但可不限於此。First, in step S431, the synchronization device Di can receive a synchronization signal from the i-1 th synchronization device through the network input interface Ii of the synchronization device Di.
Figure 02_image033
and control signals
Figure 02_image035
, where the control signal
Figure 02_image035
can be generated by the i-1 th synchronizing device and used to request the synchronizing device Di based on the synchronizing signal
Figure 02_image033
Synchronized to the i-1 th synchronization device. In an embodiment of the invention, the control signal
Figure 02_image035
For example, it is a UART signal, but not limited to this.

此外，同步信號

Figure 02_image033
可包括
Figure 02_image005
、
Figure 02_image001
、
Figure 02_image007
，其中
Figure 02_image005
為所述第i-1個同步裝置產生的1PPS信號，
Figure 02_image001
為所述第i-1個同步裝置產生的頻率信號（其亦可具有上述預設頻率（例如10MHz）），
Figure 02_image007
為所述第i-1個同步裝置產生的日時間資訊，但可不限於此。In addition, the synchronization signal
Figure 02_image033
can include
Figure 02_image005
,
Figure 02_image001
,
Figure 02_image007
,in
Figure 02_image005
the 1PPS signal generated for the i-1th synchronization device,
Figure 02_image001
the frequency signal generated for the i-1th synchronization device (which may also have the above-mentioned preset frequency (eg 10MHz)),
Figure 02_image007
The time-of-day information generated for the i-1 th synchronization device, but not limited to this.

之後，在步驟S432中，同步裝置Di可基於同步信號

Figure 02_image033
及控制信號
Figure 02_image035
執行與所述第i-1個同步裝置的同步操作，並相應地產生同步信號
Figure 02_image037
。具體而言，由於控制信號
Figure 02_image035
係要求同步裝置Di基於同步信號
Figure 02_image033
同步於所述第i-1個同步裝置，因此當同步裝置Di接收到控制信號
Figure 02_image035
之後，可相應地將所述第i-1個同步裝置視為主裝置，並以僕裝置的身分與將自身的頻率、時間、相位同步於所述第i-1個同步裝置，但可不限於此。Then, in step S432, the synchronization device Di may be based on the synchronization signal
Figure 02_image033
and control signals
Figure 02_image035
perform a synchronizing operation with the i-1th synchronizing device and generate a synchronizing signal accordingly
Figure 02_image037
. Specifically, due to the control signal
Figure 02_image035
The system requires the synchronizing device Di to be based on the synchronizing signal
Figure 02_image033
synchronizing to the i-1th synchronizing device, so when the synchronizing device Di receives the control signal
Figure 02_image035
Afterwards, the i-1 th synchronizing device can be regarded as a master device accordingly, and the frequency, time and phase of itself can be synchronized with the i-1 th synchronizing device as a slave device, but not limited to this.

因此，在第三實施例中，步驟S432中的同步操作可包括時間同步操作、頻率同步操作及相位同步操作。在一實施例中，同步裝置Di可基於同步信號

Figure 02_image033
中的
Figure 02_image001
與所述第i-1個同步裝置進行頻率同步操作，以相應地產生
Figure 02_image039
（即，同步裝置Di產生的頻率信號，其亦可對應於上述預設頻率（例如10MHz））。再者，同步裝置Di可基於同步信號
Figure 02_image033
中的
Figure 02_image007
與所述第i-1個同步裝置進行時間同步操作，以相應地產生
Figure 02_image041
（即，同步裝置Di產生的日時間資訊）。Therefore, in the third embodiment, the synchronization operation in step S432 may include a time synchronization operation, a frequency synchronization operation, and a phase synchronization operation. In one embodiment, the synchronization device Di may be based on a synchronization signal
Figure 02_image033
middle
Figure 02_image001
frequency synchronizing operation with the i-1 th synchronizing device to generate a corresponding
Figure 02_image039
(That is, the frequency signal generated by the synchronization device Di may also correspond to the above-mentioned preset frequency (eg, 10 MHz)). Furthermore, the synchronization device Di may be based on a synchronization signal
Figure 02_image033
middle
Figure 02_image007
perform a time synchronization operation with the i-1th synchronization device to generate a corresponding
Figure 02_image041
(ie, the time of day information generated by the synchronization device Di).

此外，在第三實施例中，同步裝置Di可基於同步信號

Figure 02_image033
中的
Figure 02_image005
與所述第i-1個同步裝置進行相位同步操作，以相應地產生一特定1PPS信號。之後，同步裝置Di的數位鎖相迴路例如可對此特定1PPS信號執行一回送操作，而同步裝置Di可估計
Figure 02_image005
與（經回送操作後的）特定1PPS信號之間的特定偏移量，並基於此特定偏移量將所述特定1PPS信號校正為
Figure 02_image043
，但本發明可不限於此。在一實施例中，同步裝置Di可另透過10G介面連接於管理裝置MM，並可透過此10G介面將上述特定偏移量回報至管理裝置MM，但可不限於此。Furthermore, in the third embodiment, the synchronizing means Di may be based on a synchronizing signal
Figure 02_image033
middle
Figure 02_image005
A phase synchronization operation is performed with the i-1th synchronization device to generate a specific 1PPS signal accordingly. Afterwards, the digital phase-locked loop of the synchronization device Di can, for example, perform a loopback operation on the specific 1PPS signal, and the synchronization device Di can estimate
Figure 02_image005
A specific offset from a specific 1PPS signal (after loopback operation), and based on this specific offset, the specific 1PPS signal is corrected to
Figure 02_image043
, but the present invention may not be limited to this. In one embodiment, the synchronization device Di can be further connected to the management device MM through a 10G interface, and can report the above-mentioned specific offset to the management device MM through the 10G interface, but it is not limited thereto.

接著，在步驟S433中，同步裝置Di可透過同步裝置Di的網路輸出介面Oi發送同步信號

Figure 02_image037
及控制信號
Figure 02_image045
至第i+1個同步裝置，其中同步信號
Figure 02_image037
可包括
Figure 02_image043
、
Figure 02_image047
、
Figure 02_image041
，而控制信號
Figure 02_image045
可由同步裝置Di所產生，並用於要求所述第i+1個同步裝置基於同步信號
Figure 02_image037
同步於同步裝置Di。在本發明的實施例中，控制信號
Figure 02_image045
例如是一種UART信號，但可不限於此。Next, in step S433, the synchronization device Di can send a synchronization signal through the network output interface Oi of the synchronization device Di
Figure 02_image037
and control signals
Figure 02_image045
to the i+1th synchronizing device, where the synchronizing signal
Figure 02_image037
can include
Figure 02_image043
,
Figure 02_image047
,
Figure 02_image041
, while the control signal
Figure 02_image045
can be generated by the sync device Di and used to request the i+1th sync device based on the sync signal
Figure 02_image037
Synchronized to the synchronization device Di. In an embodiment of the invention, the control signal
Figure 02_image045
For example, it is a UART signal, but not limited to this.

在本發明的第四實施例中，同步裝置DN還可包括同步模組，而此同步模組可包括處理器及數位鎖相迴路，其中所述處理器可載入特定的軟體、程式碼、應用程式，以協同所述數位鎖相迴路來實現本發明提出的分散式同步方法，其細節詳述如下。In the fourth embodiment of the present invention, the synchronization device DN may further include a synchronization module, and the synchronization module may include a processor and a digital phase-locked loop, wherein the processor may be loaded with specific software, code, An application program is used to cooperate with the digital phase-locked loop to realize the distributed synchronization method proposed by the present invention, the details of which are detailed as follows.

請參照圖4D，其是依據本發明第四實施例繪示的分散式同步方法流程圖。本實施例的方法可由圖3的同步裝置DN執行，以下即搭配圖3所示的元件說明圖4D各步驟的細節。Please refer to FIG. 4D , which is a flowchart of a distributed synchronization method according to the fourth embodiment of the present invention. The method of this embodiment can be executed by the synchronization device DN of FIG. 3 , and the details of each step of FIG. 4D will be described below with the elements shown in FIG. 3 .

首先，在步驟S441中，同步裝置DN可透過同步裝置DN的網路輸入介面IN從第N-1個同步裝置接收同步信號

Figure 02_image049
及控制信號
Figure 02_image051
，其中控制信號
Figure 02_image051
可由所述第N-1個同步裝置所產生，並用於要求同步裝置DN基於同步信號
Figure 02_image049
同步於所述第N-1個同步裝置。在本發明的實施例中，控制信號
Figure 02_image051
例如是一種UART信號，但可不限於此。First, in step S441, the synchronization device DN can receive a synchronization signal from the N-1th synchronization device through the network input interface IN of the synchronization device DN
Figure 02_image049
and control signals
Figure 02_image051
, where the control signal
Figure 02_image051
can be generated by the N-1th synchronizing device and used to request the synchronizing device DN based on the synchronizing signal
Figure 02_image049
Synchronized to the N-1th synchronization device. In an embodiment of the invention, the control signal
Figure 02_image051
For example, it is a UART signal, but not limited to this.

此外，同步信號

Figure 02_image049
可包括
Figure 02_image053
、
Figure 02_image055
、
Figure 02_image057
，其中
Figure 02_image053
為所述第N-1個同步裝置產生的1PPS信號，
Figure 02_image055
為所述第N-1個同步裝置產生的頻率信號（其亦可具有上述預設頻率（例如10MHz）），
Figure 02_image057
為所述第N-1個同步裝置產生的日時間資訊，但可不限於此。In addition, the synchronization signal
Figure 02_image049
can include
Figure 02_image053
,
Figure 02_image055
,
Figure 02_image057
,in
Figure 02_image053
the 1PPS signal generated for the N-1th synchronization device,
Figure 02_image055
the frequency signal generated for the N-1th synchronization device (which may also have the above-mentioned preset frequency (eg 10MHz)),
Figure 02_image057
The time-of-day information generated for the N-1 th synchronization device, but not limited to this.

之後，在步驟S442中，同步裝置DN可基於同步信號

Figure 02_image049
及控制信號
Figure 02_image051
執行與所述第N-1個同步裝置的同步操作，並相應地產生同步信號
Figure 02_image059
。具體而言，由於控制信號
Figure 02_image051
係要求同步裝置DN基於同步信號
Figure 02_image049
同步於所述第N-1個同步裝置，因此當同步裝置DN接收到控制信號
Figure 02_image051
之後，可相應地將所述第N-1個同步裝置視為主裝置，並以僕裝置的身分與將自身的頻率、時間、相位同步於所述第N-1個同步裝置，但可不限於此。After that, in step S442, the synchronization device DN may be based on the synchronization signal
Figure 02_image049
and control signals
Figure 02_image051
perform a synchronizing operation with the N-1th synchronizing device and generate a synchronizing signal accordingly
Figure 02_image059
. Specifically, due to the control signal
Figure 02_image051
The system requires the synchronization device DN to be based on the synchronization signal
Figure 02_image049
Synchronized to the N-1th synchronizing device, so when the synchronizing device DN receives the control signal
Figure 02_image051
After that, the N-1th synchronization device can be regarded as the master device accordingly, and the frequency, time and phase of itself can be synchronized with the N-1th synchronization device as a slave device, but not limited to this.

因此，在第四實施例中，步驟S442中的同步操作可包括時間同步操作、頻率同步操作及相位同步操作。在一實施例中，同步裝置DN可基於同步信號

Figure 02_image049
中的
Figure 02_image055
與所述第N-1個同步裝置進行頻率同步操作，以相應地產生
Figure 02_image061
（即，同步裝置DN產生的頻率信號，其亦可對應於上述預設頻率（例如10MHz））。再者，同步裝置DN可基於同步信號
Figure 02_image049
中的
Figure 02_image057
與所述第N-1個同步裝置進行時間同步操作，以相應地產生
Figure 02_image063
（即，同步裝置DN產生的日時間資訊）。Therefore, in the fourth embodiment, the synchronization operation in step S442 may include a time synchronization operation, a frequency synchronization operation, and a phase synchronization operation. In one embodiment, the synchronization device DN may be based on a synchronization signal
Figure 02_image049
middle
Figure 02_image055
frequency synchronizing operation with the N-1th synchronizing device to generate a corresponding
Figure 02_image061
(That is, the frequency signal generated by the synchronization device DN may also correspond to the above-mentioned preset frequency (eg, 10 MHz)). Furthermore, the synchronization device DN may be based on a synchronization signal
Figure 02_image049
middle
Figure 02_image057
perform a time synchronization operation with the N-1th synchronization device to generate a corresponding
Figure 02_image063
(ie, the time of day information generated by the synchronization device DN).

此外，在第四實施例中，同步裝置DN可基於同步信號

Figure 02_image049
中的
Figure 02_image053
與所述第N-1個同步裝置進行相位同步操作，以相應地產生一特定1PPS信號。之後，同步裝置DN的數位鎖相迴路例如可對此特定1PPS信號執行一回送操作，而同步裝置DN可估計
Figure 02_image053
與（經回送操作後的）特定1PPS信號之間的特定偏移量，並基於此特定偏移量將所述特定1PPS信號校正為
Figure 02_image065
，但本發明可不限於此。在一實施例中，同步裝置DN可另透過10G介面連接於管理裝置MM，並可透過此10G介面將上述特定偏移量回報至管理裝置MM，但可不限於此。Furthermore, in the fourth embodiment, the synchronization device DN may be based on a synchronization signal
Figure 02_image049
middle
Figure 02_image053
A phase synchronization operation is performed with the N-1th synchronization device to generate a specific 1PPS signal accordingly. Afterwards, the digital phase-locked loop of the synchronizing device DN can perform a loopback operation for this specific 1PPS signal, and the synchronizing device DN can estimate
Figure 02_image053
A specific offset from a specific 1PPS signal (after loopback operation), and based on this specific offset, the specific 1PPS signal is corrected to
Figure 02_image065
, but the present invention may not be limited to this. In an embodiment, the synchronization device DN can be further connected to the management device MM through a 10G interface, and can report the above-mentioned specific offset to the management device MM through the 10G interface, but it is not limited thereto.

接著，在步驟S443中，同步裝置DN可透過同步裝置DN的網路輸出介面ON發送同步信號

Figure 02_image059
及控制信號
Figure 02_image067
至管理裝置MM，其中同步信號
Figure 02_image059
可包括
Figure 02_image065
、
Figure 02_image061
、
Figure 02_image063
，而控制信號
Figure 02_image067
可由同步裝置DN所產生，並用於通知管理裝置MM同步裝置D1~DN已完成同步，但可不限於此。在本發明的實施例中，控制信號
Figure 02_image067
例如是一種UART信號，但可不限於此。Next, in step S443, the synchronization device DN can send a synchronization signal through the network output interface ON of the synchronization device DN
Figure 02_image059
and control signals
Figure 02_image067
to the management means MM, where the synchronization signal
Figure 02_image059
can include
Figure 02_image065
,
Figure 02_image061
,
Figure 02_image063
, while the control signal
Figure 02_image067
It can be generated by the synchronization device DN and used to notify the management device MM that the synchronization devices D1 to DN have completed synchronization, but it is not limited to this. In an embodiment of the invention, the control signal
Figure 02_image067
For example, it is a UART signal, but not limited to this.

在第五實施例中，管理裝置MM可網路輸入介面IM從同步裝置DN接同步信號

Figure 02_image059
及控制信號
Figure 02_image067
。之後，管理裝置MM即可估計（經回送操作的）
Figure 02_image011
及
Figure 02_image065
之間的相位偏移量，並判斷此相位偏移量是否大於一偏移量門限值。In the fifth embodiment, the management device MM can receive the synchronization signal from the synchronization device DN through the network input interface IM
Figure 02_image059
and control signals
Figure 02_image067
. Afterwards, the management device MM can estimate (operated by loopback)
Figure 02_image011
and
Figure 02_image065
and determine whether the phase offset is greater than an offset threshold value.

在一實施例中，反應於判定所述相位偏移量大於偏移量門限值，管理裝置MM可依據相位偏移量與偏移量門限值之間的差值控制同步裝置D1~DN的至少其中之一進行相位校正操作。In one embodiment, in response to determining that the phase offset is greater than the offset threshold, the management device MM may control at least the synchronization devices D1˜DN according to the difference between the phase offset and the offset threshold. One of them performs a phase correction operation.

舉例而言，假設

Figure 02_image011
及
Figure 02_image065
之間的相位偏移量為+7ns，而所述偏移量門限值為5ns。在此情況下，管理裝置MM例如可基於+7ns與5ns之間的差值（即，+2ns）來控制同步裝置D1~DN的至少其中之一進行相位校正操作。例如，管理裝置MM可要求同步裝置D1~DN的其中之二個別將所產生的1PPS信號調慢1ns（即，共調慢2ns），以實現上述相位校正操作，但可不限於此。For example, suppose
Figure 02_image011
and
Figure 02_image065
The phase offset between is +7ns, and the offset threshold is 5ns. In this case, the management device MM may, for example, control at least one of the synchronization devices D1 to DN to perform a phase correction operation based on the difference between +7ns and 5ns (ie, +2ns). For example, the management device MM may require two of the synchronization devices D1 ˜DN to slow down the generated 1PPS signal by 1 ns individually (ie, slow down by 2 ns in total) to realize the above-mentioned phase correction operation, but it is not limited thereto.

由上可知，透過本發明提出的分散式同步系統及方法，可在管理裝置MM不具備IEEE 1588及SyncE功能的情況下，以較低的成本實現同步裝置D1~DN的同步。並且，相較於圖2所示的二層式DDC架構，圖3的單層式DDC架構可達到較高的同步精確度。As can be seen from the above, through the distributed synchronization system and method proposed in the present invention, the synchronization of the synchronization devices D1 to DN can be achieved at a lower cost when the management device MM does not have the IEEE 1588 and SyncE functions. Moreover, compared with the two-layer DDC architecture shown in FIG. 2 , the single-layer DDC architecture of FIG. 3 can achieve higher synchronization accuracy.

請參照圖5，其是依據本發明之一實施例繪示的同步裝置的資料平面及控制平面的示意圖。在圖5中，對於各個同步裝置Di（

Figure 02_image015
）而言，其可包括資料平面DPi及控制平面CPi，其中資料平面DPi可包括100G及400G的介面，而控制平面CPi可包括網路輸入介面Ii、網路輸出介面Oi及10G介面Eth，但可不限於此。Please refer to FIG. 5 , which is a schematic diagram of a data plane and a control plane of a synchronization device according to an embodiment of the present invention. In Figure 5, for each synchronization device Di (
Figure 02_image015
), it can include data plane DPi and control plane CPi, wherein data plane DPi can include 100G and 400G interfaces, and control plane CPi can include network input interface Ii, network output interface Oi and 10G interface Eth, but But not limited to this.

在本實施例中，由於同步裝置Di係透過屬於控制平面CPi中的網路輸入介面Ii及網路輸出介面Oi來接收/發送同步信號及控制信號，而非透過屬於資料平面DPi的100G及400G的介面（即，具有較高傳輸能力）來接收/發送資料量較少的同步信號及控制信號，因此可讓同步裝置Di的硬體資源得到較為適當的利用。In this embodiment, since the synchronization device Di receives/sends synchronization signals and control signals through the network input interface Ii and network output interface Oi belonging to the control plane CPi, rather than through the 100G and 400G belonging to the data plane DPi The interface (ie, having higher transmission capability) is used to receive/send synchronization signals and control signals with less data, so that the hardware resources of the synchronization device Di can be utilized more appropriately.

為使本案的概念更易於理解，以下另輔以圖6說明本案與習知技術的差異。請參照圖6，其是依據圖2及圖3繪示的技術比較圖。在圖6中，DDC系統600例如相同於圖2的DDC系統200，而DDC系統610例如是圖3的分散式同步系統300的一種實施態樣（即，N為5時的態樣）。In order to make the concept of the present case easier to understand, the difference between the present case and the prior art is illustrated with the aid of FIG. 6 below. Please refer to FIG. 6 , which is a technical comparison diagram according to FIG. 2 and FIG. 3 . In FIG. 6 , the DDC system 600 is, for example, the same as the DDC system 200 in FIG. 2 , and the DDC system 610 is, for example, an implementation aspect of the distributed synchronization system 300 in FIG. 3 (ie, the aspect when N is 5).

如先前所提及的，DDC系統600中的管理交換器及各個LC係個別為一邊界時鐘。然而，在實現本發明提出的分散式同步方法之後，DDC系統610中的管理裝置MM及同步裝置D1~D5個別可理解為一普通時鐘（ordinary clock，OC），因而可體現與DDC系統600不同的運作方式/概念。As previously mentioned, the management switch and each LC in DDC system 600 are each a boundary clock. However, after implementing the distributed synchronization method proposed by the present invention, the management device MM and the synchronization devices D1 to D5 in the DDC system 610 can be understood as an ordinary clock (ordinary clock, OC) individually, and thus can be different from the DDC system 600 how/concept.

此外，如先前所提及的，為了讓圖3中的各個網路輸入介面及網路輸出介面可用於傳遞日時間資訊（例如

Figure 02_image069
）、控制信號（例如
Figure 02_image071
）、1PPS信號（例如
Figure 02_image073
）及頻率信號（例如
Figure 02_image075
），各網路輸入介面及網路輸出介面的腳位可具有與習知RJ45不同的定義，以下將作進一步說明。Furthermore, as mentioned earlier, in order to allow the various network input and network output interfaces in Figure 3 to be used to communicate time of day information (eg
Figure 02_image069
), control signals (e.g.
Figure 02_image071
), 1PPS signal (e.g.
Figure 02_image073
) and frequency signals (e.g.
Figure 02_image075
), the pins of each network input interface and network output interface may have different definitions from those of the conventional RJ45, which will be further described below.

在本發明的實施例中，所提及的日時間資訊、控制信號、1PPS信號及頻率信號個別可為一差動信號。在此情況下，每個1PPS信號（例如

Figure 02_image073
）可理解為包括1PPS-及1PPS+等信號成分；每個頻率信號（例如是對應於10MHz的
Figure 02_image075
）可理解為包括10M-及10M+等信號成分；每個控制信號（例如
Figure 02_image071
）可理解為包括UART-及UART+等信號成分；每個日時間資訊（例如
Figure 02_image069
）可理解為包括ToD-及ToD+等信號成分，但可不限於此。In the embodiment of the present invention, the mentioned time-of-day information, the control signal, the 1PPS signal and the frequency signal can each be a differential signal. In this case, each 1PPS signal (eg
Figure 02_image073
) can be understood as including signal components such as 1PPS- and 1PPS+; each frequency signal (for example, corresponding to 10MHz)
Figure 02_image075
) can be understood as including signal components such as 10M- and 10M+; each control signal (for example,
Figure 02_image071
) can be understood as including signal components such as UART- and UART+;
Figure 02_image069
) can be understood to include signal components such as ToD- and ToD+, but not limited to this.

請參照圖7，其是依據本發明之一實施例繪示的習知RJ45介面腳位表與本案RJ45介面腳位表的比較圖。如圖7所示，在習知RJ45介面腳位表710中共有編號1至編號8等8個腳位，其中編號1及2（以下將編號1及2的腳位稱為第一腳位）係保留（reserved）腳位，編號3係用於傳送/接收1PPS-，編號4為接地端腳位，編號5為使用者定義（user-defined）腳位（以下將編號4及5的腳位稱為第二腳位），編號6用於傳送/接收1PPS+，編號7用於傳送/接收ToD-，編號8用於傳送/接收ToD+。Please refer to FIG. 7 , which is a comparison diagram of the conventional RJ45 interface pin table and the RJ45 interface pin table of the present case according to an embodiment of the present invention. As shown in FIG. 7 , there are 8 pins numbered 1 to 8 in the conventional RJ45 interface pin table 710 , among which the pins are numbered 1 and 2 (the pins numbered 1 and 2 are referred to as the first pins hereinafter) It is reserved (reserved) pin, No. 3 is used to transmit/receive 1PPS-, No. 4 is a ground pin, No. 5 is a user-defined (user-defined) pin (the following will be No. 4 and 5 pins Called the second pin), number 6 is used to transmit/receive 1PPS+, number 7 is used to transmit/receive ToD-, and number 8 is used to transmit/receive ToD+.

然而，在本案的RJ45介面腳位表720中，編號1改為用於傳送/接收10M-，編號2改為用於傳送/接收10M+（即，上述第一腳位改為用於傳送/接收頻率信號）。另外，編號4改為用於傳送/接收UART-，而編號5則改為用於傳送/接收UART+（即，上述第二腳位改為用於傳送/接收控制信號）。其餘的編號3、6、7、8的功能則未更動。However, in the RJ45 interface pin table 720 of this case, the number 1 is changed to transmit/receive 10M-, and the number 2 is changed to transmit/receive 10M+ (that is, the first pin above is changed to transmit/receive frequency signal). In addition, number 4 is changed to transmit/receive UART-, and number 5 is changed to transmit/receive UART+ (ie, the second pin above is changed to transmit/receive control signals). The rest of the functions numbered 3, 6, 7, and 8 remain unchanged.

在此情況下，當圖3中的任一網路輸入介面採用RJ45介面腳位表720時，此網路輸入介面即可透過編號1~8的腳位分別接收10M-、10M+、1PPS-、UART-、UART+、1PPS+、ToD-及ToD+等信號成分，但可不限於此。換言之，編號1、2可理解為第一輸入腳位，編號3、6可理解為1PPS信號輸入腳位，編號4、5可理解為第二輸入腳位，編號7、8可理解為日時間信號輸入腳位，但可不限於此。In this case, when any network input interface in Figure 3 uses the RJ45 interface pin table 720, the network input interface can receive 10M-, 10M+, 1PPS-, Signal components such as UART-, UART+, 1PPS+, ToD- and ToD+, but not limited to this. In other words, numbers 1 and 2 can be understood as the first input pins, numbers 3 and 6 can be understood as 1PPS signal input pins, numbers 4 and 5 can be understood as the second input pins, and numbers 7 and 8 can be understood as the time of day Signal input pin, but not limited to this.

另一方面，當圖3中的任一網路輸出介面採用RJ45介面腳位表720時，此網路輸入介面即可透過編號1~8的腳位分別傳送10M-、10M+、1PPS-、UART-、UART+、1PPS+、ToD-及ToD+等信號成分，但可不限於此。換言之，編號1、2可理解為第一輸出腳位，編號3、6可理解為1PPS信號輸出腳位，編號4、5可理解為第二輸出腳位，編號7、8可理解為日時間信號輸出腳位，但可不限於此。On the other hand, when any network output interface in Figure 3 uses the RJ45 interface pin table 720, the network input interface can transmit 10M-, 10M+, 1PPS-, UART through the pins numbered 1 to 8 respectively. -, UART+, 1PPS+, ToD-, ToD+ and other signal components, but not limited to this. In other words, numbers 1 and 2 can be understood as the first output pin, numbers 3 and 6 can be understood as 1PPS signal output pins, numbers 4 and 5 can be understood as the second output pin, and numbers 7 and 8 can be understood as the time of day Signal output pin, but not limited to this.

請參照圖8，其是依據本發明之一實施例繪示的同步裝置的功能方塊圖。在圖8中，同步裝置Di可包括網路輸入介面Ii、網路輸出介面Oi及同步模組SNi，其中網路輸入介面Ii、網路輸出介面Oi可個別採用圖7所示的RJ45介面腳位表720。Please refer to FIG. 8 , which is a functional block diagram of a synchronization device according to an embodiment of the present invention. In FIG. 8 , the synchronization device Di may include a network input interface Ii, a network output interface Oi, and a synchronization module SNi, wherein the network input interface Ii and the network output interface Oi can individually use the RJ45 interface pins shown in FIG. 7 . Bit table 720.

在此情況下，網路輸入介面Ii可用於接收來自前一級裝置的

Figure 02_image077
、
Figure 02_image079
、
Figure 02_image081
及控制信號
Figure 02_image035
，而網路輸出介面Oi則可用於傳送同步裝置Di產生的
Figure 02_image083
、
Figure 02_image039
、
Figure 02_image085
及控制信號
Figure 02_image045
至下一級裝置。舉例而言，若同步裝置Di為同步裝置D1（即，i為1），則網路輸入介面Ii可用於接收來自圖3中管理裝置MM（即，同步裝置D1的前一級裝置）的
Figure 02_image011
、
Figure 02_image009
、
Figure 02_image013
及參考控制信號
Figure 02_image021
，而網路輸出介面Oi則可用於傳送
Figure 02_image029
、
Figure 02_image025
、
Figure 02_image027
及控制信號
Figure 02_image031
至同步裝置D2（即，同步裝置D1的下一級裝置）。舉另一例而言，若同步裝置Di為同步裝置DN（即，i為N），則網路輸入介面Ii可用於接收來自圖3中第N-1個同步裝置（即，同步裝置DN的前一級裝置）的
Figure 02_image087
、
Figure 02_image089
、
Figure 02_image091
及控制信號
Figure 02_image051
，而網路輸出介面Oi則可用於傳送
Figure 02_image065
、
Figure 02_image061
、
Figure 02_image063
及控制信號
Figure 02_image067
至管理裝置MM（即，同步裝置DN的下一級裝置）。In this case, the network input interface Ii can be used to receive
Figure 02_image077
,
Figure 02_image079
,
Figure 02_image081
and control signals
Figure 02_image035
, and the network output interface Oi can be used to transmit the
Figure 02_image083
,
Figure 02_image039
,
Figure 02_image085
and control signals
Figure 02_image045
to the next level device. For example, if the synchronizing device Di is the synchronizing device D1 (ie, i is 1), then the network input interface Ii can be used to receive information from the management device MM (ie, the previous-level device of the synchronizing device D1 ) in FIG. 3 .
Figure 02_image011
,
Figure 02_image009
,
Figure 02_image013
and reference control signal
Figure 02_image021
, while the network output interface Oi can be used to transmit
Figure 02_image029
,
Figure 02_image025
,
Figure 02_image027
and control signals
Figure 02_image031
To sync device D2 (ie, the next-level device to sync device D1). For another example, if the synchronizing device Di is the synchronizing device DN (ie, i is N), the network input interface Ii can be used to receive data from the N-1 th synchronizing device in FIG. primary device)
Figure 02_image087
,
Figure 02_image089
,
Figure 02_image091
and control signals
Figure 02_image051
, while the network output interface Oi can be used to transmit
Figure 02_image065
,
Figure 02_image061
,
Figure 02_image063
and control signals
Figure 02_image067
To the management device MM (ie, the device next to the synchronization device DN).

另外，如先前所提及的，網路輸入介面Ii所接收的控制信號

Figure 02_image035
、
Figure 02_image005
、
Figure 02_image001
、
Figure 02_image007
個別可為一差動信號，即圖8上半部雙虛線處所示的10M-/+、1PPS-/+、UART-/+及ToD-/+。In addition, as mentioned earlier, the control signals received by the network input interface Ii
Figure 02_image035
,
Figure 02_image005
,
Figure 02_image001
,
Figure 02_image007
Each can be a differential signal, ie, 10M-/+, 1PPS-/+, UART-/+, and ToD-/+ shown at the double-dashed line in the upper half of FIG. 8 .

在一實施例中，同步模組SNi可基於控制信號

Figure 02_image035
、
Figure 02_image005
、
Figure 02_image001
、
Figure 02_image007
執行與前一級裝置的同步操作，並相應地產生同步信號
Figure 02_image037
及控制信號
Figure 02_image045
。之後，同步模組SNi可透過網路輸出介面Oi發送同步信號
Figure 02_image037
及控制信號
Figure 02_image045
至下一級裝置。同步模組SNi所執行操作的細節可參考先前實施例中有關於同步裝置D1~DN的說明，於此不另贅述。In one embodiment, the synchronization module SNi may be based on a control signal
Figure 02_image035
,
Figure 02_image005
,
Figure 02_image001
,
Figure 02_image007
Executes the synchronization operation with the previous stage device and generates the synchronization signal accordingly
Figure 02_image037
and control signals
Figure 02_image045
. After that, the synchronization module SNi can send the synchronization signal through the network output interface Oi
Figure 02_image037
and control signals
Figure 02_image045
to the next level device. For details of the operations performed by the synchronization module SNi, reference may be made to the descriptions of the synchronization devices D1 to DN in the previous embodiments, which will not be repeated here.

如圖8所示，同步模組SNi可包括差動至單端橋接器DSi、數位鎖相迴路LLi、處理器Pi及單端至差動橋接器SDi。差動至單端橋接器DSi可耦接於網路輸入介面Ii，並用於將

Figure 02_image001
、
Figure 02_image005
、控制信號
Figure 02_image035
及
Figure 02_image007
分別轉換為對應的第一單端信號
Figure 02_image093
、第二單端信號
Figure 02_image095
、第三單端信號
Figure 02_image097
及第四單端信號
Figure 02_image099
。As shown in FIG. 8 , the synchronous module SNi may include a differential-to-single-ended bridge DSi, a digital phase-locked loop LLi, a processor Pi, and a single-ended-to-differential bridge SDi. The differential-to-single-ended bridge DSi can be coupled to the network input interface Ii and used to convert the
Figure 02_image001
,
Figure 02_image005
,control signal
Figure 02_image035
and
Figure 02_image007
Converted to the corresponding first single-ended signal respectively
Figure 02_image093
, the second single-ended signal
Figure 02_image095
, the third single-ended signal
Figure 02_image097
and the fourth single-ended signal
Figure 02_image099
.

在一實施例中，由於硬體上的特性，控制信號

Figure 02_image035
及
Figure 02_image007
等二個差動信號會彼此綁定（bundle），因此差動至單端橋接器DSi可在接收綁定的控制信號
Figure 02_image035
及
Figure 02_image007
之後，將此二差動信號分離，並個別轉換為對應的單端信號。In one embodiment, due to features on the hardware, the control signal
Figure 02_image035
and
Figure 02_image007
The two differential signals will be bundled with each other, so the differential-to-single-ended bridge DSi can receive the bundled control signals
Figure 02_image035
and
Figure 02_image007
Afterwards, the two differential signals are separated and individually converted into corresponding single-ended signals.

在此情況下，差動至單端橋接器DSi可包括RS422埠DSi1及UART DSi2。RS422埠DSi1可耦接於上述第二輸入腳位（即，網路輸入介面Ii的編號4、5）及上述日時間信號輸入腳位（即，網路輸入介面Ii的編號7、8），並用於接收彼此綁定的該參考控制信號及

Figure 02_image013
。另外，UART DSi2可耦接於RS422埠DSi1及處理器Pi，並用於分離控制信號
Figure 02_image035
及
Figure 02_image007
，並將控制信號
Figure 02_image035
及
Figure 02_image007
分別轉換成對應的第三單端信號
Figure 02_image097
及第四單端信號
Figure 02_image099
。In this case, the differential-to-single-ended bridge DSi may include the RS422 port DSi1 and the UART DSi2. The RS422 port DSi1 can be coupled to the above-mentioned second input pins (ie, the numbers 4 and 5 of the network input interface Ii) and the above-mentioned time-of-day signal input pins (ie, the numbers 7 and 8 of the network input interface Ii), and used to receive the reference control signal bound to each other and
Figure 02_image013
. In addition, UART DSi2 can be coupled to RS422 port DSi1 and processor Pi, and used to separate control signals
Figure 02_image035
and
Figure 02_image007
, and will control the signal
Figure 02_image035
and
Figure 02_image007
are converted into corresponding third single-ended signals respectively
Figure 02_image097
and the fourth single-ended signal
Figure 02_image099
.

數位鎖相迴路LLi耦接於差動至單端橋接器DSi，並接收分別對應於

Figure 02_image001
、
Figure 02_image005
的第一單端信號
Figure 02_image093
及第二單端信號
Figure 02_image095
。The digital phase-locked loop LLi is coupled to the differential-to-single-ended bridge DSi, and receives corresponding
Figure 02_image001
,
Figure 02_image005
The first single-ended signal of
Figure 02_image093
and the second single-ended signal
Figure 02_image095
.

處理器Pi耦接於數位鎖相迴路LLi及差動至單端橋接器DSi，並經配置以控制數位鎖相迴路LLi基於第一單端信號

Figure 02_image093
及第二單端信號
Figure 02_image095
執行與前一級裝置的頻率同步操作及相位同步操作，並相應地產生第五單端信號
Figure 02_image101
及第六單端信號
Figure 02_image103
，其中第五單端信號
Figure 02_image101
及第六單端信號
Figure 02_image103
分別對應於第一單端信號
Figure 02_image093
及第二單端信號
Figure 02_image095
。接著，處理器Pi可從差動至單端橋接器DSi接收分別對應於控制信號
Figure 02_image035
及
Figure 02_image007
的第三單端信號
Figure 02_image097
及第四單端信號
Figure 02_image099
，並基於第三單端信號
Figure 02_image097
產生第七單端信號
Figure 02_image105
（即用於控制下一級裝置與同步裝置Di進行同步的單端信號）。並且，處理器Pi可基於第四單端信號
Figure 02_image099
執行與前一級裝置的時間同步操作，以產生第八單端信號
Figure 02_image107
。The processor Pi is coupled to the digital phase-locked loop LLi and the differential-to-single-ended bridge DSi, and is configured to control the digital phase-locked loop LLi based on the first single-ended signal
Figure 02_image093
and the second single-ended signal
Figure 02_image095
Perform frequency synchronization operation and phase synchronization operation with the previous stage device, and generate the fifth single-ended signal accordingly
Figure 02_image101
and the sixth single-ended signal
Figure 02_image103
, where the fifth single-ended signal
Figure 02_image101
and the sixth single-ended signal
Figure 02_image103
respectively correspond to the first single-ended signal
Figure 02_image093
and the second single-ended signal
Figure 02_image095
. Then, the processor Pi may receive control signals corresponding to the respective control signals from the differential-to-single-ended bridge DSi
Figure 02_image035
and
Figure 02_image007
The third single-ended signal of
Figure 02_image097
and the fourth single-ended signal
Figure 02_image099
, and based on a third single-ended signal
Figure 02_image097
Generate a seventh single-ended signal
Figure 02_image105
(ie, a single-ended signal used to control the synchronization of the next-level device with the synchronization device Di). Also, the processor Pi may be based on the fourth single-ended signal
Figure 02_image099
Performs a time synchronization operation with the previous stage device to generate the eighth single-ended signal
Figure 02_image107
.

單端至差動橋接器SDi可耦接於處理器Pi及數位鎖相迴路LLi，並經配置以從數位鎖相迴路LLi接收第五單端信號

Figure 02_image101
及第六單端信號
Figure 02_image103
，並將其分別轉換為
Figure 02_image047
、
Figure 02_image043
。另外，單端至差動橋接器SDi可從處理器Pi接收第七單端信號
Figure 02_image105
及第八單端信號
Figure 02_image107
，並將其分別轉換為控制信號
Figure 02_image045
及
Figure 02_image041
。之後，單端至差動橋接器SDi可將
Figure 02_image047
、
Figure 02_image043
、控制信號
Figure 02_image045
及
Figure 02_image041
發送至網路輸出介面Oi。The single-ended-to-differential bridge SDi may be coupled to the processor Pi and the digital phase-locked loop LLi, and is configured to receive a fifth single-ended signal from the digital phase-locked loop LLi
Figure 02_image101
and the sixth single-ended signal
Figure 02_image103
, and convert them to
Figure 02_image047
,
Figure 02_image043
. Additionally, the single-ended-to-differential bridge SDi may receive a seventh single-ended signal from the processor Pi
Figure 02_image105
and the eighth single-ended signal
Figure 02_image107
, and convert them into control signals respectively
Figure 02_image045
and
Figure 02_image041
. Then, the single-ended-to-differential bridge SDi can convert
Figure 02_image047
,
Figure 02_image043
,control signal
Figure 02_image045
and
Figure 02_image041
Sent to the network output interface Oi.

此外，單端至差動橋接器SDi可包括RS422埠SDi1及UART SDi2。RS422埠SDi1可耦接於上述第二輸出腳位（即，網路輸出介面Oi的編號4、5）及上述日時間信號輸出腳位（即，網路輸出介面Oi的編號7、8）。另外，UART SDi2可耦接於RS422埠SDi1及處理器Pi。在本實施例中，UART SDi2可用於將第七單端信號

Figure 02_image105
及第八單端信號
Figure 02_image107
分別轉換為對應的差動信號（即，控制信號
Figure 02_image045
及
Figure 02_image041
），並將控制信號
Figure 02_image045
綁定於
Figure 02_image041
，以及將綁定後的控制信號
Figure 02_image045
及
Figure 02_image041
發送至RS422埠SDi1。之後，RS422埠SDi1即可將綁定後的控制信號
Figure 02_image045
及
Figure 02_image041
傳送至網路輸出介面Oi中的對應腳位，以發送至下一級裝置（的網路輸入介面），但可不限於此。In addition, the single-ended to differential bridge SDi may include RS422 port SDi1 and UART SDi2. The RS422 port SDi1 can be coupled to the second output pins (ie, numbers 4 and 5 of the network output interface Oi) and the above-mentioned time-of-day signal output pins (ie, numbers 7 and 8 of the network output interface Oi). In addition, the UART SDi2 can be coupled to the RS422 port SDi1 and the processor Pi. In this embodiment, UART SDi2 can be used to convert the seventh single-ended signal
Figure 02_image105
and the eighth single-ended signal
Figure 02_image107
are converted into corresponding differential signals (i.e., control signals
Figure 02_image045
and
Figure 02_image041
), and will control the signal
Figure 02_image045
bound to
Figure 02_image041
, and the bound control signal
Figure 02_image045
and
Figure 02_image041
Send to RS422 port SDi1. After that, the RS422 port SDi1 can bind the control signal
Figure 02_image045
and
Figure 02_image041
It is sent to the corresponding pin in the network output interface Oi for sending to the next-level device (the network input interface of the device), but it is not limited to this.

請參照圖9A，其是依據本發明之一實施例繪示的管理裝置的功能方塊圖。如圖9A所示，管理裝置MM可包括處理模組PM、網路輸出介面Oi及一單端至差動橋接器。在本實施例中，處理模組PM可用於提供參考同步信號

Figure 02_image019
及參考控制信號
Figure 02_image021
。具體而言，處理模組PM可包括處理器MP及數位鎖相迴路ML，其中處理器MP可在透過10G介面從GM（未繪示）接收PTP封包P1之後，藉由解譯PTP封包P1而取得對應於
Figure 02_image011
、
Figure 02_image009
、
Figure 02_image013
。之後，處理器MP可控制數位鎖相迴路ML對
Figure 02_image011
進行回送操作，以用於與同步裝置DN提供的
Figure 02_image065
比較。另外，處理器MP可產生用於要求同步裝置D1基於參考同步信號
Figure 02_image019
同步於管理裝置MM的參考控制信號
Figure 02_image021
，並透過管理裝置MM的單端至差動橋接器將
Figure 02_image011
、
Figure 02_image009
、
Figure 02_image013
及參考控制信號
Figure 02_image021
發送至網路輸出介面OM。相應地，網路輸出介面OM即可將
Figure 02_image011
、
Figure 02_image009
、
Figure 02_image013
及參考控制信號
Figure 02_image021
發送至同步裝置D1。Please refer to FIG. 9A , which is a functional block diagram of a management device according to an embodiment of the present invention. As shown in FIG. 9A, the management device MM may include a processing module PM, a network output interface Oi, and a single-ended-to-differential bridge. In this embodiment, the processing module PM can be used to provide the reference synchronization signal
Figure 02_image019
and reference control signal
Figure 02_image021
. Specifically, the processing module PM can include a processor MP and a digital phase-locked loop ML, wherein the processor MP can decode the PTP packet P1 by interpreting the PTP packet P1 after receiving the PTP packet P1 from the GM (not shown) through the 10G interface. get corresponding to
Figure 02_image011
,
Figure 02_image009
,
Figure 02_image013
. After that, the processor MP can control the digital phase locked loop ML pair
Figure 02_image011
A loopback operation is performed for synchronization with the device DN provided by the
Figure 02_image065
Compare. In addition, the processor MP may generate a synchronization signal for requesting the synchronization device D1 to be based on the reference
Figure 02_image019
Synchronized to the reference control signal of the management device MM
Figure 02_image021
, and through the single-ended to differential bridge of the management device MM will
Figure 02_image011
,
Figure 02_image009
,
Figure 02_image013
and reference control signal
Figure 02_image021
Sent to the network output interface OM. Correspondingly, the network output interface OM can
Figure 02_image011
,
Figure 02_image009
,
Figure 02_image013
and reference control signal
Figure 02_image021
Sent to sync device D1.

在圖9A中，處理器MP與所示單端至差動橋接器之間的信號傳遞方式，以及單端至差動橋接器的運作方式可參照圖8中處理器Pi與單端至差動橋接器SDi的相關說明，其細節於此不另贅述。In FIG. 9A , the signal transmission mode between the processor MP and the single-ended-to-differential bridge shown, and the operation of the single-ended-to-differential bridge can refer to the processor Pi and the single-ended-to-differential bridge in FIG. 8 . The related description of the bridge SDi will not be repeated here.

請參照圖9B，其是依據圖9A繪示的管理裝置的功能方塊圖。在本實施例中，管理裝置MM可更包括網路輸入介面IM，其可用於接收來自同步裝置DN的

Figure 02_image065
、
Figure 02_image061
、
Figure 02_image063
及控制信號
Figure 02_image067
，並相應地轉傳至處理模組PM。Please refer to FIG. 9B , which is a functional block diagram of the management device shown in FIG. 9A . In this embodiment, the management device MM can further include a network input interface IM, which can be used to receive the information from the synchronization device DN.
Figure 02_image065
,
Figure 02_image061
,
Figure 02_image063
and control signals
Figure 02_image067
, and correspondingly forwarded to the processing module PM.

另外，本實施例的處理模組PM可另包括所示的差動至單端橋接器，而其運作的方式可參照圖8中差動至單端橋接器DSi的相關說明，於此不另贅述。In addition, the processing module PM of this embodiment may further include a differential-to-single-ended bridge as shown, and the operation of the differential-to-single-ended bridge DSi can be referred to in FIG. Repeat.

綜上所述，透過本發明提出的分散式同步系統及方法，可在管理裝置不具備IEEE 1588及SyncE功能的情況下，以較低的成本實現同步裝置之間的同步。並且，相較於習知的二層式DDC架構，本案所呈現的單層式DDC架構可達到較高的同步精確度。To sum up, through the distributed synchronization system and method proposed in the present invention, synchronization between synchronization devices can be achieved at a lower cost when the management device does not have the IEEE 1588 and SyncE functions. Moreover, compared with the conventional two-layer DDC architecture, the single-layer DDC architecture presented in this case can achieve higher synchronization accuracy.

並且，由於本案的管理裝置及同步裝置係透過RJ45輸出/輸入介面傳送/接收對應的控制信號、1PPS信號、日時間資訊及頻率信號，而非透過資料平面中具較高傳輸能力的介面進行傳送，因此可讓管理裝置及同步裝置的硬體資源得到較合理的運用。Moreover, because the management device and synchronization device in this case transmit/receive the corresponding control signals, 1PPS signals, time-of-day information and frequency signals through the RJ45 output/input interface, rather than through the interface with higher transmission capability in the data plane. , so that the hardware resources of the management device and the synchronization device can be used more reasonably.

另外，為讓本案的RJ45輸出/輸入介面可用於傳送/接收控制信號及頻率信號，本案的RJ45輸出/輸入介面中的多個腳位可具有異於習知作法的定義方式。In addition, in order to allow the RJ45 output/input interface of the present application to be used for transmitting/receiving control signals and frequency signals, a plurality of pins in the RJ45 output/input interface of the present application may be defined in a manner different from the conventional method.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the appended patent application.

110:傳統框架交換器 111,121,CPi:CP 112,122:LC 120,200,600,610:DDC系統 201:管理交換器 202:GM 300:分散式同步系統 710,720:RJ45介面腳位表 MM:管理裝置 D1~DN:同步裝置 IM,I1~IN:網路輸入介面 OM,O1~ON:網路輸出介面 P1:PTP封包

Figure 02_image019
~
Figure 02_image059
:同步信號
Figure 02_image021
~
Figure 02_image067
:控制信號
Figure 02_image011
~
Figure 02_image065
:1PPS信號
Figure 02_image009
~
Figure 02_image061
:頻率信號
Figure 02_image013
~
Figure 02_image063
:日時間資訊 DPi:資料平面 Eth:10G介面 SNi:同步模組 Pi,MP:處理器 LLi,ML:數位鎖相迴路 DSi:差動至單端橋接器 SDi:單端至差動橋接器 DSi1,SDi1:RS422埠 DSi2,SDi2:UART PM:處理模組 S411,S412,S421~S423,S431~S433:步驟110: Traditional frame switch 111, 121, CPi: CP 112, 122: LC 120, 200, 600, 610: DDC system 201: Management switch 202: GM 300: Distributed synchronization system 710, 720: RJ45 interface pin table MM: Management device D1~DN: Synchronization device IM ,I1~IN: network input interface OM, O1~ON: network output interface P1: PTP packet
Figure 02_image019
~
Figure 02_image059
: sync signal
Figure 02_image021
~
Figure 02_image067
:control signal
Figure 02_image011
~
Figure 02_image065
:1PPS signal
Figure 02_image009
~
Figure 02_image061
: frequency signal
Figure 02_image013
~
Figure 02_image063
: Date Time Information DPi: Data Plane Eth: 10G Interface SNi: Synchronous Module Pi, MP: Processor LLi, ML: Digital Phase Locked Loop DSi: Differential to Single-Ended Bridge SDi: Single-Ended to Differential Bridge DSi1 , SDi1: RS422 port DSi2, SDi2: UART PM: Processing module S411, S412, S421~S423, S431~S433: Step

圖1A是傳統框架交換器的示意圖。 圖1B是分散式分解框架系統的示意圖。 圖2是設置有管理交換器的DDC系統的示意圖。 圖3是依據本發明之一實施例繪示的分散式同步系統示意圖。 圖4A是依據本發明第一實施例繪示的分散式同步方法流程圖。 圖4B是依據本發明第二實施例繪示的分散式同步方法流程圖。 圖4C是依據本發明第三實施例繪示的分散式同步方法流程圖。 圖4D是依據本發明第四實施例繪示的分散式同步方法流程圖。 圖5是依據本發明之一實施例繪示的同步裝置的資料平面及控制平面的示意圖。 圖6是依據圖2及圖3繪示的技術比較圖。 圖7是依據本發明之一實施例繪示的習知RJ45介面腳位表與本案RJ45介面腳位表的比較圖。 圖8是依據本發明之一實施例繪示的同步裝置的功能方塊圖。 圖9A是依據本發明之一實施例繪示的管理裝置的功能方塊圖。 圖9B是依據圖9A繪示的管理裝置的功能方塊圖。Figure 1A is a schematic diagram of a conventional frame switch. Figure 1B is a schematic diagram of a decentralized decomposition framework system. Figure 2 is a schematic diagram of a DDC system provided with a management switch. FIG. 3 is a schematic diagram of a distributed synchronization system according to an embodiment of the present invention. FIG. 4A is a flowchart of a distributed synchronization method according to the first embodiment of the present invention. FIG. 4B is a flowchart of a distributed synchronization method according to the second embodiment of the present invention. FIG. 4C is a flowchart of a distributed synchronization method according to the third embodiment of the present invention. FIG. 4D is a flowchart of a distributed synchronization method according to the fourth embodiment of the present invention. 5 is a schematic diagram of a data plane and a control plane of a synchronization apparatus according to an embodiment of the present invention. FIG. 6 is a technical comparison diagram according to FIGS. 2 and 3 . FIG. 7 is a comparison diagram of a conventional RJ45 interface pin table according to an embodiment of the present invention and the RJ45 interface pin table of the present application. FIG. 8 is a functional block diagram of a synchronization apparatus according to an embodiment of the present invention. FIG. 9A is a functional block diagram of a management device according to an embodiment of the present invention. FIG. 9B is a functional block diagram of the management device shown in FIG. 9A .

710，720:RJ45介面腳位表710, 720: RJ45 interface pin table

Claims (13)

一種分散式同步系統，其包括彼此串接的多個同步裝置，其中該些同步裝置中的第i個同步裝置包括：一網路輸入介面，其包括：多個第一輸入腳位，其用以從該些同步裝置中的第i-1個同步裝置接收f i-1，其中1<i
Figure 109123927-A0305-02-0028-1
N，N為該些同步裝置的總數，f i-1為所述第i-1個同步裝置產生的頻率信號；多個第二輸入腳位，其用以從所述第i-1個同步裝置接收一控制信號，其中該控制信號要求所述第i個同步裝置同步於所述第i-1個同步裝置；多個1秒脈衝(pulse per second，PPS)信號輸入腳位，其用以從所述第i-1個同步裝置接收1PPS i-1，其中1PPS i-1為所述第i-1個同步裝置產生的1PPS信號；多個日時間信號輸入腳位，其用以從所述第i-1個同步裝置接收ToD i-1，其中ToD i-1為所述第i-1個同步裝置產生的日時間資訊；一網路輸出介面；以及一同步模組，其耦接於該網路輸入介面及該網路輸出介面之間，並經配置以：基於該控制信號、1PPS i-1、f i-1、ToD i-1執行與所述第i-1個同步裝置的一同步操作，並相應地產生另一同步信號及另一控制信號；以及 透過該網路輸出介面發送所述另一同步信號及所述另一控制信號。 A distributed synchronization system, which includes a plurality of synchronization devices connected in series, wherein the i-th synchronization device among the synchronization devices includes: a network input interface, which includes: a plurality of first input pins, which are used for to receive f i -1 from the i-1 th sync device among the sync devices, where 1 < i
Figure 109123927-A0305-02-0028-1
N , N is the total number of these synchronizing devices, f i -1 is the frequency signal generated by the i-1 th synchronizing device; a plurality of second input pins are used to synchronize from the i-1 th synchronizing device The device receives a control signal, wherein the control signal requires the i-th synchronization device to be synchronized with the i-1-th synchronization device; a plurality of 1-second pulse (pulse per second, PPS) signal input pins are used for Receive 1 PPS i -1 from the i-1 th synchronizing device, wherein 1 PPS i -1 is the 1 PPS signal generated by the i-1 th synchronizing device; a plurality of time-of-day signal input pins are used for Receive ToD i -1 from the i-1 th synchronizing device, wherein ToD i -1 is the time of day information generated by the i-1 th synchronizing device; a network output interface; and a synchronization module, which is coupled between the network input interface and the network output interface, and is configured to: based on the control signal, 1 PPS i -1 , f i -1 , ToD i -1 to execute and the i-1th A synchronizing operation of a synchronizing device, and correspondingly generating another synchronizing signal and another control signal; and sending the other synchronizing signal and the other control signal through the network output interface. 如請求項1所述的分散式同步系統，其中該網路輸出介面包括：多個第一輸出腳位，其用以發送f i ，其中f i 為所述第i個同步裝置產生的頻率信號；多個第二輸出腳位，其用以發送所述另一控制信號；多個1PPS信號輸出腳位，其用以輸出1PPS i ，其中1PPS i 為所述第i個同步裝置產生的1PPS信號；多個日時間信號輸出腳位，其用以輸出ToD i ，其中ToD i 為所述第i個同步裝置產生的日時間資訊。 The distributed synchronization system according to claim 1, wherein the network output interface comprises: a plurality of first output pins for sending f i , wherein f i is a frequency signal generated by the i-th synchronization device A plurality of second output pins, which are used to send the other control signal; A plurality of 1PPS signal output pins, which are used to output 1 PPS i , wherein 1 PPS i is generated by the i-th synchronizing device 1PPS signal; a plurality of time-of-day signal output pins, which are used to output ToD i , where ToD i is the time-of-day information generated by the i-th synchronization device. 如請求項1所述的分散式同步系統，其中該網路輸入介面及該網路輸出介面分別為一RJ45輸入介面及一RJ45輸出介面。 The distributed synchronization system of claim 1, wherein the network input interface and the network output interface are an RJ45 input interface and an RJ45 output interface, respectively. 如請求項1所述的分散式同步系統，其中1PPS i-1、f i-1、ToD i-1及該控制信號各別為一差動信號，且該同步模組包括：一差動至單端橋接器，其耦接於該網路輸入介面，並用於將f i-1、1PPS i-1、該控制信號及ToD i-1分別轉換為對應的一第一單端信號、一第二單端信號、一第三單端信號及一第四單端信號；一數位鎖相迴路，其耦接於該差動至單端橋接器，並接收分別對應於f i-1、1PPS i-1的該第一單端信號及該第二單端信號； 一處理器，其耦接於該數位鎖相迴路及該差動至單端橋接器，並經配置以：控制該數位鎖相迴路基於該第一單端信號及該第二單端信號執行與所述第i-1個同步裝置的一頻率同步操作及一相位同步操作，並相應地產生一第五單端信號及一第六單端信號，其中該第五單端信號及該第六單端信號分別對應於該第一單端信號及該第二單端信號；從該差動至單端橋接器接收分別對應於該控制信號及ToD i-1的該第三單端信號及該第四單端信號，並基於該第三單端信號產生一第七單端信號；基於該第四單端信號執行與所述第i-1個同步裝置的一時間同步操作，以產生一第八單端信號；一單端至差動橋接器，其耦接於該處理器及該數位鎖相迴路，並經配置以：從該數位鎖相迴路接收該第五單端信號及該第六單端信號，並將其分別轉換為f i 、1PPS i ；從該處理器接收該第七單端信號及該第八單端信號，並將其分別轉換為所述另一控制信號及ToD i ；將f i 、1PPS i 、所述另一控制信號及ToD i 發送至該網路輸出介面。 The distributed synchronization system according to claim 1, wherein 1 PPS i -1 , f i -1 , ToD i -1 and the control signal are respectively a differential signal, and the synchronization module includes: a differential signal to a single-ended bridge, which is coupled to the network input interface and used to convert f i -1 , 1 PPS i -1 , the control signal and ToD i -1 into a corresponding first single-ended signal, a second single-ended signal, a third single-ended signal and a fourth single-ended signal; a digital phase-locked loop coupled to the differential-to-single-ended bridge, and receiving signals corresponding to f i -1 , 1 the first single-ended signal and the second single-ended signal of PPS i -1 ; a processor coupled to the digital phase-locked loop and the differential-to-single-ended bridge, and configured to: control the The digital phase-locked loop performs a frequency synchronization operation and a phase synchronization operation with the i-1 th synchronization device based on the first single-ended signal and the second single-ended signal, and correspondingly generates a fifth single-ended signal and a sixth single-ended signal, wherein the fifth single-ended signal and the sixth single-ended signal correspond to the first single-ended signal and the second single-ended signal, respectively; received from the differential-to-single-ended bridge, respectively The third single-ended signal and the fourth single-ended signal corresponding to the control signal and ToD i -1 , and a seventh single-ended signal is generated based on the third single-ended signal; based on the fourth single-ended signal, and a time synchronization operation of the i-1th synchronization device to generate an eighth single-ended signal; a single-ended-to-differential bridge coupled to the processor and the digital phase-locked loop, and configured To: receive the fifth single-ended signal and the sixth single-ended signal from the digital phase-locked loop, and convert them into f i and 1 PPS i respectively; receive the seventh single-ended signal and the sixth single-ended signal from the processor Eight single-ended signals are converted into the other control signal and ToD i respectively; fi , 1 PPS i , the other control signal and ToD i are sent to the network output interface. 如請求項4所述的分散式同步系統，其中該控制信號綁定於ToD i-1，且該差動至單端橋接器更包括： 一RS422埠，其耦接於該些第二腳位及該些日時間信號輸入腳位，並用於接收彼此綁定的該控制信號及ToD i-1；一通用非同步收發器，其耦接於該RS422埠及該處理器，並用於分離該控制信號及ToD i-1。 The distributed synchronization system of claim 4, wherein the control signal is bound to ToD i -1 , and the differential-to-single-ended bridge further comprises: an RS422 port coupled to the second pins and the input pins of the date and time signal, and used to receive the control signal and ToD i -1 bound to each other; a universal asynchronous transceiver, which is coupled to the RS422 port and the processor, and used to separate the control Signal and ToD i -1 . 一種分散式同步系統，其包括彼此串接的多個同步裝置，其中該些同步裝置中的第1個同步裝置包括：一網路輸入介面，其包括：多個第一輸入腳位，其用以從一管理裝置接收f 0，其中f 0為一管理裝置經解譯一精確時間協定封包而取得的一參考頻率信號；多個第二輸入腳位，其用以從該管理裝置接收一參考控制信號，其中該參考控制信號要求所述第1個同步裝置同步於該管理裝置；多個1秒脈衝(pulse per second，PPS)信號輸入腳位，其用以從該管理裝置接收1PPS 0，其中1PPS 0為該管理裝置經解譯該精確時間協定封包而取得的一參考1秒脈衝信號；多個日時間信號輸入腳位，其用以從該管理裝置接收ToD 0，其中ToD 0為該管理裝置經解譯該精確時間協定封包而取得的一參考日時間資訊；一網路輸出介面；以及 一同步模組，其耦接於該網路輸入介面及該網路輸出介面之間，並經配置以：基於該參考控制信號、1PPS 0、f 0、ToD 0執行與該管理裝置的一同步操作，並相應地產生一第一同步信號及一第一控制信號；以及透過該網路輸出介面發送該第一同步信號及該第一控制信號至該些同步裝置中的第2個同步裝置。 A distributed synchronization system, which includes a plurality of synchronization devices connected in series, wherein the first synchronization device in the synchronization devices includes: a network input interface, which includes: a plurality of first input pins, which are used for to receive f 0 from a management device, where f 0 is a reference frequency signal obtained by a management device by deciphering a precise time agreement packet; a plurality of second input pins are used for receiving a reference from the management device A control signal, wherein the reference control signal requires the first synchronization device to be synchronized with the management device; a plurality of 1-second pulse (pulse per second, PPS) signal input pins are used to receive 1 PPS 0 from the management device , wherein 1 PPS 0 is a reference 1-second pulse signal obtained by the management device by deciphering the PTP packet; a plurality of time-of-day signal input pins are used to receive ToD 0 from the management device, wherein ToD 0 a reference date and time information obtained by the management device by deciphering the precise time protocol packet; a network output interface; and a synchronization module coupled between the network input interface and the network output interface , and is configured to: perform a synchronization operation with the management device based on the reference control signal, 1 PPS 0 , f 0 , ToD 0 , and correspondingly generate a first synchronization signal and a first control signal; and through the The network output interface sends the first synchronization signal and the first control signal to a second synchronization device among the synchronization devices. 如請求項6所述的分散式同步系統，其中該網路輸出介面包括：多個第一輸出腳位，其用以發送f 1，其中f 1為所述第1個同步裝置產生的頻率信號；多個第二輸出腳位，其用以發送該第一控制信號；多個1PPS信號輸出腳位，其用以輸出1PPS 1，其中1PPS 1為所述第1個同步裝置產生的1PPS信號；多個日時間信號輸出腳位，其用以輸出ToD 1，其中ToD 1為所述第1個同步裝置產生的日時間資訊。 The distributed synchronization system of claim 6, wherein the network output interface comprises: a plurality of first output pins for sending f 1 , wherein f 1 is a frequency signal generated by the first synchronization device ; A plurality of second output pins for sending the first control signal; A plurality of 1PPS signal output pins for outputting 1 PPS 1 , wherein 1 PPS 1 is the 1PPS generated by the first synchronizing device Signal; a plurality of time-of-day signal output pins, which are used to output ToD 1 , where ToD 1 is the time-of-day information generated by the first synchronization device. 如請求項6所述的分散式同步系統，其中該網路輸入介面及該網路輸出介面分別為一RJ45輸入介面及一RJ45輸出介面。 The distributed synchronization system of claim 6, wherein the network input interface and the network output interface are an RJ45 input interface and an RJ45 output interface, respectively. 如請求項6所述的分散式同步系統，其中1PPS 0、f 0、ToD 0及該參考控制信號各別為一差動信號，且該同步模組包括： 一差動至單端橋接器，其耦接於該網路輸入介面，並用於將f 0、1PPS 0、該參考控制信號及ToD 0分別轉換為對應的一第一單端信號、一第二單端信號、一第三單端信號及一第四單端信號；一數位鎖相迴路，其耦接於該差動至單端橋接器，並接收分別對應於f 0、1PPS 0的該第一單端信號及該第二單端信號；一處理器，其耦接於該數位鎖相迴路及該差動至單端橋接器，並經配置以：控制該數位鎖相迴路基於該第一單端信號及該第二單端信號執行與該管理裝置的一頻率同步操作及一相位同步操作，並相應地產生一第五單端信號及一第六單端信號，其中該第五單端信號及該第六單端信號分別對應於該第一單端信號及該第二單端信號；從該差動至單端橋接器接收分別對應於該控制信號及ToD 0的該第三單端信號及該第四單端信號，並基於該第三單端信號產生一第七單端信號；基於該第四單端信號執行與該管理裝置的一時間同步操作，以產生一第八單端信號；一單端至差動橋接器，其耦接於該處理器及該數位鎖相迴路，並經配置以：從該數位鎖相迴路接收該第五單端信號及該第六單端信號，並將其分別轉換為f 1、1PPS 1； 從該處理器接收該第七單端信號及該第八單端信號，並將其分別轉換為該第一控制信號及ToD 1；將f 1、1PPS 1、該第一控制信號及ToD 1發送至該網路輸出介面。 The distributed synchronization system of claim 6, wherein 1 PPS 0 , f 0 , ToD 0 and the reference control signal are respectively a differential signal, and the synchronization module comprises: a differential-to-single-ended bridge , which is coupled to the network input interface and is used to convert f 0 , 1 PPS 0 , the reference control signal and ToD 0 into a corresponding first single-ended signal, a second single-ended signal, a third single-ended signal and a fourth single-ended signal; a digital phase-locked loop coupled to the differential-to-single-ended bridge and receiving the first single-ended signal and the first single-ended signal corresponding to f 0 and 1 PPS 0 respectively a second single-ended signal; a processor coupled to the digital phase-locked loop and the differential-to-single-ended bridge, and configured to: control the digital phase-locked loop based on the first single-ended signal and the first single-ended signal The two single-ended signals perform a frequency synchronization operation and a phase synchronization operation with the management device, and correspondingly generate a fifth single-ended signal and a sixth single-ended signal, wherein the fifth single-ended signal and the sixth single-ended signal The terminal signal corresponds to the first single-ended signal and the second single-ended signal respectively; the third single-ended signal and the fourth single-ended signal corresponding to the control signal and ToD 0 are received from the differential-to-single-ended bridge, respectively. terminal signal, and generate a seventh single-ended signal based on the third single-ended signal; perform a time synchronization operation with the management device based on the fourth single-ended signal to generate an eighth single-ended signal; a single-ended to a differential bridge coupled to the processor and the digital phase-locked loop and configured to: receive the fifth single-ended signal and the sixth single-ended signal from the digital phase-locked loop and convert them respectively are f 1 , 1 PPS 1 ; receive the seventh single-ended signal and the eighth single-ended signal from the processor, and convert them into the first control signal and ToD 1 respectively; convert f 1 , 1 PPS 1 , The first control signal and ToD 1 are sent to the network output interface. 如請求項9所述的分散式同步系統，其中該參考控制信號綁定於ToD 0，且該差動至單端橋接器更包括：一RS422埠，其耦接於該些第二輸入腳位及該些日時間信號輸入腳位，並用於接收彼此綁定的該參考控制信號及ToD 0；一通用非同步收發器，其耦接於該RS422埠及該處理器，並用於分離該參考控制信號及ToD 0。 The distributed synchronization system of claim 9, wherein the reference control signal is bound to ToD 0 , and the differential-to-single-ended bridge further comprises: an RS422 port coupled to the second input pins and the time-of-day signal input pins for receiving the reference control signal and ToD 0 bound to each other; a universal asynchronous transceiver coupled to the RS422 port and the processor for separating the reference control signal and ToD 0 . 一種分散式同步系統，其包括一管理裝置，該管理裝置包括：一處理模組，其經配置以：提供一參考同步信號及一參考控制信號，其中該參考同步信號包括1PPS 0、f 0、ToD 0，1PPS 0為一參考1PPS信號，f 0為一參考頻率信號，ToD 0為一參考日時間資訊，且該參考控制信號要求彼此串接的多個同步裝置中的第1個同步裝置同步於該管理裝置，其中1PPS 0、f 0、ToD 0及該參考控制信號各別為差動信號；一網路輸出介面，其為包括8個腳位的RJ45輸出介面，且耦接於該處理模組並接收該參考同步信號及該參考控制信號，其中該網路輸出介面包括： 多個第一輸出腳位，其用以發送f 0至所述第1個同步裝置，其中該些第一輸出腳位為所述8個腳位中的第1個腳位及第2個腳位；多個第二輸出腳位，其用以發送該參考控制信號至所述第1個同步裝置，其中該些第二輸出腳位為所述8個腳位中的第4個腳位及第5個腳位；多個1秒脈衝(pulse per second，PPS)信號輸出腳位，其用以發送1PPS 0至所述第1個同步裝置，其中該些1PPS信號輸出腳位為所述8個腳位中的第3個腳位及第6個腳位；多個日時間信號輸出腳位，其用以發送ToD 0至所述第1個同步裝置，其中該些日時間信號輸出腳位為所述8個腳位中的第7個腳位及第8個腳位。 A distributed synchronization system includes a management device, the management device includes: a processing module configured to: provide a reference synchronization signal and a reference control signal, wherein the reference synchronization signal includes 1 PPS 0 , f 0 , ToD 0 , 1 PPS 0 is a reference 1PPS signal, f 0 is a reference frequency signal, ToD 0 is a reference date and time information, and the reference control signal requires the first synchronization among multiple synchronization devices connected in series with each other The device is synchronized with the management device, wherein 1 PPS 0 , f 0 , ToD 0 and the reference control signal are differential signals respectively; a network output interface is an RJ45 output interface including 8 pins and is coupled to The processing module receives the reference synchronization signal and the reference control signal, wherein the network output interface includes: a plurality of first output pins for sending f 0 to the first synchronization device, wherein the Some first output pins are the first pin and the second pin among the 8 pins; a plurality of second output pins are used to send the reference control signal to the first synchronization The device, wherein the second output pins are the 4th pin and the 5th pin among the 8 pins; a plurality of 1-second pulse (pulse per second, PPS) signal output pins are used for To send 1 PPS 0 to the first synchronization device, wherein the 1PPS signal output pins are the 3rd pin and the 6th pin of the 8 pins; a plurality of time-of-day signal output pins bit, which is used to send ToD 0 to the first synchronization device, wherein the output pins of the time-of-day signal are the seventh pin and the eighth pin of the eight pins. 如請求項11所述的分散式同步系統，其中該管理裝置更包括一網路輸入介面，其包括：多個第一輸入腳位，其用以從該些同步裝置中的第N個同步裝置接收f N ，其中N為該些同步裝置的總數，f N 為所述第N個同步裝置產生的頻率信號；多個第二輸入腳位，其用以從所述第N個同步裝置接收一控制信號，其中該控制信號通知該管理裝置該些同步裝置已完成同步；多個1PPS信號輸入腳位，其用以從所述第N個同步裝置接收1PPS N ，其中1PPS N 為所述第N個同步裝置產生的1PPS信號； 多個日時間信號輸入腳位，其用以從所述第N個同步裝置接收ToD N ，其中ToD N 為所述第N個同步裝置產生的日時間資訊。 The distributed synchronization system of claim 11, wherein the management device further comprises a network input interface, comprising: a plurality of first input pins, which are used for synchronizing from the Nth synchronization device among the synchronization devices receiving f N , where N is the total number of the synchronizing devices, f N is the frequency signal generated by the Nth synchronizing device; a plurality of second input pins are used to receive a signal from the Nth synchronizing device A control signal, wherein the control signal informs the management device that the synchronization devices have completed synchronization; a plurality of 1PPS signal input pins, which are used to receive 1PPS N from the Nth synchronization device, where 1PPS N is the 1PPS signal generated by the Nth synchronizing device; a plurality of time-of-day signal input pins for receiving ToDN from the Nth synchronizing device, where ToDN is the time-of-day information generated by the Nth synchronizing device . 如請求項12所述的分散式同步系統，其中該網路輸入介面為一RJ45輸入介面。 The distributed synchronization system of claim 12, wherein the network input interface is an RJ45 input interface.
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TW201210381A (en) * 2010-08-27 2012-03-01 Univ Nat Taiwan Device, system, and method for time synchronization
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TW201827851A (en) * 2016-11-29 2018-08-01 日商因艾伯爾股份有限公司 Time synchronization system and transmission device
CN207835469U (en) * 2018-05-29 2018-09-07 云南电网有限责任公司曲靖供电局 Clock system
TWM612938U (en) * 2020-07-15 2021-06-11 優達科技股份有限公司 Distributed synchronization system

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