TWI769050B - Semiconductor structure and method for manufacturing the same - Google Patents

Abstract

A semiconductor structure and a method for manufacturing a semiconductor are provided. The semiconductor structure includes a channel pillar, a dielectric layer formed on the channel pillar, a via formed in the dielectric layer and electrically connected to the channel pillar, and a spacer formed between the dielectric layer and the via.

Description

Semiconductor structure and method of making the same

The present disclosure relates to a semiconductor structure and a manufacturing method thereof, and more particularly, to a semiconductor structure including spacer elements formed on sidewalls of through-hole elements and a manufacturing method thereof.

Etching techniques have been widely used in semiconductor manufacturing. For example, in order to form ohmic contacts between the pads of the channel pillars and the via elements, the via elements may be formed on the channel pillars by an etching process. However, an over-etching problem may occur in the etching process used to form the through-hole device, thereby forming a leakage path in the semiconductor structure and affecting the insulation properties of the wires in the semiconductor structure.

Therefore, there is a need to provide a semiconductor structure and a method for fabricating the same, which can avoid the generation of leakage paths, and at the same time ensure good ohmic contact between the channel column and the via element, so as to improve the electrical performance of the semiconductor structure.

The present disclosure relates to semiconductor structures and methods of fabricating the same.

According to one aspect of the present disclosure, a method of fabricating a semiconductor structure is provided. A method of fabricating a semiconductor structure includes: providing a channel post; forming a dielectric layer on the channel post; forming spacer elements in the dielectric layer; and forming a via element in the dielectric layer, the via element being electrically connected to the channel post, The spacer elements are interposed between the dielectric layer and the via elements.

According to another aspect of the present disclosure, a semiconductor structure is provided. The semiconductor structure includes a channel pillar, a dielectric layer formed on the channel pillar, a via element formed in the dielectric layer and electrically connected to the via pillar, and a spacer element formed between the dielectric layer and the via element.

In order to have a better understanding of the above and other aspects of the present invention, the following embodiments are given and described in detail in conjunction with the accompanying drawings as follows.

10: Semiconductor structure

101: Substrate

102: Insulation layer

103: Conductive layer

104: Memory Layer

105: Channel Layer

105S: Sidewall

106: Insulation column

106S: Sidewall

107: Pad

107S: Sidewall

110: Stacked Structure

111: Channel column

111S:Sidewall

111U: Upper surface

112: Air gap

115: Dielectric film

116: Conductive film

116S: Sidewall

117: Dielectric layer

118: Opening

120: Spacer element

121: Barrier layer

122: Through-hole components

D1, D2: direction

T1: Thickness

1 to 5 are schematic cross-sectional views illustrating a method of fabricating a semiconductor structure according to an embodiment of the present disclosure.

In the embodiments of the present disclosure, a semiconductor structure and a method of fabricating the semiconductor structure are provided. According to an embodiment of the manufacturing method, a semiconductor structure can be obtained, for example, including a spacer element (spacer) formed on the sidewall of a via element (via). The semiconductor structure, thereby avoiding the generation of a leakage path between the through-hole element and the conductive layer in the semiconductor structure, and maintaining the insulation between the through-hole element and the conductive layer in the semiconductor structure, so as to improve the electrical performance of the semiconductor structure.

In practical applications, the embodiments of the present disclosure may be implemented in various semiconductor structures. For example, the embodiment may be applied to a three-dimensional vertical channel type memory device or a three-dimensional integrated circuit (IC) structure with a high aspect ratio, but the present disclosure is not limited to this application. Relevant embodiments are provided below, and the memory device and the manufacturing method thereof provided by the present disclosure are described in detail in conjunction with the drawings.

Meanwhile, it should be noted that the descriptions in the embodiments, such as the detailed structure, the steps of the manufacturing method and the material application, etc., are for illustrative purposes only, and the scope of protection of the present disclosure is not limited to the above-described aspects. Those skilled in the relevant art can make changes and modifications to the structures and manufacturing methods of the embodiments to meet the needs of practical applications without departing from the spirit and scope of the present disclosure. Therefore, other implementation aspects not proposed in the present disclosure may also be applicable. Furthermore, the drawings are simplified for the purpose of clearly explaining the contents of the embodiments, and the dimension ratios in the drawings are not drawn according to the actual product scale. Therefore, the description and the drawings are only used to describe the embodiments, rather than to limit the protection scope of the present disclosure. In the following, the same/similar symbols are used to represent the same/similar elements for description.

In addition, the term "electrically connected" in the description and the scope of the patent application may mean that a plurality of elements form ohmic contacts, that current flows between the plurality of elements, or that the plurality of elements are operatively related. Operational associativity can be e.g. One element is used to drive another element, but current may not flow directly between these two elements.

1-5 are cross-sectional views illustrating a method of fabricating a semiconductor structure according to an embodiment. The manufacturing method of the semiconductor structure includes the following steps: Referring to FIG. 1 , a substrate 101 is provided. The substrate 101 may include doped or undoped semiconductor materials, such as p-doped, n-doped or undoped silicon. However, the present invention is not limited to this. In another embodiment, the substrate 101 may use other materials, such as dielectric materials or conductive materials. The stacked structure 110 is formed on the substrate 101 . The stacked structure 110 may include a plurality of insulating layers 102 and a plurality of conductive layers 103 that are alternately stacked along the first direction D1. The first direction D1 may be the normal direction of the upper surface of the substrate 101 . The plurality of conductive layers 103 isolate the plurality of insulating layers 102 from each other. The insulating layer 102 may include an insulating material including an oxide. In one embodiment, the insulating layer 102 may include silicon oxide. The conductive layer 103 may include a conductive material such as metal. In one embodiment, the conductive layer 103 may include tungsten.

Channel pillars 111 are provided in the stacked structure 110 . In this embodiment, the channel pillars 111 are formed on the substrate 101 through the stacked structure 110 extending along the first direction D1. The channel pillars 111 may include the memory layer 104 , the channel layer 105 , the insulating pillars 106 and the pads 107 . Pads 107 may be formed on the insulating pillars 106 . The channel layer 105 may be formed on the sidewalls 106S of the insulating pillars 106 and on the sidewalls 107S of the pads 107 . The memory layer 104 may be formed on the sidewalls 105S of the channel layer 105 . In this embodiment, the memory layer 104 may have a tubular shape and surround the channel layer 105, the channel layer 105 It may have a tubular shape and surround the insulating pillars 106 and the pads 107 , and the channel layer 105 is interposed between the memory layer 104 and the insulating pillars 106 and/or between the memory layer 104 and the pads 107 .

The memory layer 104 may include a multilayer structure known in the field of memory technology, such as ONO (oxide-nitride-oxide) structure, ONONO (oxide-nitride-oxide-nitride-oxide) ) structure, ONONONO (oxide-nitride-oxide-nitride-oxide-nitride-oxide) structure, SONOS (silicon-silicon oxide-silicon nitride-silicon oxide-silicon) structure, BE-SONOS ( Band gap silicon-silicon oxide-silicon nitride-silicon oxide-silicon) structure, TANOS (tantalum nitride-alumina-silicon nitride-silicon oxide-silicon) structure, MA BE-SONOS (metal-high dielectric constant) Material energy band gap silicon-silicon oxide-silicon nitride-silicon oxide-silicon) structure and its combination. The channel layer 105 may comprise doped or undoped semiconductor material. In one embodiment, the channel layer 105 may comprise polysilicon, such as doped polysilicon or undoped polysilicon. The insulating pillars 106 may include an insulating material including an oxide. In one embodiment, the insulating pillars 106 may comprise silicon oxide. The pads 107 may comprise a semiconductor material, such as a silicide, a doped semiconductor material, or an undoped semiconductor material. In one embodiment, the pads 107 may comprise polysilicon, such as doped polysilicon or undoped polysilicon. The pads 107 can be electrically connected to the channel layer 105 .

In one embodiment, the conductive film 116 is provided in the stacked structure 110 . The conductive film 116 extends through the stacked structure 110 along the first direction D1 and is formed on the substrate 101 . The dielectric film 115 may be formed on the sidewalls 116S of the conductive film 116 and disposed between the conductive film 116 and the stacked structure 110 . In one embodiment, the lead The electrical film 116 may include an air gap 112 formed inside the conductive film 116 . The conductive film 116 may comprise polysilicon, metal, or other suitable conductive materials. In one embodiment, the conductive film 116 may include tungsten. The dielectric film 115 may include a dielectric material such as silicon oxide. Next, a dielectric layer 117 may be formed on the stack structure 110 and the channel pillars 111, for example, by a deposition process. The dielectric layer 117 may include oxide, such as silicon oxide.

Please refer to Figure 2. A plurality of openings 118 are formed in the dielectric layer 117 . For example, the dielectric layer 117 may be patterned by an exposure photolithography process to form the openings 118 . A plurality of openings 118 extend downward through the dielectric layer 117 along the first direction D1, and extend to the top insulating layer 102 in the stacked structure 110 to expose the upper surfaces 111U of the channel pillars 111, respectively. In one embodiment, the etching process in the exposure lithography process for forming the openings 118 does not stop at the upper surface 111U of the channel column 111, and the etching process continues after exposing the upper surface 111U of the channel column 111, so that part of the upper surface 111U is exposed. The memory layer 104 is removed, and the at least one conductive layer 103 in the stack structure 110 is exposed in the opening 118 . In this embodiment, as shown in FIG. 2 , the opening 118 makes the upper surface 111U of the channel column 111 , the sidewall 111S of the channel column 111 (or can be understood as the memory layer 104 ), and the uppermost layer of the plurality of conductive layers 103 . The sidewalls of the conductive layer 103 are exposed.

Please refer to Figure 3. Next, spacer elements 120 are formed in the dielectric layer 117 . Specifically, the spacer elements 120 are formed on the inner sidewalls and bottom surfaces of the openings 118, for example, by a deposition process. Spacer elements 120 may include oxides, such as silicon oxide. In one embodiment, the spacer element 120 is not limited to the profile as shown, but may include spacers deposited on the inner sidewalls and bottom surface of the opening 118 . any possible outline. For example, the upper surface of the spacer element 120 may be a flat surface or a non-flat surface.

Please refer to Figure 4. Next, the portion of the spacer element 120 located on the upper surface 111U of the channel pillar 111 may be removed by an anisotropic etching process, leaving the portion of the spacer element 120 located on the inner sidewall of the opening 118 . Specifically, the spacer members 120 formed on the upper surfaces 111U of the channel pillars 111 are removed to expose the pads 107 . In one embodiment, as shown in FIG. 4 , after the anisotropic etching process, a part of the spacer element 120 is disposed between the channel column 111 and the conductive layer 103 of the stack structure 110 ; or, it can also be understood as a spacer element A part of 120 is formed on the sidewall 111S of the channel pillar 111 .

Please refer to Figure 5. Next, a barrier layer 121 may be formed on the sidewalls of the spacer elements 120 and the upper surfaces 111U of the channel pillars 111 through a deposition process. The barrier layer 121 may include a conductive material, such as metal. In one embodiment, the barrier layer 121 may include titanium (titanium; Ti) or titanium nitride (titanium nitride; TiN). After the barrier layer 121 is formed, through-hole elements 122 can be formed on the inner sidewalls of the barrier layer 121 by a deposition process to fill the openings 118 . Via element 122 may comprise a conductive material such as metal. In one embodiment, the via element 122 may comprise tungsten. The spacer element 120 may be interposed between the dielectric layer 107 and the via element 122 , the barrier layer 121 may be located between the spacer element 120 and the via element 122 , and the via element 122 may be electrically connected to the channel through the barrier layer 121 Pad 107 of post 111 . In this embodiment, the barrier layer 121 directly contacts the pads 107 of the channel pillars 111 , but the present disclosure is not limited thereto.

The semiconductor structure 10 can be obtained by the manufacturing method described above with reference to FIGS. 1 to 5 . As shown in FIG. 5 , the semiconductor structure 10 includes a substrate 101 , a stacked structure 110 disposed on the substrate 101 and including a plurality of conductive layers 103 and a plurality of insulating layers 102 staggered and stacked along the first direction D1 , along the first direction D1 . The direction D1 extends through the channel pillars 111 of the stacked structure 110 , the dielectric layer 117 formed on the channel pillars 111 and the stacked structure 110 , the via elements 122 formed in the dielectric layer 117 and electrically connected to the channel pillars 111 , and Spacer elements 120 are formed between the dielectric layer 117 and the via elements 122 .

The spacer element 120 may be used to isolate the via element 122 from the conductive layer 103 in the stack structure 110 . The spacer element 120 may have a thickness T1 between 10-500 angstroms (angstrom; Å) in the second direction D2, which is orthogonal to the second direction D2. Specifically, as shown in FIG. 5 , a portion of the spacer element 120 is formed on the conductive layer 103 exposed by the opening 118 in the channel column 111 and the plurality of conductive layers 103 (in this embodiment, it can also be understood as a plurality of conductive layers 103 ) between the uppermost conductive layer 103 ) to prevent the via element 122 from contacting the conductive layer 103 exposed by the opening 118 to cause a leakage path between the via element 122 and the conductive layer 103 . The spacer element 120 can electrically insulate the via element 122 from the conductive layer 103 exposed by the opening 118 .

In one embodiment, the thickness T1 of the spacer element 120 in the second direction D2 may be 100 angstroms. When the thickness T1 of the spacer element 120 in the second direction D2 is less than 10 angstroms, the insulation between the conductive layer 103 and the via element 122 in the stacked structure 110 is insufficient, and it is difficult to avoid the generation of leakage paths. in the spacer When the thickness T1 of the member 120 in the second direction D2 is greater than 500 angstroms, the conductive path between the via element 122 and the pad 107 may be blinded and a reliable conductive path cannot be provided.

The semiconductor structure 10 may also include a barrier layer 121 formed between the via elements 122 and the spacer elements 120 . The barrier layer 121 may be on the sidewall of the via element 122 and surround the via element 122 . The semiconductor structure 10 may further include a conductive film 116 extending through the stacked structure 110 along the first direction D1 , and a dielectric film 115 interposed between the conductive film 116 and the stacked structure 110 . In this embodiment, the semiconductor structure 10 is illustrated as including two channel pillars 111 and two conductive films 116 , however, the present disclosure is not limited thereto, and the semiconductor structure may include more or less channel pillars 111 and more or more less conductive film 116.

In one embodiment, the semiconductor structure 10 may be applied to a three-dimensional memory device having a vertical channel structure inverse and gate (NAND) type, and the semiconductor structure 10 may include a plurality of memory cells defined in the memory layer 104 . More specifically, memory cells may be defined in the memory layer 104 where each of the plurality of conductive layers 103 is interleaved with the channel layers 105 of the channel pillars 111 . The conductive layer 103 can be used as a word line (WL), and the conductive film 116 can be used as a common source line (CSL). In one embodiment, the semiconductor structure 10 may be applied to a gate-all-around type memory device.

In the semiconductor structure 10 of the present disclosure, the insulating properties of the conductive layer 103 can be effectively ensured by disposing the spacer elements 120 , even if the through-hole elements 122 are not completely aligned with the channel pillars 111 or the over-etching problem occurs when the through-hole elements 122 are disposed, the sure Good ohmic contact between the via post 111 and the via element 122 is maintained, and a leakage path between the via element 122 and the conductive layer 103 is avoided, thereby improving the electrical performance of the semiconductor structure. For example, in the case where the channel pillars 111 are not perpendicular to the upper surface of the substrate 101 , the etching process for forming the via element 122 (eg, the etching process for forming the openings 118 ) may not stop at the channel due to the inclination of the channel pillars 111 On the upper surface of the pillar 111 , the etching process will continue toward the direction of the substrate 101 , thereby destroying the insulation of the conductive layer 103 in the stacked structure (or can be understood as over-etching). The present disclosure can effectively repair the insulation of the conductive layer 103 by disposing the spacer element 120 . Embodiments of the present disclosure can be integrated into existing semiconductor structure processes. In addition, when the semiconductor structure of the present disclosure is applied to a three-dimensional memory device, by disposing the spacer element 120, the generation of a leakage path between the word line and the bit line (BL) can be avoided, and the word line can be ensured and bit line insulation.

In a comparative example, the semiconductor structure does not include a spacer element formed between the dielectric layer and the via element, so that the over-etching problem that occurs during the formation of the opening can expose the conductive layer to the opening, so that the via element and the via element are exposed. /or the barrier layer may be formed on the conductive layer exposed by the opening, resulting in that the electrical connection cannot be established correctly, and an unexpected leakage path may be generated.

To sum up, although the present invention has been disclosed by the above embodiments, it is not intended to limit the present invention. Those skilled in the art to which the present invention pertains can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the appended patent application.

10: Semiconductor structure

101: Substrate

102: Insulation layer

103: Conductive layer

104: Memory Layer

105: Channel Layer

106: Insulation column

107: Pad

110: Stacked Structure

111: Channel column

111U: Upper surface

115: Dielectric film

116: Conductive film

117: Dielectric layer

118: Opening

120: Spacer element

121: Barrier layer

122: Through-hole components

D1, D2: direction

T1: Thickness

Claims (9)

A semiconductor structure, comprising: a stack structure including a plurality of conductive layers and a plurality of insulating layers stacked alternately; a channel column extending through the stack structure along a first direction; a dielectric layer formed on the channel column and formed on the stacked structure; a via element formed in the dielectric layer and electrically connected to the channel column; and a spacer element formed between the dielectric layer and the via element, the spacer Elements extend through the dielectric layer and into the stack, and the spacer elements are in contact with the conductive layer. The semiconductor structure of claim 1, wherein a portion of the spacer element is formed on a sidewall of the channel pillar. The semiconductor structure of claim 1, wherein the spacer element has a thickness between 10-500 angstroms in a second direction, the first direction being orthogonal to the second direction. The semiconductor structure of claim 1, wherein a portion of the spacer element is formed between the channel post and at least one of the conductive layers. The semiconductor structure of claim 1, wherein the spacer element comprises an oxide. A method of fabricating a semiconductor structure, comprising: providing a channel column; forming a dielectric layer on the channel column; forming a spacer element in the dielectric layer, comprising: forming an opening through the dielectric layer to expose the via post; and forming the spacer element on a sidewall of the opening; and forming a via element in the dielectric layer electrically connected to the via element A channel column, the spacer element is interposed between the dielectric layer and the through hole element. The method of claim 6, further comprising: providing a stack structure through which the channel column extends along a first direction, wherein a portion of the spacer element is formed between the stack structure and the channel column, The spacer element has a thickness of between 10-500 angstroms in a second direction, the first direction being orthogonal to the second direction. The method of claim 6, wherein the opening exposes an upper surface of the channel column and a side wall of the channel column. The method of claim 6, wherein the step of forming the spacer element in the dielectric layer further comprises: removing a portion of the spacer element to expose a pad of the channel post.

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