TWI768563B - Printed wiring board, memory system, and manufacturing method of printed wiring board - Google Patents

Abstract

Embodiments provide a printed wiring board, a memory system, and a manufacturing method of the printed wiring board capable of improving transmission characteristics. The printed wiring board of the embodiment includes a first insulating portion, a second insulating portion, a first conductive portion, and a second conductive portion. The said 2nd insulating part is located in the outer vicinity of the said printed wiring board rather than the said 1st insulating part in the thickness direction of a printed wiring board. The first conductive portion is located between the first insulating portion and the second insulating portion, and includes a first conductive material. The second conductive portion includes a first portion located between the first insulating portion and the first conductive portion, in contact with the first conductive portion, and extending along the first conductive portion, and includes The resistivity of the second conductive material is smaller than that of the first conductive material.

Description

Printed wiring board, memory system, and manufacturing method of printed wiring board

Embodiments of the present invention relate to a printed wiring board, a memory system, and a method for manufacturing the printed wiring board. [Connected Application] This application enjoys the priority of the basic application with Japanese Patent Application No. 2020-144942 (filing date: August 28, 2020). This application includes all the contents of the basic application by referring to the basic application.

A printed wiring board provided with a wiring pattern formed of a copper material is known. It is expected that the transmission characteristics of printed wiring boards will be improved.

Embodiments of the present invention provide a printed wiring board, a memory system, and a manufacturing method of the printed wiring board capable of improving transmission characteristics. The printed wiring board of the embodiment includes a first insulating portion, a second insulating portion, a first conductive portion, and a second conductive portion. The said 2nd insulating part is located in the outer vicinity of the said printed wiring board rather than the said 1st insulating part in the thickness direction of the said printed wiring board. The first conductive portion is located between the first insulating portion and the second insulating portion, and includes a first conductive material. The second conductive portion includes a first portion located between the first insulating portion and the first conductive portion, in contact with the first conductive portion, and extending along the first conductive portion, and includes The resistivity of the second conductive material is smaller than that of the first conductive material.

如同圖7中所示一般，可以得知，在作為配線材料而使用有銀的情況時，相對於16GHz之訊號的集膚深度d係為0.5μm程度，相對於32GHz之訊號的集膚深度d係為0.35μm程度。亦即是，若是設置0.5μm程度或者是0.35μm程度之厚度的表層部62，則係能夠使起因於集膚效應而集中於配線60之表面附近的電流之大部分在表層部62中流動。 ＜6.優點＞ 在訊號之高速化更為進展的情況時，集膚效應之影響係會為更為增大的可能性。因此，在本實施形態中，印刷配線板5之配線60，係具備有包含第1導電材料M1之本體部61、和包含電阻率為較第1導電材料M1而更小之第2導電材料M2之表層部62。本體部61，係位置在第2絕緣基材20與阻焊劑層30之間。表層部62，係包含有位置在第2絕緣基材20與本體部61之間之第1部分62a。若依據此種構成，則起因於集膚效應而在配線60之表面附近流動的電流之至少一部分，係能夠通過藉由電阻率為小的第2導電材料M2所形成之表層部62而流動。藉由此，係能夠謀求傳輸特性之提升(例如，傳輸之高速化及/或傳輸損失之降低)。 於此，係亦可考慮將配線全體以電阻率為小之第2導電材料M2來形成。然而，電阻率相對性而言為小之第2導電材料M2(例如銀)，多係相較於電阻率相對性而言為大之第1導電材料M1(例如銅)而為高價。因此，若是將配線全體以第2導電材料M2來形成，則印刷配線板之製造成本係會變高。另一方面，在本實施形態中，係將配線60之本體部61藉由第1導電材料M1來形成，並將起因於集膚效應而電流有所集中之配線60之表層部62藉由第2導電材料M2來形成。若依據此種構成，則係能夠對於印刷配線板5之製造成本的提高作抑制，並且亦謀求印刷配線板5之傳輸特性之提升。 在本實施形態中，配線60之表層部62之第1部分62a之Z方向之厚度T4a，係較配線60之本體部61之Z方向之厚度T3而更薄。若依據此種構成，則係能夠將第2導電材料M2之使用量減少，而能夠對於印刷配線板5之製造成本的提高更進一步作抑制。進而，在本實施形態中，配線60之表層部62之第1部分62a之Z方向之厚度T4a與第2部分62b之Z方向之厚度T4b的合計，係較配線60之本體部61之Z方向之厚度T3而更薄。若依據此種構成，則係能夠將第2導電材料M2之使用量更進一步減少。 在本實施形態中，在配線60中，係流動有15GHz以上之頻率的高速訊號。配線60之表層部62之厚度T2a、T2b、T2c、T2d，例如係為0.5μm以下。若依據此種構成，則係能夠使在配線60中流動的電流之大部分在配線60之表層部62中流動。藉由此，係能夠謀求傳輸特性之更進一步的提升。進而，若是配線60之表層部62之厚度T2a、T2b、T2c、T2d係為0.5μm程度，則就算是藉由無電解鍍敷也能夠較為容易地製造。 在本實施形態中，配線60之表層部62，係包含有位置在阻焊劑層30與配線60之本體部61之間之第2部分62b。若依據此種構成，則係能夠使更多的電流通過表層部62而流動。藉由此，係能夠謀求傳輸特性之更進一步的提升。 在本實施形態中，成為參考部(reference)並流動有返回電流之接地層40，亦係具備有藉由第1導電材料M1所形成之本體部41、和藉由電阻率相對性而言為小的第2導電材料M2所形成之表層部42。若依據此種構成，則返回電流亦係成為容易流動，而能夠謀求印刷配線板5之傳輸特性的更進一步之提升。 於此，第2導電材料M2(例如銀)，係會有相較於第1導電材料M1(例如銅)而容易發生離子遷移(導電材料離子化並進入至絕緣材料中之現象)或腐蝕的情形。然而，在本實施形態中，係在配線60之表層部62與第2絕緣基材20之間設置有有機被膜70之一部分。藉由此，就算是在將配線60之表層部62藉由第2導電材料M2來形成的情況時，亦能夠對起因於第2導電材料M2所導致的離子遷移或腐蝕作抑制。藉由此，係能夠使印刷配線板5之長期信賴性提升。 在將墊片80之表面藉由第2導電材料M2(例如銀)來形成的情況時，相較於將墊片80之表面藉由第1導電材料M1(例如銅)來形成的情況，電子零件EC之連接端子S與墊片80之間之接合性係能夠變高。因此，在將墊片80之表面藉由第2導電材料M2(例如銀)來形成的情況時，係會有能夠將助焊劑F省略或者是將墊片80之表面之粗化處理省略的情形。故而，係會有能夠謀求印刷配線板5之製造成本之降低的情況。 (變形例) 接著，針對第1實施形態之變形例作說明。本變形例，係亦能夠與後述之第2~第4實施形態作組合而實施之。 圖8，係為對於第1實施形態之變形例的印刷配線板5M作展示之剖面圖。 印刷配線板5M，係並未包含有上述之有機被膜50之間隙Sa、Sb以及有機被膜70之間隙Sc、Sd。亦即是，有機被膜50之第1部分50a，係分別與有機被膜50之第3部分50c以及第4部分50d有所連接。同樣的，有機被膜70之第1部分70a，係分別與有機被膜70之第3部分70c以及第4部分70d有所連接。 圖9以及圖10，係為對於變形例之印刷配線板5M之製造方法作展示之圖。在本變形例之製造方法中，係將包含有第2導電材料M2之金屬箔45(例如銀箔)作為種層，並利用有被稱作閃蝕刻(flash ecthing)或快蝕刻(quick etching)之半加成(Semi-additive)法，在此點上，係與上述之第1實施形態之印刷配線板5的製造方法相異。 在本變形例之製造方法中，如同圖9中之(a)所示一般，係形成有對於第1絕緣基材10而設置有第2導電層46之中間體M。中間體M，係可藉由與參照圖5中之(a)、(b)所作了說明的第1實施形態之印刷配線板5相同之工程來製造之。中間體M，係與第1實施形態相同的，包含有中介存在於第1絕緣基材10與第2導電層46之間之有機被膜部51。 接著，如同圖9中之(b)所示一般，在第2導電層46之上設置遮罩MK。遮罩MK，係在第2導電層46之表面上對應於接地層40之本體部41所被作設置的區域以外之區域地而被作設置。 接著，如同圖9中之(c)所示一般，在並未被設置有遮罩MK之區域處，形成包含第1導電材料M1之第1導電層47。本變形例之第1導電層47，係身為並不進行圖案加工地而成為接地層40之本體部41的導電層。第1導電層47(亦即是，接地層40之本體部41)，係藉由進行使用有第1導電材料M1之第1鍍敷處理，而被形成。第1鍍敷處理，係可採用電解鍍敷，亦可採用無電解鍍敷，但是，若是採用電解鍍敷，則係能夠合適地進行較厚的本體部41之成膜。 接著，如同圖9中之(d)所示一般，將遮罩MK去除。其結果，第1導電層47之第1面47b、第2面47c以及第3面47d係露出於外部。第1面47b，係身為在Z方向上而朝向與第2導電層46相反側之面。第2面47c，係身為朝向與第1面47b相異之方向之面。第3面47d，係身為在Y方向上而朝向與第2面47c相反側之面。 接著，如同圖10中之(e)所示一般，在第1導電層47(亦即是，接地層40之本體部41)之表面上、以及第2導電層46中之並未被第1導電層47所覆蓋之區域之表面上，形成包含第2導電材料M2之第3導電層48。第3導電層48，係藉由進行使用有第2導電材料M2之第2鍍敷處理，而被形成。第2鍍敷處理，例如係為無電解鍍敷。第3導電層48，係以與第1導電層47之第1面47b、第2面47c、第3面47d以及第2導電層46中之並未被第1導電層47所覆蓋之區域之表面相接的方式而被形成。在此過程中，第3導電層48之厚度，係較在完成品中之接地層40之表層部42之厚度而更厚。 接著，如同圖10中之(f)所示一般，藉由被稱作閃蝕刻或快蝕刻之半加成法，來將第2導電層46之不必要部分、第3導電層48之不必要部分以及有機被膜部51之不必要部分去除。具體而言，第2導電層46中之並未被第1導電層47或第3導電層48所覆蓋之部分(第2導電層46之不必要部分)、第3導電層48之被設置在第2導電層46之不必要部分之表面上的部分(第3絕緣基材48之不必要部分)以及有機被膜部51中之位置於第2導電層46之不必要部分與第1絕緣基材10之間之部分(有機被膜部51之不必要部分)，係被去除。在此過程中，第3導電層48中的被設置在第1導電層47之第1面47b、第2面47c以及第3面47d之表面上的部分之厚度係變薄。藉由此蝕刻之工程結束一事，藉由第3導電層48和第2導電層46，係形成將接地層40之本體部41以環狀來作包圍的表層部42。藉由此，接地層40係被形成，並且有機被膜50之第1部分50a係被形成。在本實施形態中之所謂「閃蝕刻(快蝕刻)」，係指在使用有半加成法時，將為了進行圖案鍍敷所設置的薄的金屬種層全體性地藉由蝕刻來去除一事。 接著，如同圖10中之(g)所示一般，在接地層40之上面(第1導電層47之第1面47b)以及左右之側面(第1導電層47之第2面47c以及第3面47d)處，有機被膜50之材料係被作塗布。藉由此，從3方向而包圍接地層40之有機被膜部52係被形成。有機被膜部52，係包含有上述之有機被膜50之第2部分50b、第3部分50c以及第4部分50d。藉由有機被膜部52被形成一事，藉由此有機被膜部52和上述之有機被膜部51，係形成將表層部42從外周側來以環狀作包圍的有機被膜50。如同上述一般，在本變形例中，有機被膜50之第1部分50a，係分別與有機被膜50之第3部分50c以及第4部分50d有所連接。 之後，與第1實施形態之印刷配線板5相同的，對於第1絕緣基材10以及接地層40而層積第2絕緣基材20。又，藉由與本變形例之接地層40以及有機被膜50之製造方法相同的方法，配線60以及有機被膜70係被製造出來。最後，係設置阻焊劑層30。 (第2實施形態) 接著，針對第2實施形態作說明。第2實施形態，係使接地層40以及配線60之各者具備有雙重之有機被膜之層，在此點上，係與第1實施形態相異。以下所說明的構成以外之構成，係與第1實施形態之構成相同。 圖11，係為對於第2實施形態之印刷配線板5A作展示之剖面圖。在本實施形態中，印刷配線板5A，係除了第1實施形態之印刷配線板5之構成之外，更進而包含有有機被膜91以及有機被膜92。 有機被膜91，係被形成為將有機被膜50從外周側來作覆蓋之環狀。有機被膜91，係被設置在有機被膜50與第1絕緣基材10之間、以及有機被膜50與第2絕緣基材20之間。 同樣的，有機被膜91，係被形成為將有機被膜70從外周側來作覆蓋之環狀。有機被膜92，係被設置在有機被膜70與第2絕緣基材20之間、以及有機被膜70與阻焊劑層30之間。 在本實施形態中，有機被膜50、70，係如同上述一般地而身為對於第2導電材料M2之離子遷移作抑制的功能層。有機被膜50、70，例如，係藉由塗布螫合劑或硫醇劑等而被形成。有機被膜50、70之各者，係為「第1有機被膜」之其中一例。 另一方面，有機被膜91、92，係身為將有機被膜50、70與絕緣基材10、20或者是阻焊劑層30之間的接著性(接合性)提高之功能層。有機被膜91、92，係藉由與有機被膜50、70相異之材料而被形成。有機被膜91、92，係藉由相較於有機被膜50、70而更容易與絕緣基材10、20或者是阻焊劑層30作接著的材料而被形成。有機被膜91、92，例如，係藉由矽烷耦合劑而被形成。有機被膜91、92之各者，係為「第2有機被膜」之其中一例。 若依據此種構成，則就算是在為了對於離子遷移或腐蝕等作抑制而設置了有機被膜50、70的情況時，亦能夠將接地層40或配線60與絕緣基材10、20或者是阻焊劑層30之間的接著性提高。藉由此，係能夠使印刷配線板5A之長期信賴性更進一步提升。 (第3實施形態) 接著，針對第3實施形態作說明。第3實施形態，係具備有將接地層40和配線60作連接之通孔95，在此點上，係與第1實施形態相異。以下所說明的構成以外之構成，係與第1實施形態之構成相同。 圖12，係為對於第3實施形態之印刷配線板5B作展示之剖面圖。圖12，係將印刷配線板5B之一部分構成抽出並作展示。在本實施形態中，印刷配線板5B，係除了第1實施形態之印刷配線板5之構成之外，更進而具備有通孔95。在圖12所示之例中，印刷配線板5B，係具備有接地層40、和配線60、以及將接地層40和配線60作連接之通孔95。但是，通孔95，係並不被限定於將接地層40和配線60作連接之通孔，而亦可身為將複數之訊號用之配線60作連接之通孔。於此情況，係只要在以下之說明中的「接地層40」、「本體部41」、「表層部42」分別替換為「配線60」、「本體部61」、「表層部62」即可。通孔95，係為「導電性之連接部」之其中一例。但是，「導電性之連接部」，係亦可為貫孔等。 通孔95，係在Z方向上而中介存在於接地層40與配線60之間。亦即是，通孔95，係在Z方向上而與接地層40相重疊，並且在Z方向上與配線60相重疊。通孔95，係被設置在第2絕緣基材20之內部，並在第2絕緣基材20之內部而於Z方向上延伸。通孔95，例如係藉由第1導電材料M1而被形成。 通孔95，係作為Z方向之端部，而具備有第1端部95a、和位置於與第1端部95a相反側處之第2端部95b。通孔95之第1端部95a，係與接地層40之表層部42之第2部分42b相接。通孔95之第2端部95b，係與配線60之本體部61以及表層部62相接。藉由此，通孔95，係將接地層40與配線60作電性連接。 若依據此種構成，則由於通孔95與接地層40之表層部42係被作連接，因此，係能夠將在配線60之表層部62中所流動的電流有效率地導引至接地層40之表層部42處。藉由此，而使傳輸損失更進一步降低，而能夠謀求傳輸特性之提升。 (第4實施形態) 接著，針對第4實施形態作說明。第4實施形態，係使通孔95包含有藉由第2導電材料M2所形成之表層部，在此點上，係與第3實施形態相異。以下所說明的構成以外之構成，係與第3實施形態之構成相同。 圖13，係為對於第4實施形態之印刷配線板5C作展示之剖面圖。在本實施形態中，通孔95，係具備有本體部96、和表層部97。本體部96，係在Z方向上，位置於接地層40之表層部42之第2部分42b與配線60之本體部61之間。本體部96，係在第2絕緣基材20之內部而在Z方向上延伸。在本實施形態中，本體部96，係與配線60之本體部61相接。例如，本體部96，係具備有面向接地層40之底面96a、和從底面96a之周緣部起而朝向配線60延伸之周面96b。本體部96，係藉由第1導電材料M1而被形成。本體部96，係為「第3導電部」之其中一例。 表層部97，係藉由第2導電材料M2而被形成。表層部97，係為「第4導電部」之其中一例。表層部97，係包含有第1部分97a、和第2部分97b。 第1部分97a，係在Z方向上，位置於接地層40之表層部42與通孔95之本體部96之間。第1部分97a，係沿著通孔95之本體部96之底面96a而在X方向以及Y方向上延伸。第1部分97a，係在Z方向上與接地層40之表層部42相接，並且在Z方向上與通孔95之本體部96相接。 第2部分97b，係從第1部分97a之周緣部起朝向配線60之表層部62而延伸。第2部分97b，係沿著通孔95之本體部96之周面96b而延伸。第2部分97b，係在X方向以及Y方向上，位置於第2絕緣基材20與通孔95之本體部96之間。第2部分97b，係被形成為在X方向以及Y方向上而包圍本體部96之環狀。第2部分97b，係與配線60之表層部62之第1部分62a相接。亦即是，第1部分97a以及第2部分97b，係形成將接地層40之表層部42與配線60之表層部62作連接的電阻率為小之電流路徑。 接著，針對第4實施形態之印刷配線板5C之製造方法作說明。 圖14以及圖15，係為對於印刷配線板5C之製造方法之其中一例作展示之圖。首先，藉由與參照圖5以及圖6所作了說明的第1實施形態之印刷配線板5相同之工程，來形成圖6中之(g)所示之中間構造體。之後，如同圖14中之(k)所示一般，準備包含有第2導電材料M2之金屬箔65(例如銀箔)。在金屬箔65之單面(圖12中之下面)處，係被塗布有有機被膜70之材料，而被形成有層狀之有機被膜部71。有機被膜部71，例如係被設置在金屬箔65之單面之全面上。 接著，如同圖14中之(l)所示一般，於單面處被設置有有機被膜部71之金屬箔65，係被貼附在上述中間構造體之第2絕緣基材20之第1面20a上。對於第2絕緣基材20之金屬箔65之貼附，例如係藉由壓接而被進行，但是，係亦可採用其他之方法。藉由此，係對於第2絕緣基材20而形成導電層66。導電層66，係身為於X方向以及Y方向上而擴廣之面狀之層。 接著，如同圖14中之(m)所示一般，在導電層66之上形成保護膜(阻劑)P2。之後，通過被形成於保護膜P2處之開口部P2a，而設置在Z方向上貫通導電層66、有機被膜部71以及第2絕緣基材20之孔部20h。例如，在形成孔部20h之過程中，位置於與孔部20h相對應之區域處的有機被膜50之第2部分50b之一部分係被去除。其結果，在後續工程中通孔95係成為並不隔著有機被膜50地而與接地層40之表層部42相接。當使通孔95替代接地層40而與配線60作連接的情況、或者是使通孔不僅是接地層40而亦進而與配線60作連接的情況時，通孔95係成為並不隔著有機被膜70地而與配線60之表層部62相接。 接著，保護膜P2係被去除，如同圖14中之(n)所示一般，係對於孔部20h之內面和導電層66之表面而進行使用有第2導電材料M2之鍍敷處理。藉由此，沿著孔部20h之內面，包含有第2導電材料M2之導電層67係被形成。另外，在設置導電層67之前，係亦可追加「在孔部20h之內面而設置與有機被膜50(或者是有機被膜70)相同之有機被膜」之工程。導電層67，係形成通孔95之表層部97，並且形成配線60之表層部62之第1部分62a之一部分。 接著，如同圖15中之(o)所示一般，係對於導電層66之上而進行使用有第1導電材料M1之鍍敷處理。藉由此，來將孔部20h之內部作填埋並形成通孔95之本體部96，並且形成在導電層66之上而擴廣的包含有第1導電材料M1之導電層68。藉由本工程所形成之本體部96，係與之前所被形成的表層部97一同地成為通孔95。 接著，如同圖15中之(p)所示一般，對於導電層66、有機被膜部71以及導電層68進行圖案加工。藉由此，係從導電層66而形成配線60之表層部62之第1部分62a，並從導電層68而形成配線60之本體部61，並且從有機被膜部71而形成有機被膜70之第1部分70a。之後，如同圖15中之(q)、(r)所示一般，藉由進行與圖5中之(e)、(f)相同之工程，配線60之表層部62以及有機被膜70係被形成。 若依據此種構成，則從配線60而流動至接地層40的電流之至少一部分，係能夠通過藉由電阻率為小的第2導電材料M2所形成之通孔95之表層部97而流動。藉由此，係能夠使印刷配線板5之傳輸特性更進一步提升。 以上，雖係針對數個的實施形態以及變形例作了說明，但是，實施形態係並不被限定於上述之例。上述之數個的實施形態以及變形例，係亦可相互作組合並實現之。 若依據以上所說明了的至少1個的實施形態，則印刷配線板，係具備有第1絕緣部、第2絕緣部、第1導電部以及第2導電部。前述第1導電部，係位置於前述第1絕緣部與前述第2絕緣部之間，並包含第1導電材料。前述第2導電部，係包含有位置於前述第1絕緣部與前述第1導電部之間之第1部分，並包含電阻率為較前述第1導電材料而更小之第2導電材料。若依據此種構成，則係能夠謀求傳輸特性之提升。 雖係針對本發明之數種實施形態作了說明，但是，該些實施形態，係僅為作為例子所提示者，而並非為對於本發明之範圍作限定者。此些之實施形態，係可藉由其他之各種形態來實施，在不脫離發明之要旨的範圍內，係可進行各種之省略、置換、變更。此些之實施形態及其變形，係被包含於發明之範圍以及要旨內，並且亦被包含於申請專利範圍中所記載之發明及其均等範圍內。 Hereinafter, the manufacturing method of the printed wiring board, the memory system, and the printed wiring board of the embodiment will be described with reference to the drawings. In the following description, the same reference numerals are attached to the components having the same or similar functions. In addition, there may be cases where the overlapping description of these configurations is omitted. In the following description, the term "parallel" includes the case of "slightly parallel", and the term "orthogonal" includes the case of "slightly orthogonal". The term "overlapping" refers to a situation where the virtual projection images of two objects overlap each other, and the two objects are not directly in contact with each other. The so-called "connection" is not limited to the case of being physically connected, but also includes the case of being electrically connected. On the other hand, the term "adjacent" means that the two members are adjacent to each other without intervening any material. The so-called "surface" is used in the sense of surface, not in the sense of front-surface. First, the X direction, the Y direction, and the Z direction are defined. The X direction and the Y direction are the directions along the first surface 10a (see FIG. 3 ) of the first insulating base material 10 of the printed wiring board 5 to be described later. The X direction is the direction in which at least a part of the wiring 60 described later extends. The Y direction is a direction that intersects (eg, is orthogonal to) the X direction. The Z direction is a direction intersecting (eg, orthogonal to) the X direction and the Y direction. The Z direction is the thickness direction of the printed wiring board 5 . In this specification, the system may also be referred to as "up" or "down". However, these expressions are only for the convenience of description, and are not intended to prescribe the direction of gravity. (First Embodiment) <1. Overall Configuration of Memory System> FIG. 1 is a block diagram showing the configuration of the memory system 1 of the first embodiment connected to the host device 2 . The memory system 1 is, for example, a storage device such as an SSD (Solid State Drive). The memory system 1 is connected to the host device 2 and functions as an external memory device of the host device 2 . The host device 2 is, for example, a device that controls the memory system 1 in an information processing device such as a server device, a personal computer, or a mobile terminal. The host device 2 can issue an access request to the memory system 1 (a request for writing data or a request for reading data, etc.). The memory system 1 includes, for example, a memory controller 100 , external connection terminals 200 , one or more (for example, plural) NAND devices 300 , and a DRAM (Dynamic Random Access Memory) 400 . However, the memory system 1 may not include the DRAM 400 . The memory controller 100 executes writing, reading, and deletion of data in the NAND device 300 based on the access request issued by the host device 2 . The memory controller 100 is one example of a "controller". Details of the memory controller 100 will be described later. The external connection terminals 200 are terminal pins, terminal pads, etc., and can be electrically connected to the host device 2 . The NAND device 300 is a NAND-type flash memory. The NAND device 300 is provided with a memory array including a plurality of memory cells, and stores data in a non-volatile manner. The NAND device 300 is one example of a "semiconductor memory device". However, the semiconductor memory device is not limited to the above-mentioned examples, and may be a resistance variable type, a magnetic variable type, or other types of semiconductor memory devices. The DRAM 400 is the data of the write object received from the host device 2 and written to the NAND device 300 and/or read from the NAND device 300 and read before being sent to the host device 2 Object data, etc., as temporary memory. <2. Configuration of Memory Controller> Next, the memory controller 100 will be described in detail. The memory controller 100, for example, includes a host interface circuit (host I/F) 110, a RAM (Random Access Memory) 120, a ROM (Read Only Memory) 130, a CPU (Central Processing Unit) 140, an ECC (Error Correcting Memory) Code) circuit 150 , NAND interface circuit (NANDI/F) 160 and DRAM interface circuit (DRAMI/F) 170 . These structures are connected to each other by the bus bar 180 . For example, the memory controller 100 is formed by integrating these components into a single chip SoC (System on a Chip). However, a part of these components may also be provided outside the memory controller 100 . One or more of the RAM 120 , the ROM 130 , the CPU 140 and the ECC circuit 150 may also be provided inside the host I/F 110 or the NAND I/F 160 . The host I/F 110 , under the control of the CPU 140 , performs control of data transfer between the host device 2 and the memory controller 100 . The host I/F 110 transmits and receives electrical signals between the memory controller 100 and the host device 2 through the transmission line L1 between the memory controller 100 and the external connection terminal 200 . The host I/F110 is one of the high-speed interfaces for sending and receiving high-speed signals. The RAM 120 is, for example, SDRAM (Synchronous Dynamic Random Access Memory) or SRAM (Static Random Access Memory), but is not limited to this. The RAM 120 provides a work area for the CPU 140 . The RAM 120 is loaded with firmware (programs) stored in the ROM 130 when the memory system 1 operates. The RAM 120 also functions as a buffer for data transfer between the host device 2 and the NAND device 300 . The CPU 140 is one example of a hardware processor. The CPU 140 controls the operation of the memory controller 100 by, for example, executing the firmware loaded into the RAM 120 . For example, the CPU 140 controls operations related to writing, reading, and deleting of data to the NAND device 300 . The ECC circuit 150 performs coding for error correction for the data to be written to the NAND device 300 . The ECC circuit 150 performs error correction on the read data based on the error correction code added during the writing operation. The NAND I/F 160 , under the control of the CPU 140 , performs the control of data transfer between the memory controller 100 and the NAND device 300 . The NAND I/F 160 transmits and receives electrical signals between the memory controller 100 and the NAND device 300 through the transmission line L2 between the memory controller 100 and the NAND device 300 . NAND I/F160 is another example of a high-speed interface for sending and receiving high-speed signals. The DRAM I/F 170, under the control of the CPU 140, executes the control of data transfer between the memory controller 100 and the DRAM 400. The DRAM I/F 170 transmits and receives electrical signals between the memory controller 100 and the DRAM 400 through the transmission line L3 between the memory controller 100 and the DRAM 400 . DRAM I/F170 is another example of a high-speed interface for sending and receiving high-speed signals. <3. Configuration of Printed Wiring Board> FIG. 2 is a perspective cross-sectional view showing the printed wiring board 5 of the first embodiment. The printed wiring board 5 is included in the memory system 1 described above. The memory controller 100 , the external connection terminals 200 , the NAND device 300 and the DRAM 400 are provided on the printed wiring board 5 . The printed wiring board 5 is, for example, a multilayer substrate, and in FIG. 2 , only a part of the layers is shown. This point is also the same in the following figures. The printed wiring board 5 may be a rigid substrate, a flexible substrate, or a rigid and flexible substrate in which the rigid substrate and the flexible substrate are integrally connected. The printed wiring board 5 is not limited to a multilayer substrate, and may be a single-sided substrate or a double-sided substrate. As shown in FIG. 2 , the printed wiring board 5 includes a first insulating base material 10 , a second insulating base material 20 , a solder resist layer 30 , a ground layer 40 , an organic film 50 (see FIG. 3 ), and wiring 60 , the organic film 70 (see FIG. 3 ), and the spacer 80 . The wiring 60, the ground layer 40, or the combination of the wiring 60 and the ground layer 40 constitute at least a part of any one of the above-mentioned transmission line L1, transmission line L2, or transmission line L3. FIG. 3 is a cross-sectional view taken along the line F3-F3 of the printed wiring board 5 shown in FIG. 2 . The first insulating base material 10 is formed in a layered shape along the X direction and the Y direction. The first insulating substrate 10 is made of a general printed wiring board insulating material (glass cloth substrate epoxy resin, glass composite substrate epoxy resin, paper substrate phenol resin, polyimide, etc.) formed, and has insulating properties. The first insulating base material 10 includes a first surface 10a facing the ground layer 40 and the second insulating base material 20 described later, and a second surface 10b located on the opposite side of the first surface 10a. The second insulating base material 20 is formed in a layered shape along the X direction and the Y direction. The second insulating base material 20 is the same as the first insulating base material 10, and is formed of an insulating material of a general printed wiring board, and has insulating properties. The second insulating base material 20 is overlapped in the Z direction with respect to the first insulating base material 10 . The second insulating base material 20 is located in the vicinity of the outside of the printed wiring board 5 with respect to the first insulating base material 10 in the Z direction. The second insulating base material 20 includes a first surface 20a facing the wiring 60 and the solder resist layer 30 described later, and a surface opposite to the first surface 20a and facing the ground layer 40 and the first insulating base material 10 The second surface 20b. From a certain viewpoint, the first insulating base material 10 is one example of the "first insulating portion", and the second insulating base material 20 is one example of the "second insulating portion". The second insulating base material 20 includes a first portion 21 that overlaps the ground layer 40 in the Z direction, a second portion 22 that is aligned with the ground layer 40 in the Y direction, and a second portion 22 that overlaps the ground layer 40 in the Y direction. The third portion 23 from the opposite side is arranged side by side with the ground layer 40 . The second portion 22 and the third portion 23 are in contact with the first insulating base material 10 . The solder resist layer 30 is exposed outside the printed wiring board 5 and forms a part of the surface of the printed wiring board 5 . The solder resist layer 30 is formed in a layered shape along the X direction and the Y direction. The solder resist layer 30 is a protective layer covering a circuit pattern including the wiring 60 described later. The solder resist layer 30 is formed of, for example, an insulating material prepared by mixing epoxy resin and inorganic powder, and has insulating properties. The solder resist layer 30 is overlapped in the Z direction with respect to the second insulating base material 20 . The solder resist layer 30 is located in the vicinity of the outside of the printed wiring board 5 with respect to the second insulating base material 20 in the Z direction. The solder resist layer 30 includes a first surface 30a exposed outside the printed wiring board 5 and a second surface 30b located on the opposite side of the first surface 30a and facing the wiring 60 and the second insulating base material 20 . From another viewpoint, the second insulating base material 20 is one example of the "first insulating portion", and the solder resist layer 30 is one example of the "second insulating portion". The solder resist layer 30 includes a first portion 31 that overlaps the wiring 60 in the Z direction, a second portion 32 that is aligned with the wiring 60 in the Y direction, and a second portion 32 from the opposite side of the second portion 32. The third portion 33 is arranged alongside the wiring 60 . The second portion 32 and the third portion 33 are in contact with the second insulating base material 20 . The ground layer (ground pattern) 40 is a conductor pattern provided between the first insulating base material 10 and the second insulating base material 20 . The ground layer 40 serves as a voltage reference for the printed wiring board 5 and forms a return path through which a return current of a current (electrical signal) passing through the wiring 60 described later flows. The ground layer 40 extends in the X direction and the Y direction. In the present embodiment, the ground layer 40 is a flat pattern extending in the X direction and the Y direction. The width of the ground layer 40 in the Y direction is larger than the width of the wiring 60 in the Y direction. The ground layer 40 overlaps the wiring 60 in the Z direction. In the present embodiment, the ground layer 40 includes a main body portion 41 and a surface layer portion 42 . The main body portion 41 is located between the first insulating base material 10 and the second insulating base material 20 . The main body portion 41 extends in the X direction along the first surface 10 a of the first insulating base material 10 . In this embodiment, the main body portion 41 is formed in a layered shape along the X direction and the Y direction. The width W1 of the body portion 41 in the Y direction is larger than the thickness T1 of the body portion 41 in the Z direction. The thickness T1 of the body portion 41 in the Z direction is, for example, 10 μm to 50 μm. The main body portion 41 is formed of the first conductive material M1. The first conductive material M1 is, for example, a metal material. The first conductive material M1 is, for example, copper. The main body portion 41 is one example of the "first conductive portion". The surface layer portion 42 is formed of a second conductive material M2 different from the first conductive material M1. The second conductive material M2 is a conductive material whose resistivity is smaller than that of the first conductive material M1. The second conductive material M2 is, for example, a metal material. The second conductive material M2 is, for example, silver. The surface layer portion 42 is one example of the "second conductive portion". In the present embodiment, the surface layer portion 42 includes a first portion 42a, a second portion 42b, a third portion 42c, and a fourth portion 42d. The first portion 42 a is located between the first insulating base material 10 and the main body portion 41 . The first portion 42 a is in contact with the main body portion 41 in the Z direction, and extends in the X direction along the main body portion 41 . In the present embodiment, the first portion 42a is formed in a layered shape along the X direction and the Y direction. The second portion 42b is located between the second insulating base material 20 and the main body portion 41 . That is, the second portion 42b overlaps the main body portion 41 from the side opposite to the first portion 42a in the Z direction. The second portion 42b is in contact with the main body portion 41 in the Z direction, and extends in the X direction along the main body portion 41 . In this embodiment, the second portion 42b is formed in a layered shape along the X direction and the Y direction. The third portion 42c is located between the second portion 22 of the second insulating base material 20 and the body portion 41 in the Y direction. The third portion 42c is in contact with the main body portion 41 in the Y direction, and extends in the X direction along the main body portion 41 . In other words, the third portion 42c is in contact with the main body portion 41 from a direction different from that of the first portion 42a and the second portion 42b. The third portion 42c also extends in the Z direction and connects the first portion 42a and the second portion 42b. In the present embodiment, the third portion 42c is formed in a layered shape along the X direction and the Z direction. The fourth portion 42d is located between the third portion 23 of the second insulating base material 20 and the main body portion 41 in the Y direction. That is, the fourth portion 42d overlaps the main body portion 41 from the side opposite to the third portion 42c in the Y direction. The fourth portion 42d is in contact with the main body portion 41 in the Y direction, and extends in the X direction along the main body portion 41 . In other words, the fourth portion 42d is in contact with the main body portion 41 from a direction different from that of the first portion 42a and the second portion 42b. The fourth portion 42d also extends in the Z direction and connects the first portion 42a and the second portion 42b. In the present embodiment, the fourth portion 42d is formed in a layered shape along the X direction and the Z direction. In the present embodiment, the first portion 42a, the second portion 42b, the third portion 42c, and the fourth portion 42d are connected to each other. Thereby, the surface layer portion 42 is formed in a ring shape surrounding the main body portion 41 in the cross section along the Y direction and the Z direction (that is, the cross section shown in FIG. 3 ). Here, the so-called "ring" in the present embodiment may be, for example, an incomplete ring that is partially broken due to manufacturing reasons. In addition, the so-called "ring" is not limited to a circular ring, but also includes a rectangular ring. These definitions are also the same below. In this embodiment, the thickness T2a of the first part 42a in the Z direction, the thickness T2b of the second part 42b in the Z direction, the thickness T2c of the third part 42c in the Y direction, and the thickness T2d of the fourth part 42d in the Y direction Each of them is, for example, 0.5 μm. That is, each of the thickness T2a of the first portion 42a in the Z direction, the thickness T2b of the second portion 42b in the Z direction, the thickness T2c of the third portion 42c in the Y direction, and the thickness T2d of the fourth portion 42d in the Y direction , which is thinner than the thickness T1 of the body portion 41 in the Z direction. In this embodiment, the sum of the thickness T2a of the first portion 42a in the Z direction and the thickness T2b of the second portion 42b in the Z direction is thinner than the thickness T1 of the body portion 41 in the Z direction. FIG. 4 is a cross-sectional view taken along the line F4-F4 of the printed wiring board 5 shown in FIG. 2 . As shown in FIG. 4 , the surface layer portion 42 is provided to cover the entire length of the main body portion 41 , or is provided to a partial area of the entire length of the main body portion 41 . For example, the surface layer portion 42 covers the entire length of the main body portion 41 or a partial area of the entire length of the main body portion 41 , and covers the main body portion 41 in a ring shape. Returning to FIG. 3 , the organic film 50 will be described. The organic film 50 is formed in a ring shape covering the surface layer portion 42 of the ground layer 40 from the outer peripheral side in the cross section along the Y direction and the Z direction (that is, the cross section shown in FIG. 3 ). The organic film 50 includes a first portion 50a, a second portion 50b, a third portion 50c, and a fourth portion 50d. The first portion 50 a is provided between the first portion 42 a of the surface layer portion 42 and the first insulating base material 10 , and covers the first portion 42 a of the surface layer portion 42 . The second portion 50b is provided between the second portion 42b of the surface layer portion 42 and the first portion 21 of the second insulating base material 20 and covers the second portion 42b of the surface layer portion 42 . The third portion 50c is provided between the third portion 42c of the surface layer portion 42 and the second portion 22 of the second insulating base material 20 and covers the third portion 42c of the surface layer portion 42 . The fourth portion 50d is provided between the fourth portion 42d of the surface layer portion 42 and the third portion 23 of the second insulating base material 20, and covers the fourth portion 42d of the surface layer portion 42. In the present embodiment, there is a gap Sa in the Y direction between the first portion 50a and the third portion 50c. The 1st part 50a and the 3rd part 50c are divided by the clearance gap Sa. The gap Sa is located between the third portion 42c of the surface layer portion 42 and the first insulating base material 10 in the Z direction. The width in the Y direction of the gap Sa is, for example, substantially the same as the thickness T2c in the Y direction of the third portion 42c of the surface layer portion 42 . Similarly, there is a gap Sb in the Y direction between the first portion 50a and the fourth portion 50d. The first portion 50a and the fourth portion 50d are divided by the gap Sb. The gap Sb is located between the fourth portion 42d of the surface layer portion 42 and the first insulating base material 10 in the Z direction. The width in the Y direction of the gap Sb is, for example, substantially the same as the thickness T2d in the Y direction of the fourth portion 42d of the surface layer portion 42 . The organic film 50 is a functional layer that suppresses ion migration of the second conductive material M2 (eg, silver). The organic film 50 is formed, for example, by applying a chelating agent, a thiol agent, or the like. The thickness of the organic film 50 is, for example, 1 μm. The same applies to the organic film 70 to be described later. The wiring 60 is a wiring pattern provided on the printed wiring board 5 . The wiring 60 is provided between the second insulating base material 20 and the solder resist layer 30 . At least a part of the wiring 60 extends in the X direction. In this embodiment, the wiring 60 is a signal wiring through which electrical signals flow. As described above, the wiring 60 is formed, for example, between the memory controller 100 and the external connection terminal 200 , between the memory controller 100 and the NAND device 300 , or between the memory controller 100 and the DRAM 400 . In this embodiment, the wiring 60 flows a high-speed signal of 15 GHz or more. For example, the wiring 60 flows a 32GT/s (16GHz) or 64GT/s (32GHz) signal corresponding to the fifth or sixth generation of PCIe (Peripheral Component Interconnect-Express) (registered trademark). However, the signal flowing through the wiring 60 is not limited to the above-mentioned example. In the present embodiment, the wiring 60 includes a main body portion 61 and a surface layer portion 62 . The surface layer portion 62 includes a first portion 62a, a second portion 62b, a third portion 62c, and a fourth portion 62d. The configuration of the wiring 60 is the same as that of the ground layer 40 . Therefore, in the detailed description related to the wiring 60, in the above-mentioned description related to the ground layer 40, "the main body part 41", "the surface layer part 42", "the first part 42a", and "the second part 42b" are used. , "Part 3 42c", "Part 4 42d", "Part 1 10", "Part 2 20", "Part 1 21", "Part 2 22", "Part 3 Part 23", respectively replaced with "Main part 61", "Surface part 62", "First part 62a", "Second part 62b", "Third part 62c", "Fourth part 62d", "Second part 62b" The insulating base material 20", the "solder resist layer 30", the "first part 31", the "second part 32", and the "third part 33" may be sufficient. The main body portion 61 is another example of the "first conductive portion". The surface layer portion 62 is another example of the "second conductive portion". In Table 1, "components used in the description related to the ground layer 40 (components before replacement)" and "components used in the description related to the wiring 60 (components after replacement)" ” to show the correspondence between them. [Table 1] Elements before replacement Elements after replacement main body 41 main body 61 Surface layer 42 Surface layer 62 Part 1 42a Part 1 62a Part 2 42b Part 2 62b Part 3 42c Part 3 62c Part 4 42d Part 4 62d first insulating substrate 10 second insulating substrate 20 second insulating substrate 20 Solder resist layer 30 Part 1 of 21 Part 1 of 31 Part 2 of 22 Part 2 of 32 Part 3 of 23 Part 3 of 33 In the present embodiment, the thickness T3 of the body portion 61 in the Z direction is, for example, 10 μm to 50 μm. Each of the thickness T4a of the first part 62a of the surface layer part 62 in the Z direction, the thickness T4b of the second part 62b in the Z direction, the thickness T4c of the third part 62c in the Y direction, and the thickness T4d of the fourth part 62d in the Y direction , for example, it is 0.5 μm. That is, each of the thickness T4a in the Z direction of the first part 62a, the thickness T4b in the Z direction of the second part 62b, the thickness T4c in the Y direction of the third part 62c, and the thickness T4d in the Y direction of the fourth part 62d , which is thinner than the thickness T3 of the body portion 61 in the Z direction. In this embodiment, the sum of the thickness T4a of the first portion 62a in the Z direction and the thickness T4b of the second portion 62b in the Z direction is thinner than the thickness T3 of the body portion 61 in the Z direction. The organic film 70 is formed in a ring shape covering the surface layer portion 62 of the wiring 60 from the outer peripheral side in the cross section along the Y direction and the Z direction (that is, the cross section shown in FIG. 3 ). The organic film 70 includes a first portion 70a, a second portion 70b, a third portion 70c, and a fourth portion 70d. The first portion 70 a is provided between the first portion 62 a of the surface layer portion 62 and the second insulating base material 20 , and covers the first portion 62 a of the surface layer portion 62 . The second portion 70 b is provided between the second portion 62 b of the surface layer portion 62 and the first portion 31 of the solder resist layer 30 , and covers the second portion 62 b of the surface layer portion 62 . The third portion 70c is provided between the third portion 62c of the surface layer portion 62 and the second portion 32 of the solder resist layer 30, and covers the third portion 62c of the surface layer portion 62. The fourth portion 70d is provided between the fourth portion 62d of the surface layer portion 62 and the third portion 33 of the solder resist layer 30, and covers the fourth portion 62d of the surface layer portion 62. In the present embodiment, a gap Sc in the Y direction exists between the first portion 70a and the third portion 70c. The first portion 70a and the third portion 70c are divided by the gap Sc. The gap Sc is located between the third portion 62c of the surface layer portion 62 and the second insulating base material 20 in the Z direction. The width in the Y direction of the gap Sc is, for example, substantially the same as the thickness in the Y direction of the third portion 62 c of the surface layer portion 62 . Similarly, there is a gap Sd in the Y direction between the first portion 70a and the fourth portion 70d. The first portion 70a and the fourth portion 70d are divided by the gap Sd. The gap Sd is located between the fourth portion 62d of the surface layer portion 62 and the second insulating base material 20 in the Z direction. The width in the Y direction of the gap Sd is, for example, substantially the same as the thickness in the Y direction of the fourth portion 62d of the surface layer portion 62 . Next, the spacer 80 will be described. The spacer 80 is a portion having a wider width in the Y direction than the wiring 60 (see FIG. 2 ). As shown in FIG. 4 , the spacer 80 is provided on the first surface 20 a of the second insulating base material 20 . The peripheral portion of the spacer 80 is covered by the solder resist layer 30 . A part of the second portion 70b of the organic film 70 provided on the spacer 80 is exposed to the outside of the printed wiring board 5 through the opening O provided in the solder resist layer 30 . In the present embodiment, the spacer 80 is connected to both the main body portion 61 and the surface layer portion 62 of the wiring 60 . The spacer 80 has, for example, the same configuration as the wiring 60 . That is, the gasket 80 includes the main body portion 81 and the surface layer portion 82 . The body portion 81 is integrally formed with the body portion 61 of the wiring 60 and is continuous with the body portion 61 of the wiring 60 . The main body portion 81 overlaps the connection terminal S of the electronic component EC, which will be described later, in the Z direction. In the present embodiment, the main body portion 81 has a circular shape when viewed in the Z direction. However, the main body portion 81 may have a rectangular shape or other shapes. The surface layer portion 82 of the gasket 80 is provided integrally with the surface layer portion 62 of the wiring 60 and is continuous with the surface layer portion 62 of the wiring 60 . The surface layer portion 82 includes a first portion 82a, a second portion 82b, a third portion 82c (see FIG. 2 ), a fourth portion 82d (see FIG. 2 ), and a fifth portion 82e. The first portion 82 a is located between the second insulating base material 20 and the main body portion 81 . The second portion 82b overlaps the main body portion 81 from the opposite side to the first portion 82a in the Z direction. At least a part of the second portion 82b faces the opening O in the Z direction while sandwiching the second portion 70b of the organic film 70 . At least a part of the second portion 82b is positioned between the connection terminal S of the electronic component EC and the main body portion 81 in a state where the electronic component EC is mounted. The connection terminal S of the electronic component EC is connected to at least a part of the 2nd part 82b. The third portion 82c is aligned with the main body portion 81 in the Y direction, and is provided along the side surface of the main body portion 81 (see FIG. 2 ). In the present embodiment, the third portion 82c has a circular arc shape along the peripheral surface of the main body portion 81 . The fourth portion 82d is aligned with the main body portion 81 in the Y direction from the opposite side to the third portion 82c, and is provided along the side surface of the main body portion 81 (see FIG. 2 ). In the present embodiment, the fourth portion 82d has an arc shape along the peripheral surface of the main body portion 81 . The fifth portion 82e is aligned with the body portion 81 in the X direction from the side opposite to the wiring 60, and is provided along the side surface of the body portion 81 (see FIG. 2). The fifth portion 82e is a region that overlaps the wiring 60 in the surface layer portion 82 when viewed in the X direction. The fifth portion 82e is provided between the third portion 82c and the fourth portion 82d. In the present embodiment, the fifth portion 82e has an arc shape along the peripheral surface of the main body portion 81 . As shown in FIG. 4 , a part of the first part 70a of the organic film 70 is provided between the first part 82a of the surface layer part 82 and the second insulating substrate 20 and covers the first part of the surface layer part 82 82a. A part of the second part 70b of the organic film 70 is provided between the second part 82b of the surface layer part 82 and the first part 31 of the solder resist layer 30 and between the second part 82b of the surface layer part 82 and the opening O , and covers the second portion 82b of the surface layer portion 82 . A part of the organic film 70 is provided between the fifth part 82e of the surface layer part 82 and the solder resist layer 30 and covers the fifth part 82e of the surface layer part 82 . Although the details are not shown, a part of the third part 70c of the organic film 70 is provided between the third part 82c of the surface layer part 82 and the second part 32 of the solder resist layer 30, and covers the surface layer part 82 Part 3 82c. A part of the fourth portion 70d of the organic film 70 is provided between the fourth portion 82d of the surface layer portion 82 and the third portion 33 of the solder resist layer 30, and covers the fourth portion 82d of the surface layer portion 82. Electronic components EC, for example, are electronic components packaged in BGA (Ball Grid Array). In this embodiment, the electronic component EC is any one of the above-mentioned memory controller 100 , the interface component including the external connection terminal 200 , the NAND device 300 , or the DRAM 400 . The connection terminal S is, for example, a solder connection portion (solder ball) of a BGA package. In the present embodiment, the surface of the spacer 80 is coated with a flux F for improving the connectivity between the connection terminal S of the electronic component EC and the spacer 80 . The connection terminal S of the electronic component EC is connected to the surface of the pad 80 via the flux F. However, the flux F series is not essential and may be omitted. Other descriptions related to the gasket 80 are as long as in the above description related to the ground layer 40, "the body part 41", "the surface layer part 42", "the first part 42a", "the second part 42b", "Part 3 42c", "Part 4 42d", "Part 1 10", "Part 2 20", "Part 1 21", "Part 2 22", "Part 3"23" are replaced with "main body part 81", "surface layer part 82", "1st part 82a", "2nd part 82b", "3rd part 82c", "4th part 82d", "2nd part of insulating base" Material 20", "solder resist layer 30", "first part 31", "second part 32", and "third part 33" are sufficient. Table 2 is about "components used in the description related to the ground layer 40 (components before replacement)" and "components used in the description related to the spacer 80 (components after replacement)" )” to show the corresponding relationship. [Table 2] Elements before replacement Elements after replacement main body 41 main body 81 Surface layer 42 Surface layer 82 Part 1 42a Part 1 82a Part 2 42b Part 2 82b Part 3 42c Part 3 82c Part 4 42d Part 4 82d first insulating substrate 10 second insulating substrate 20 second insulating substrate 20 Solder resist layer 30 Part 1 of 21 Part 1 of 31 Part 2 of 22 Part 2 of 32 Part 3 of 23 Part 3 of 33 <4. Manufacturing method of printed wiring board> FIG. 5 and FIG. 6 are diagrams showing one example of the manufacturing method of the printed wiring board 5 . First, as shown in FIG. 5( a ), a metal foil 45 (eg, a silver foil) containing the second conductive material M2 is prepared. On one side of the metal foil 45 (the lower surface in FIG. 4 ), the material of the organic film 50 is applied, and a layered organic film portion 51 is formed. The organic film portion 51 is provided, for example, on the entire surface of one side of the metal foil 45 . Next, as shown in FIG. 5( b ), the metal foil 45 provided with the organic film portion 51 on one surface is attached to the first surface 10 a of the first insulating base material 10 . Attachment of the metal foil 45 of the first insulating base material 10 is performed by, for example, crimping, but other methods may also be employed. Thereby, the second conductive layer 46 is formed with respect to the first insulating base material 10 . The second conductive layer 46 is a planar layer extending in the X direction and the Y direction. Here, the expression "for a certain component (component A) is formed (or provided) with another component (component B)", except that the surface of component A and the surface of component B are in contact with each other In addition to the case where it is formed in the manner of , it also includes the case where there are other layers between the constituent element A and the constituent element B. This definition is also the same in the following. For example, “the second conductive layer 46 is formed on the first insulating base material 10 ” is not only a case where the surface of the first insulating base material 10 is formed in contact with the second conductive layer 46 but also It includes the case where another layer is interposed between the first insulating base material 10 and the second conductive layer 46 . In the present embodiment, the organic film portion 51 is interposed between the first insulating base material 10 and the second conductive layer 46 . Next, as shown in FIG. 5( c ), on the surface of the second conductive layer 46 , the first conductive layer 47 including the first conductive material M1 is formed. For example, the first conductive layer 47 is formed by performing a first plating process using the first conductive material M1 on the surface of the second conductive layer 46 . The first plating treatment may be either electrolytic plating or electroless plating. However, if electrolytic plating is employed, a relatively thick first conductive layer 47 can be appropriately formed. The first conductive layer 47 is a planar layer that spreads in the X direction and the Y direction. Next, as shown in FIG. 5( d ), patterning is performed on the first conductive layer 47 , the second conductive layer 46 , and the organic film portion 51 . That is, by etching the unnecessary parts of the first conductive layer 47 , the second conductive layer 46 and the organic film portion 51 , the first conductive layer 47 , the second conductive layer 46 and the organic film portion 51 are etched. Unnecessary parts are removed. Thereby, the main body portion 41 of the ground layer 40 is formed from the first conductive layer 47 , the first portion 42 a of the surface layer portion 42 of the ground layer 40 is formed from the second conductive layer 46 , and the organic film portion 51 is formed. The first portion 50a of the organic film 50 is formed. In the description of the present embodiment, the first conductive layer 47 is not limited to the first conductive layer 47 before being patterned, but also the first conductive layer 47 (also known as the first conductive layer 47 after the unnecessary portion is removed by the patterning process). That is, the main body portion 41) of the ground layer 40 is called a "first conductive layer". Next, as shown in (e) of FIG. 6 , on the surface of the body portion 41 of the ground layer 40 (that is, the first conductive layer 47 after being patterned), a second conductive material M2 is formed. the third conductive layer 48. The third conductive layer 48 is formed by performing a second plating process using the second conductive material M2 on the surface of the body portion 41 of the ground layer 40 . The second plating treatment is, for example, electroless plating. To describe in detail, the patterned first conductive layer 47 includes a first surface 47b facing the opposite side of the second conductive layer 46 in the Z direction, and a first surface 47b facing opposite to the first surface 47b. The second surface 47c in the different direction and the third surface 47d facing the opposite side to the second surface 47c in the Y direction. After that, the third conductive layer 48 is formed so as to be in contact with the first surface 47b , the second surface 47c , and the third surface 47d of the first conductive layer 47 . That is, the third conductive layer 48 that surrounds the body portion 41 of the ground layer 40 from three directions is formed. The third conductive layer 48 includes the second portion 42b, the third portion 42c, and the fourth portion 42d of the surface layer portion 42 of the ground layer 40 described above. Since the third conductive layer 48 is formed, the third conductive layer 48 and the patterned second conductive layer 46 form a surface layer that surrounds the body portion 41 of the ground layer 40 in a ring shape. Section 42. Thereby, the ground layer 40 is formed. Next, as shown in (f) of FIG. 6 , the material of the organic film 50 is applied on the upper surface of the ground layer 40 and on the left and right side surfaces. Thereby, the organic film portion 52 surrounding the ground layer 40 from the three directions is formed. The organic film portion 52 includes the second portion 50b, the third portion 50c, and the fourth portion 50d of the organic film 50 described above. As the organic film portion 52 is formed, the organic film portion 52 and the above-described organic film portion 51 form an organic film 50 that surrounds the surface layer portion 42 in a ring shape from the outer peripheral side. Next, as shown in (g) of FIG. 6 , the second insulating base material 20 is laminated on the first insulating base material 10 and the ground layer 40 . That is, the second conductive layer 47, the second conductive layer 46, and the third conductive layer 48 described above are provided from the opposite side to the first insulating base material 10 in the Z direction. Insulating base material 20 . Next, as shown in (h) of FIG. 6 , the wiring 60 and the organic film 70 are formed on the first surface 20 a of the second insulating base material 20 . The details of the manufacturing method of the wiring 60 and the organic film 70 are the same as the details of the manufacturing method of the ground layer 40 and the organic film 50 (refer to FIGS. 5( a ) to ( d ) and 6 ( e ) to ( g ). description) is the same. Furthermore, in this embodiment, the spacer 80 is formed by the same process as the wiring 60 . When describing the wiring 60 and the spacer 80 , the body portion 61 of the wiring 60 and the body portion 81 of the spacer 80 are formed by the patterned first conductive layer 47 . In the patterned first conductive layer 47, except "the first surface 47b facing the opposite side of the second conductive layer 46 in the Z direction" and "directing in the direction different from the first surface 47b" In addition to the second surface 47c" and the "third surface 47d facing the opposite side of the second surface 47c in the Y direction", "the fifth surface of the surface layer portion 82 of the gasket 80" is also formed in a subsequent process. The fourth surface 47e (refer to FIG. 4 ) where the portion 82e meets. On the other hand, the third conductive layer 48 is formed so as to be in contact with the first surface 47b , the second surface 47c , the third surface 47d , and the fourth surface 47e of the first conductive layer 47 . Finally, the solder resist layer 30 is provided for the second insulating base material 20 and the wiring 60 , and the opening portion O is formed so that the spacer 80 is exposed to the outside of the printed wiring board 5 . Thereby, the printed wiring board 5 is completed. <5. Action> When a high-speed signal flows in the wiring 60 , the skin effect that "concentrated current flows in the vicinity of the surface of the wiring 60" may increase. In the present embodiment, at least part of the current flowing in the vicinity of the surface of the wiring 60 due to the skin effect can be caused by the second conductive material M2 having a lower resistivity than the first conductive material M1 The formed wiring 60 flows in the surface layer portion 62 . FIG. 7 is a diagram showing an example of the skin depth related to the printed wiring board 5 . FIG. 7 , for example, shows the skin depth of a PCIe-related 5th generation (16GHz) or 6th generation (32GHz) signal. For the skin depth d[μm] in Figure 7, if the resistivity is set to ρ[Ω･m], the angular frequency (2πf) is set to ω[Hz], and the magnetic permeability is set to μ[H/ m], is obtained by the following formula (1).

As shown in FIG. 7 , it can be seen that when silver is used as the wiring material, the skin depth d for the 16 GHz signal is about 0.5 μm, and the skin depth d for the 32 GHz signal is about 0.5 μm. is about 0.35 μm. That is, if the surface layer portion 62 having a thickness of about 0.5 μm or about 0.35 μm is provided, most of the current concentrated near the surface of the wiring 60 due to the skin effect can flow in the surface layer portion 62 . <6. Advantages> When the speed-up of the signal progresses further, the influence of the skin effect is more likely to increase. Therefore, in the present embodiment, the wiring 60 of the printed wiring board 5 is provided with the main body portion 61 containing the first conductive material M1, and the second conductive material M2 containing the resistivity smaller than that of the first conductive material M1. The surface layer portion 62 . The main body portion 61 is located between the second insulating base material 20 and the solder resist layer 30 . The surface layer portion 62 includes a first portion 62 a located between the second insulating base material 20 and the main body portion 61 . According to such a configuration, at least a part of the current flowing near the surface of the wiring 60 due to the skin effect can flow through the surface layer portion 62 formed of the second conductive material M2 having a small resistivity. By doing so, it is possible to improve the transmission characteristics (for example, increase the transmission speed and/or reduce the transmission loss). Here, it is also considered to form the entire wiring with the second conductive material M2 having a small resistivity. However, the second conductive material M2 (for example, silver) with relatively small resistivity is more expensive than the first conductive material M1 (for example, copper) with relatively large resistivity. Therefore, if the entire wiring is formed with the second conductive material M2, the manufacturing cost of the printed wiring board increases. On the other hand, in the present embodiment, the body portion 61 of the wiring 60 is formed by the first conductive material M1, and the surface layer portion 62 of the wiring 60 where the current is concentrated due to the skin effect is formed by the first conductive material M1. 2 conductive material M2 is formed. According to such a configuration, an increase in the manufacturing cost of the printed wiring board 5 can be suppressed, and an improvement in the transmission characteristics of the printed wiring board 5 can also be achieved. In this embodiment, the thickness T4a of the first portion 62a of the surface layer portion 62 of the wiring 60 in the Z direction is thinner than the thickness T3 of the body portion 61 of the wiring 60 in the Z direction. According to such a structure, the usage-amount of the 2nd conductive material M2 can be reduced, and the increase of the manufacturing cost of the printed wiring board 5 can be suppressed further. Furthermore, in the present embodiment, the sum of the thickness T4a in the Z direction of the first part 62a of the surface layer part 62 of the wiring 60 and the thickness T4b in the Z direction of the second part 62b is compared with the Z direction of the body part 61 of the wiring 60 The thickness T3 is thinner. According to such a configuration, the usage amount of the second conductive material M2 can be further reduced. In the present embodiment, a high-speed signal having a frequency of 15 GHz or more flows through the wiring 60 . The thicknesses T2a, T2b, T2c, and T2d of the surface layer portion 62 of the wiring 60 are, for example, 0.5 μm or less. According to such a configuration, most of the current flowing in the wiring 60 can be caused to flow in the surface layer portion 62 of the wiring 60 . With this, it is possible to further improve the transmission characteristics. Furthermore, if the thicknesses T2a, T2b, T2c, and T2d of the surface layer portion 62 of the wiring 60 are about 0.5 μm, it can be produced relatively easily even by electroless plating. In the present embodiment, the surface layer portion 62 of the wiring 60 includes the second portion 62b located between the solder resist layer 30 and the main body portion 61 of the wiring 60 . According to such a configuration, more current can be caused to flow through the surface layer portion 62 . With this, it is possible to further improve the transmission characteristics. In the present embodiment, the ground layer 40 that serves as a reference and flows the return current also includes the body portion 41 formed of the first conductive material M1, and the resistivity is relatively The surface layer portion 42 formed of the small second conductive material M2. According to such a configuration, the return current can easily flow, and it is possible to further improve the transmission characteristics of the printed wiring board 5 . Here, the second conductive material M2 (such as silver) is prone to ion migration (the phenomenon that the conductive material is ionized and enters the insulating material) or corroded compared with the first conductive material M1 (such as copper). situation. However, in this embodiment, a part of the organic film 70 is provided between the surface layer portion 62 of the wiring 60 and the second insulating base material 20 . Thereby, even when the surface layer portion 62 of the wiring 60 is formed of the second conductive material M2, ion migration or corrosion caused by the second conductive material M2 can be suppressed. Thereby, the long-term reliability of the printed wiring board 5 can be improved. When the surface of the pad 80 is formed with the second conductive material M2 (eg, silver), compared with the case where the surface of the pad 80 is formed with the first conductive material M1 (eg, copper), electron The bondability between the connection terminal S of the component EC and the spacer 80 can be increased. Therefore, when the surface of the spacer 80 is formed of the second conductive material M2 (eg, silver), the flux F may be omitted or the roughening treatment of the surface of the spacer 80 may be omitted. . Therefore, there may be cases where a reduction in the manufacturing cost of the printed wiring board 5 can be achieved. (Modification) Next, the modification of 1st Embodiment is demonstrated. This modification can also be implemented in combination with the second to fourth embodiments described later. FIG. 8 is a cross-sectional view showing a printed wiring board 5M according to a modification of the first embodiment. The printed wiring board 5M does not include the above-mentioned gaps Sa and Sb of the organic film 50 and gaps Sc and Sd of the organic film 70 . That is, the first portion 50a of the organic film 50 is connected to the third portion 50c and the fourth portion 50d of the organic film 50, respectively. Similarly, the first portion 70a of the organic film 70 is connected to the third portion 70c and the fourth portion 70d of the organic film 70, respectively. FIG. 9 and FIG. 10 are diagrams showing the manufacturing method of the printed wiring board 5M of the modified example. In the manufacturing method of the present modification, the metal foil 45 (eg, silver foil) containing the second conductive material M2 is used as a seed layer, and a process called flash etching or quick etching is used. The semi-additive method is different from the manufacturing method of the printed wiring board 5 of the above-mentioned first embodiment in this point. In the manufacturing method of this modification, as shown in FIG.9(a), the intermediate body M which provided the 2nd conductive layer 46 with respect to the 1st insulating base material 10 is formed. The intermediate body M can be produced by the same process as the printed wiring board 5 of the first embodiment described with reference to (a) and (b) of FIG. 5 . The intermediate body M is the same as that of the first embodiment, and includes the organic film portion 51 interposed between the first insulating base material 10 and the second conductive layer 46 . Next, as shown in FIG. 9( b ), a mask MK is provided on the second conductive layer 46 . The mask MK is provided on the surface of the second conductive layer 46 corresponding to a region other than the region where the body portion 41 of the ground layer 40 is provided. Next, as shown in (c) of FIG. 9 , the first conductive layer 47 including the first conductive material M1 is formed in the region where the mask MK is not provided. The first conductive layer 47 of this modification is a conductive layer that becomes the main body portion 41 of the ground layer 40 without being patterned. The first conductive layer 47 (that is, the body portion 41 of the ground layer 40 ) is formed by performing a first plating process using the first conductive material M1 . The first plating treatment may be either electrolytic plating or electroless plating. However, if electrolytic plating is employed, it is possible to appropriately form a thick film of the main body portion 41 . Next, as shown in (d) of FIG. 9 , the mask MK is removed. As a result, the first surface 47b, the second surface 47c, and the third surface 47d of the first conductive layer 47 are exposed to the outside. The first surface 47b is the surface facing the opposite side to the second conductive layer 46 in the Z direction. The second surface 47c is a surface facing in a direction different from that of the first surface 47b. The third surface 47d is a surface facing the opposite side to the second surface 47c in the Y direction. Next, as shown in (e) of FIG. 10 , on the surface of the first conductive layer 47 (that is, the body portion 41 of the ground layer 40 ) and the second conductive layer 46 are not covered by the first conductive layer 47 . On the surface of the area covered by the conductive layer 47, a third conductive layer 48 including the second conductive material M2 is formed. The third conductive layer 48 is formed by performing a second plating process using the second conductive material M2. The second plating treatment is, for example, electroless plating. The third conductive layer 48 is connected to the first surface 47b, the second surface 47c, the third surface 47d of the first conductive layer 47, and the region of the second conductive layer 46 that is not covered by the first conductive layer 47. formed in such a way that the surfaces meet. During this process, the thickness of the third conductive layer 48 is thicker than the thickness of the surface layer portion 42 of the ground layer 40 in the finished product. Next, as shown in (f) of FIG. 10 , unnecessary parts of the second conductive layer 46 and unnecessary parts of the third conductive layer 48 are removed by a semi-additive method called flash etching or fast etching. Parts and unnecessary parts of the organic film portion 51 are removed. Specifically, the portion of the second conductive layer 46 that is not covered by the first conductive layer 47 or the third conductive layer 48 (unnecessary portion of the second conductive layer 46 ), the third conductive layer 48 is provided on the The portion on the surface of the unnecessary portion of the second conductive layer 46 (unnecessary portion of the third insulating substrate 48 ) and the portion of the organic film portion 51 located at the unnecessary portion of the second conductive layer 46 and the first insulating substrate The portion between 10 (unnecessary portion of the organic film portion 51 ) is removed. During this process, the thickness of the portion of the third conductive layer 48 provided on the surfaces of the first surface 47b, the second surface 47c, and the third surface 47d of the first conductive layer 47 is reduced. When the etching process is completed, the third conductive layer 48 and the second conductive layer 46 form the surface layer portion 42 that surrounds the body portion 41 of the ground layer 40 in a ring shape. Thereby, the ground layer 40 is formed, and the first portion 50a of the organic film 50 is formed. In the present embodiment, "flash etching (fast etching)" refers to removing the entire thin metal seed layer provided for pattern plating by etching when a semi-additive method is used. . Next, as shown in (g) of FIG. 10 , on the upper surface of the ground layer 40 (the first surface 47b of the first conductive layer 47 ) and the left and right side surfaces (the second surface 47c and the third surface of the first conductive layer 47 ) At the surface 47d), the material of the organic film 50 is applied. Thereby, the organic film portion 52 surrounding the ground layer 40 from the three directions is formed. The organic film portion 52 includes the second portion 50b, the third portion 50c, and the fourth portion 50d of the organic film 50 described above. As the organic film portion 52 is formed, the organic film portion 52 and the above-described organic film portion 51 form an organic film 50 that surrounds the surface layer portion 42 in a ring shape from the outer peripheral side. As described above, in this modification, the first portion 50a of the organic film 50 is connected to the third portion 50c and the fourth portion 50d of the organic film 50, respectively. After that, similarly to the printed wiring board 5 of the first embodiment, the second insulating base material 20 is laminated on the first insulating base material 10 and the ground layer 40 . Moreover, the wiring 60 and the organic film 70 are manufactured by the same method as the manufacturing method of the ground layer 40 and the organic film 50 of this modification. Finally, the solder resist layer 30 is provided. (Second Embodiment) Next, a second embodiment will be described. The second embodiment is different from the first embodiment in that each of the ground layer 40 and the wiring 60 is provided with a layer having a double organic coating. Configurations other than the configuration described below are the same as those of the first embodiment. FIG. 11 is a sectional view showing the printed wiring board 5A of the second embodiment. In the present embodiment, the printed wiring board 5A includes the organic film 91 and the organic film 92 in addition to the configuration of the printed wiring board 5 of the first embodiment. The organic film 91 is formed in a ring shape covering the organic film 50 from the outer peripheral side. The organic film 91 is provided between the organic film 50 and the first insulating base material 10 and between the organic film 50 and the second insulating base material 20 . Similarly, the organic film 91 is formed in a ring shape covering the organic film 70 from the outer peripheral side. The organic film 92 is provided between the organic film 70 and the second insulating base material 20 and between the organic film 70 and the solder resist layer 30 . In the present embodiment, the organic films 50 and 70 are functional layers that suppress ion migration of the second conductive material M2 as described above. The organic films 50 and 70 are formed, for example, by applying a chelating agent, a thiol agent, or the like. Each of the organic films 50 and 70 is one example of the "first organic film". On the other hand, the organic films 91 and 92 are functional layers for improving the adhesiveness (bonding) between the organic films 50 and 70 and the insulating substrates 10 and 20 or the solder resist layer 30 . The organic films 91 and 92 are formed of materials different from those of the organic films 50 and 70 . The organic films 91 and 92 are formed of a material that is easier to adhere to the insulating substrates 10 and 20 or the solder resist layer 30 than the organic films 50 and 70 . The organic films 91 and 92 are formed by, for example, a silane coupling agent. Each of the organic films 91 and 92 is one example of the "second organic film". According to such a configuration, even when the organic films 50 and 70 are provided in order to suppress ion migration, corrosion, etc., the ground layer 40 or the wiring 60 and the insulating substrates 10 and 20 or the resistance The adhesion between the flux layers 30 is improved. Thereby, the long-term reliability of the printed wiring board 5A can be further improved. (3rd Embodiment) Next, 3rd Embodiment is demonstrated. The third embodiment is different from the first embodiment in that a through hole 95 for connecting the ground layer 40 and the wiring 60 is provided. Configurations other than the configuration described below are the same as those of the first embodiment. FIG. 12 is a cross-sectional view showing the printed wiring board 5B of the third embodiment. Fig. 12 shows a part of the structure of the printed wiring board 5B is extracted and shown. In this embodiment, the printed wiring board 5B is provided with the through hole 95 in addition to the structure of the printed wiring board 5 of the first embodiment. In the example shown in FIG. 12 , the printed wiring board 5B includes the ground layer 40 , the wiring 60 , and the through hole 95 for connecting the ground layer 40 and the wiring 60 . However, the through hole 95 is not limited to the through hole for connecting the ground layer 40 and the wiring 60, but may also be a through hole for connecting the wiring 60 for a plurality of signals. In this case, in the following description, "ground layer 40", "body portion 41", and "surface layer portion 42" may be replaced by "wiring 60", "body portion 61", and "surface layer portion 62", respectively. . The through hole 95 is one example of the "conductive connection portion". However, the "conductive connection portion" may be a through hole or the like. The through hole 95 is interposed between the ground layer 40 and the wiring 60 in the Z direction. That is, the through hole 95 overlaps the ground layer 40 in the Z direction, and overlaps the wiring 60 in the Z direction. The through hole 95 is provided inside the second insulating base material 20 and extends in the Z direction inside the second insulating base material 20 . The through hole 95 is formed by, for example, the first conductive material M1. The through hole 95 is an end in the Z direction, and includes a first end 95a and a second end 95b positioned on the opposite side of the first end 95a. The first end portion 95 a of the through hole 95 is in contact with the second portion 42 b of the surface layer portion 42 of the ground layer 40 . The second end portion 95b of the through hole 95 is in contact with the main body portion 61 and the surface layer portion 62 of the wiring 60 . Thereby, the through holes 95 electrically connect the ground layer 40 and the wiring 60 . According to this configuration, since the through hole 95 and the surface layer portion 42 of the ground layer 40 are connected, the current flowing in the surface layer portion 62 of the wiring 60 can be efficiently guided to the ground layer 40 . 42 of the surface layer. Thereby, the transmission loss can be further reduced, and the transmission characteristic can be improved. (Fourth Embodiment) Next, a fourth embodiment will be described. The fourth embodiment is different from the third embodiment in that the through hole 95 includes the surface layer portion formed of the second conductive material M2. Configurations other than the configuration described below are the same as those of the third embodiment. FIG. 13 is a sectional view showing the printed wiring board 5C of the fourth embodiment. In the present embodiment, the through hole 95 includes a main body portion 96 and a surface layer portion 97 . The main body portion 96 is located between the second portion 42 b of the surface layer portion 42 of the ground layer 40 and the main body portion 61 of the wiring 60 in the Z direction. The main body portion 96 extends in the Z direction inside the second insulating base material 20 . In this embodiment, the main body portion 96 is in contact with the main body portion 61 of the wiring 60 . For example, the main body portion 96 includes a bottom surface 96a facing the ground layer 40 and a peripheral surface 96b extending from the peripheral edge portion of the bottom surface 96a toward the wiring 60 . The main body portion 96 is formed of the first conductive material M1. The main body portion 96 is one example of the "third conductive portion". The surface layer portion 97 is formed of the second conductive material M2. The surface layer portion 97 is one example of the "fourth conductive portion". The surface layer portion 97 includes a first portion 97a and a second portion 97b. The first portion 97 a is located between the surface portion 42 of the ground layer 40 and the body portion 96 of the through hole 95 in the Z direction. The first portion 97 a extends in the X direction and the Y direction along the bottom surface 96 a of the main body portion 96 of the through hole 95 . The first portion 97a is in contact with the surface portion 42 of the ground layer 40 in the Z direction, and is in contact with the body portion 96 of the through hole 95 in the Z direction. The second portion 97b extends from the peripheral portion of the first portion 97a toward the surface layer portion 62 of the wiring 60 . The second portion 97b extends along the peripheral surface 96b of the body portion 96 of the through hole 95 . The second portion 97b is located between the second insulating base material 20 and the body portion 96 of the through hole 95 in the X direction and the Y direction. The second portion 97b is formed in an annular shape surrounding the main body portion 96 in the X direction and the Y direction. The second portion 97b is in contact with the first portion 62a of the surface layer portion 62 of the wiring 60 . That is, the first portion 97a and the second portion 97b form a current path with a small resistivity connecting the surface layer portion 42 of the ground layer 40 and the surface layer portion 62 of the wiring 60 . Next, the manufacturing method of the printed wiring board 5C of 4th Embodiment is demonstrated. FIG. 14 and FIG. 15 are diagrams showing one example of the manufacturing method of the printed wiring board 5C. First, the intermediate structure shown in (g) of FIG. 6 is formed by the same process as the printed wiring board 5 of 1st Embodiment demonstrated with reference to FIGS. 5 and 6. Then, as shown in (k) of FIG. 14, the metal foil 65 (for example, silver foil) containing the 2nd conductive material M2 is prepared. On one side (lower surface in FIG. 12 ) of the metal foil 65 , the material of the organic film 70 is applied, and a layered organic film portion 71 is formed. The organic film portion 71 is provided, for example, on the entire surface of one side of the metal foil 65 . Next, as shown in (l) of FIG. 14 , the metal foil 65 provided with the organic film portion 71 on one surface is attached to the first surface of the second insulating base material 20 of the above-mentioned intermediate structure 20a. The metal foil 65 of the second insulating base material 20 is attached by, for example, crimping, but other methods may also be employed. Thereby, the conductive layer 66 is formed with respect to the second insulating base material 20 . The conductive layer 66 is a planar layer extending in the X direction and the Y direction. Next, as shown in (m) of FIG. 14 , a protective film (resist) P2 is formed on the conductive layer 66 . Then, through the opening P2a formed in the protective film P2, the hole 20h penetrating the conductive layer 66, the organic film portion 71, and the second insulating base material 20 in the Z direction is provided. For example, in the process of forming the hole portion 20h, a part of the second portion 50b of the organic film 50 located at the region corresponding to the hole portion 20h is removed. As a result, the through hole 95 is in contact with the surface layer portion 42 of the ground layer 40 without interposing the organic film 50 in the subsequent process. When the through-hole 95 is used to connect the wiring 60 instead of the ground layer 40, or when the through-hole is connected not only to the ground layer 40 but also to the wiring 60, the through-hole 95 does not intervene organically. The film 70 is in contact with the surface layer portion 62 of the wiring 60 . Next, the protective film P2 is removed, and as shown in (n) of FIG. 14 , the inner surface of the hole portion 20h and the surface of the conductive layer 66 are subjected to a plating process using the second conductive material M2. Thereby, the conductive layer 67 including the second conductive material M2 is formed along the inner surface of the hole portion 20h. In addition, before providing the conductive layer 67, a process of "providing the same organic film as the organic film 50 (or the organic film 70) on the inner surface of the hole portion 20h" may be added. The conductive layer 67 forms the surface layer portion 97 of the through hole 95 and forms a part of the first portion 62 a of the surface layer portion 62 of the wiring 60 . Next, as shown in (o) in FIG. 15 , plating treatment using the first conductive material M1 is performed on the conductive layer 66 . In this way, the inside of the hole portion 20h is filled to form the body portion 96 of the through hole 95, and the conductive layer 68 including the first conductive material M1 is formed on the conductive layer 66 and expanded. The main body portion 96 formed by this process becomes the through hole 95 together with the surface layer portion 97 formed previously. Next, as shown in (p) in FIG. 15 , the conductive layer 66 , the organic film portion 71 , and the conductive layer 68 are patterned. In this way, the first portion 62 a of the surface layer portion 62 of the wiring 60 is formed from the conductive layer 66 , the body portion 61 of the wiring 60 is formed from the conductive layer 68 , and the first portion of the organic film 70 is formed from the organic film portion 71 . 1 part 70a. Then, as shown in (q) and (r) in FIG. 15 , by performing the same process as in (e) and (f) in FIG. 5 , the surface layer portion 62 of the wiring 60 and the organic film 70 are formed . According to such a configuration, at least a part of the current flowing from the wiring 60 to the ground layer 40 can flow through the surface layer portion 97 of the through hole 95 formed by the second conductive material M2 having a small resistivity. Thereby, the transmission characteristic of the printed wiring board 5 can be improved further. As mentioned above, although several embodiment and modification were described, the embodiment is not limited to the above-mentioned example. The above-mentioned several embodiments and modifications can also be combined with each other to be realized. According to at least one of the embodiments described above, the printed wiring board includes the first insulating portion, the second insulating portion, the first conductive portion, and the second conductive portion. The first conductive portion is located between the first insulating portion and the second insulating portion, and includes a first conductive material. The second conductive portion includes a first portion located between the first insulating portion and the first conductive portion, and includes a second conductive material whose resistivity is smaller than that of the first conductive material. According to such a configuration, it is possible to improve the transmission characteristics. Although several embodiments of the present invention have been described, these embodiments are presented as examples only, and are not intended to limit the scope of the present invention. These embodiments can be implemented in other various forms, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and modifications are included in the scope and gist of the invention, and are also included in the invention described in the scope of the patent application and its equivalents.

1: Memory system 5, 5A, 5B, 5C: Printed Wiring Board 10: 1st insulating base material (insulation part) 20: Second insulating base material (insulation part) 30: Solder resist layer (insulation part) 40: Ground plane 41: Body part (first conductive part) 42: Surface layer part (second conductive part) 50: Organic film (first organic film) 60: Wiring 61: Main body part (first conductive part) 62: Surface layer part (second conductive part) 70: Organic film (first organic film) 91: Organic film (second organic film) 92: Organic film (second organic film) 95: Through hole (connection part) 96: Main body part (third conductive part) 97: Surface layer part (4th conductive part)

FIG. 1 is a block diagram showing the configuration of the memory system of the first embodiment connected to the host device. 2 is a perspective cross-sectional view showing the printed wiring board of the first embodiment. [Fig. 3] is a cross-sectional view taken along the line F3-F3 of the printed wiring board shown in Fig. 2. [Fig. [Fig. 4] is a cross-sectional view taken along line F4-F4 of the printed wiring board shown in Fig. 2. [Fig. [FIG. 5(a) to FIG. 6(h)] are cross-sectional views showing one example of the manufacturing method of the printed wiring board according to the first embodiment. FIG. 7 is a diagram showing an example of the skin depth related to the printed wiring board of the first embodiment. 8 is a cross-sectional view showing a printed wiring board according to a modification of the first embodiment. 9( a ) to 10( g ) are cross-sectional views showing one example of a method for manufacturing a printed wiring board according to a modification of the first embodiment. Fig. 11 is a cross-sectional view showing the printed wiring board of the second embodiment Fig. 12 is a sectional view showing the printed wiring board of the third embodiment Fig. 13 is a sectional view showing the printed wiring board of the fourth embodiment [FIG. 14(k) to FIG. 15(r)] are cross-sectional views showing one example of the manufacturing method of the printed wiring board according to the fourth embodiment.

5: Printed wiring board 10: 1st insulating base material (insulation part) 10a: Side 1 10b: Side 2 20: Second insulating base material (insulation part) 20a: Side 1 20b: Side 2 21: Part 1 22: Part 2 23: Part 3 30: Solder resist layer (insulation part) 30a: Side 1 30b: Side 2 31: Part 1 32: Part 2 33: Part 3 40: Ground plane 41: Body part (first conductive part) 42: Surface layer part (second conductive part) 42a: Part 1 42b: Part 2 42c: Part 3 42d: Part 4 50: Organic film (first organic film) 50a: Part 1 50b: Part 2 50c: Part 3 50d: Part 4 60: Wiring 61: Main body part (first conductive part) 62: Surface layer part (second conductive part) 62a: Part 1 62b: Part 2 62c: Part 3 62d: Part 4 70: Organic film (first organic film) 70a: Part 1 70b: Part 2 70c: Part 3 70d: Part 4 M1: 1st conductive material M2: Second conductive material Sa, Sb, Sc, Sd: gap T1, T2a, T2b, T2c, T2d, T3, T4a, T4b, T4c, T4d: Thickness W1: Wide

Claims (18)

A printed wiring board, comprising: a first insulating part; and a second insulating part; and a first conductive part, located between the first insulating part and the second insulating part, and comprising a first conductive material; and the second conductive portion, including a first portion located between the first insulating portion and the first conductive portion, in contact with the first conductive portion, and extending along the first conductive portion, and including A second conductive material having a lower resistivity than the first conductive material; and a first organic film, at least a part of which is located between the second conductive portion and the first insulating portion, and the second insulating portion, It is located in the outer vicinity of the said printed wiring board rather than the said 1st insulating part in the thickness direction of the said printed wiring board. The printed wiring board according to claim 1, further comprising a pad exposed to the outside of the printed wiring board, and the first conductive portion and the second conductive portion are connected to the pad . The printed wiring board according to claim 1 or 2, wherein the thickness of the first portion of the second conductive portion in the thickness direction of the printed wiring board is greater than that in the thickness direction of the printed wiring board. The thickness of the above-mentioned first conductive portion is thinner. The printed wiring board according to claim 1 or 2, wherein the second conductive portion includes a portion located between the second insulating portion and the first conductive portion, in contact with the first conductive portion, and along the A second portion extending along the first conductive portion. The printed wiring board according to claim 4, wherein the second conductive portion includes a direction that is in contact with the first conductive portion from a direction different from the first portion and the second portion and extends along the direction of the first conductive portion. A third portion extending from the first conductive portion. The printed wiring board according to claim 5, wherein the third portion extends in the thickness direction of the printed wiring board, and connects the first portion and the second portion. The printed wiring board according to claim 1 or 2, wherein the second conductive portion is formed in a ring shape surrounding the first conductive portion. The printed wiring board according to claim 1 or 2, wherein the first conductive material contains copper, and the second conductive material contains silver. The printed wiring board according to claim 1 or 2, further comprising: a second organic film, at least a part of which is positioned on the first organic film A material different from the first organic film is contained between the film and the first insulating portion. The printed wiring board according to claim 1 or 2, further comprising a conductive connecting portion, wherein the connecting portion extends in the thickness direction of the printed wiring board inside the second insulating portion and the second conductive portion includes a second portion located between the first conductive portion and the connecting portion and in contact with the connecting portion. The printed wiring board according to claim 10, wherein the connecting portion includes: a third conductive portion that includes the first conductive material; and a fourth conductive portion that is located between the third conductive portion and the The second conductive material is included between the second conductive parts, and a part of the second conductive part is in contact with the fourth conductive part. A printed wiring board, comprising: a first insulating part; and a second insulating part; and a first conductive part, located between the first insulating part and the second insulating part, and comprising a first conductive material; and the second conductive portion, comprising a first portion positioned between the first insulating portion and the first conductive portion, and a second portion positioned between the second insulating portion and the first conductive portion, and contains resistivity compared to the aforementioned first A conductive material and a lower second conductive material; and a first organic film, at least a part of which is located between the second conductive portion and the first insulating portion. A memory system is provided with: a printed wiring board; and a controller, which is provided on the printed wiring board; and a semiconductor memory device, which is provided on the printed wiring board, and the printed wiring board is provided with a : a first insulating portion; and a second insulating portion, which is located in the vicinity of the outside of the printed wiring board with respect to the first insulating portion in the thickness direction of the printed wiring board; and a first conductive portion, which is located A first conductive material is included between the first insulating portion and the second insulating portion; and the second conductive portion is located between the first insulating portion and the first conductive portion and is connected to the first conductive portion. 1. a first portion extending along the first conductive portion in contact with the conductive portion, and comprising a second conductive material having a resistivity smaller than that of the first conductive material; and a first organic film, at least a part of which is The position is between the second conductive portion and the first insulating portion, and the first conductive portion and the second conductive portion form a wiring that is connected to the controller. The memory system of claim 13, wherein, The system is further provided with an external connection terminal that can be connected to the host device, and the wiring is a wiring between the controller and the external connection terminal, or is a connection between the controller and the semiconductor memory device. wiring. A method of manufacturing a printed wiring board, comprising: forming a first organic film on a first insulating portion, and forming a second conductive material having a resistivity smaller than that of a first conductive material on the first organic film a second conductive layer of material; and forming a first conductive layer containing the first conductive material on the second conductive layer; and forming a third conductive layer containing the second conductive material on the first conductive layer ; and forming a second insulating portion that covers the first conductive layer, the second conductive layer, and the third conductive layer from the side opposite to the first insulating portion. The method for manufacturing a printed wiring board according to claim 15, wherein the first conductive layer is formed by plating. The method for manufacturing a printed wiring board according to claim 15 or 16, wherein the first conductive layer includes a first surface oriented on the opposite side of the second conductive layer, and a surface oriented differently from the first surface The second side of the direction, with and the third surface facing the opposite side of the second surface, the third conductive layer is formed so as to be in contact with the first surface, the second surface and the third surface of the first conductive layer configuration. The method for producing a printed wiring board according to claim 15 or 16, wherein the third conductive layer is formed by electroless plating.

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