TWI766514B - Electronic device and powering method thereof - Google Patents

Abstract

An electronic device includes a power management unit, a regulator, a clock generator, and a digital circuit. The power management unit receives a wakeup instruction to generate a first control signal and a second control signal. The regulator generates a supply voltage according to the first control signal. The clock generator generates a clock signal having a first frequency according to the second control signal, and the clock signal has a second frequency in a predetermined period after the clock signal has been generated. The digital circuit is powered by the supply voltage and operates according to the clock signal.

Description

Electronic device and power supply method thereof

The present invention relates to an electronic device and a power supply method thereof, and in particular, to an electronic device that accelerates wake-up from a low power consumption mode and a power supply method thereof.

On an integrated circuit designed with low power consumption, a voltage regulator (regulator) that supplies power to the integrated circuit will switch supply modes according to different output load requirements. Usually in the state of high output current capability, the voltage regulator and its bias circuit must consume high quiescent current to maintain the stability of the output current and voltage of the voltage regulator. When the system enters the sleep mode, since the output current demand of the voltage regulator becomes lower, the system will operate the voltage regulator in a low power consumption mode, so that its quiescent current consumption is reduced, thereby reducing the power consumption when the system is idle. . Therefore, a user of the system can operate the system in a high-efficiency mode when the system needs computing, and operate in a low-power consumption mode when the system is idle, thereby achieving the purpose of saving power.

However, the time required to switch from the low-power mode to the high-power mode is a design focus of a low-power integrated circuit, because the faster the switch to the high-power mode, the faster the computing task can be completed, so it is necessary to reduce the system Time required to return from sleep mode to normal working mode.

In view of this, the present invention provides an electronic device including a power management unit, a voltage regulator, a clock generator and a digital circuit. The power management unit receives a wake-up command to generate a first control signal and a second control signal. The voltage regulator generates a supply voltage according to the first control signal. The clock generator generates a clock signal with a first frequency according to the second control signal, and at a predetermined time after generating the clock signal, the clock signal has a second frequency. The digital circuit receives the supply voltage for power supply, and operates according to the clock signal.

According to an embodiment of the present invention, the first frequency is lower than the second frequency, and when the clock generator generates the clock signal according to the first control signal, the clock signal has the first frequency, The clock signal gradually rises from the first frequency to the second frequency after the predetermined time after the clock signal is generated.

According to an embodiment of the present invention, when the power management unit receives the wake-up command, the electronic device is restored from a low power consumption mode to a normal operation mode, wherein the power management unit uses the first control signal to Wake up the above voltage regulator to the above high performance mode.

According to an embodiment of the present invention, when the electronic device operates in the low power consumption mode, the clock generator stops generating the clock signal.

According to an embodiment of the present invention, the above-mentioned digital circuit includes a central processing unit and a peripheral device.

The present invention further provides a power supply method for supplying power to a digital circuit, including receiving a wake-up command; according to the wake-up command, generating a supply voltage and a clock signal, wherein the clock signal is at a predetermined time, from a The first frequency is changed to a second frequency; and the supply voltage and the clock signal are provided to the digital circuit, so that the digital circuit is powered by the supply voltage and operates according to the clock signal.

According to an embodiment of the present invention, the first frequency is lower than the second frequency, and within the predetermined time, the clock signal gradually increases from the first frequency to the second frequency.

According to another embodiment of the present invention, the first frequency is lower than the second frequency, and when the clock generator generates the clock signal according to the first control signal, the clock signal has the first frequency , wherein the above-mentioned clock signal changes from the above-mentioned first frequency to the above-mentioned second frequency after the above-mentioned predetermined time after the above-mentioned clock signal is generated.

According to an embodiment of the present invention, before the step of receiving the wake-up command, the clock signal is not generated.

According to an embodiment of the present invention, the above-mentioned digital circuit includes a central processing unit and a peripheral device.

The following descriptions are examples of the present invention. Its purpose is to illustrate the general principles of the present invention, and should not be regarded as a limitation of the present invention. The scope of the present invention should be defined by the scope of the patent application.

It will be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and/or sections, these elements, components, regions , layer, and/or section should not be limited by these terms, and these terms are only used to distinguish between different elements, components, regions, layers, and/or sections. Thus, a first element, component, region, layer, and/or section discussed below could be termed a second element, component, region, layer, and/or section without departing from the teachings of some embodiments of the present disclosure. and/or parts.

Notably, the following disclosure may provide multiple embodiments or examples for practicing various features of the present invention. The specific component examples and arrangements described below are only used to briefly and briefly illustrate the spirit of the present invention, and are not intended to limit the scope of the present invention. Furthermore, the following description may reuse the same reference numerals or words in multiple instances. However, the purpose of re-use is merely to provide a simplified and clear description, and not to limit the relationship between the various embodiments and/or configurations discussed below. Furthermore, the description below that a feature is connected to, coupled to and/or formed on another feature, etc., may actually encompass a number of different embodiments, including that the feature is in direct contact, or includes other additional The features are formed between the features, etc., such that the features are not in direct contact.

FIG. 1 shows a block diagram of an electronic device according to an embodiment of the present invention. As shown in FIG. 1 , the electronic device 100 includes a power management unit 110 , a voltage regulator 120 , a clock generator 130 and a digital circuit 140 .

According to an embodiment of the present invention, when the electronic device 100 returns from the sleep mode to the normal mode, the power management unit 110 receives the wake-up command INS and generates the first control signal SC1 and the second control signal SC2. The voltage regulator 120 receives the first control signal SC1 and generates the supply voltage VS according to the first control signal SC1.

According to an embodiment of the present invention, when the electronic device 100 operates in the sleep mode, the voltage regulator 120 also operates in the low power consumption mode and provides the supply voltage VS. When the voltage regulator 120 receives the first control signal SC1, the voltage regulator 120 recovers from the low power consumption mode to the high power mode, and maintains the supply voltage VS, wherein the voltage regulator 120 is capable of supplying current when operating in the high power mode , higher than the ability of the voltage regulator 120 to supply current when operating in a low power consumption mode.

The clock generator 130 generates the clock signal CLK with the first frequency F1 according to the second control signal SC2, and changes the frequency of the clock signal CLK at a predetermined time T after the clock signal CLK with the first frequency F1 is generated Change to the second frequency F2. According to an embodiment of the present invention, the clock generator 130 is powered by the supply voltage VS provided by the voltage regulator 120 . According to many embodiments of the present invention, the clock signal CLK can gradually rise from the first frequency F1 to the second frequency F2 within a predetermined time T after passing through a plurality of frequencies, where the clock signal CLK is used at the predetermined time T Herein, the change from the first frequency F1 to the second frequency F2 is explained as an illustration, and is not limited to this in any form.

The digital circuit 140 is powered by the supply voltage VS provided by the voltage regulator 120 and operates according to the clock signal CLK. According to many embodiments of the present invention, the digital circuit 140 includes a central processing unit, peripheral devices, and any other circuit elements that require a clock signal for operation.

FIG. 2 is a timing diagram of an electronic device according to an embodiment of the present invention. As shown in FIG. 2, the electronic device 100 of FIG. 1 operates in the sleep mode 201 between the first time T1 and the second time T2; operates in the normal working mode 203 at the third time T3 and the fourth time T4; The wake-up mode 202 is operated between the second time T2 and the third time T3. In other words, the time between the second time T2 and the third time T3 is equivalent to the wake-up time required for the electronic device 100 to wake up from the sleep mode 201 to the normal operation mode 203 .

As shown in FIG. 2, the voltage regulator 120 in FIG. 1 corresponds to the electronic device 100 operating in a sleep mode 201, a wake-up mode 202, and a normal operation mode 203, and operates in a low-power mode 211, a conversion mode 212, and a high-efficiency mode, respectively In the energy mode 213 , the clock signal CLK generated by the clock generator 130 is shown as the first time sequence 220 .

According to an embodiment of the present invention, when the electronic device 100 operates in the sleep mode 201 , the voltage regulator 120 operates in the low power consumption mode 211 . In order to further reduce the power consumption of the sleep mode 201 of the electronic device 100 and reduce the load of the voltage regulator 120, the clock generator 130 stops generating the clock signal CLK between the first time T1 and the second time T2. In other words, between the first time T1 and the second time T2, there is no clock signal CLK, so that the digital circuit 140 also stops working.

According to another embodiment of the present invention, when the power management unit 110 receives the wake-up command INS at the second time T2 , it means that the electronic device 100 enters the wake-up mode 202 and the voltage regulator 120 enters the conversion mode 212 . Since the voltage regulator 120 needs a period of wake-up time to recover from the low-power consumption mode 211 to the high-performance mode 213 , the second time T2 to the third time T3 may be the wake-up time of the voltage regulator 120 .

As shown in FIG. 2, when the voltage regulator 120 enters the conversion mode 212, the clock generator 130 immediately starts to generate the clock signal CLK with the first frequency F1, and at the third time T3 (ie, the electronic device 100 enters the clock signal CLK) Before the high-efficiency mode 203), the frequency of the clock signal CLK rises to a second frequency F2, wherein the second frequency F2 is greater than the first frequency F1.

According to an embodiment of the present invention, the frequency of the clock signal CLK gradually increases from the first frequency F1 to the second frequency F2 during the second time T2 and the third time T3. According to another embodiment of the present invention, the frequency of the clock signal CLK is the first frequency F1 at the second time T2 and the second frequency F2 at the third time T3. In other words, when the voltage regulator 120 enters the high-efficiency mode 213 at the third time T3, the frequency of the clock signal CLK changes from the first frequency F1 to the second frequency F2.

According to an embodiment of the present invention, when the voltage regulator 120 operates in the high-efficiency mode 213, the digital circuit 140 operates according to the clock signal CLK of the second frequency F2. When the voltage regulator 120 operates in the conversion mode 212, the digital circuit 140 wakes up according to the clock signal CLK whose frequency is lower than the second frequency F2.

In other words, when the voltage regulator 120 operates in the conversion mode 212 , the digital circuit 140 returns to normal operation according to the down-converted clock signal CLK, and when the voltage regulator 120 operates in the high-efficiency mode 213 , the digital circuit 140 returns to normal operation. 140 can operate with the highest second frequency F2.

FIG. 3 is a timing diagram of an electronic device according to another embodiment of the present invention. As shown in FIG. 3 , the clock signal CLK generated by the clock generator 130 is shown as the second timing 320 , and the clock generator 130 does not start to generate the clock signal CLK until the third time T3 . In other words, in FIG. 3 , the clock generator 130 starts to generate the clock signal CLK when the voltage regulator 120 enters the high-efficiency mode 213 .

Comparing the second sequence 320 of FIG. 3 with the first sequence 220 of FIG. 2 , it can be seen that the first sequence 220 of FIG. 2 is generated earlier than the second sequence 320 of FIG. 3 . Since the time required for the digital circuit 140 to recover to normal operation is fixed, starting the wake-up earlier is beneficial for the digital circuit 140 to start normal operation earlier.

In other words, because in FIG. 2 , the clock generator 130 generates the clock signal CLK at the second time T2 when the voltage regulator 120 enters the conversion mode 212 , instead of waiting for the voltage regulator 120 to enter the high-efficiency mode 213 The clock signal CLK is not generated until the third time T3, so the digital circuit 140 can also perform the wake-up operation during the second time T2 to the third time T3, so that the digital circuit 140 and the voltage regulator 120 can perform the wake-up process at the same time. Thus, the wake-up speed of the electronic device 100 is accelerated.

FIG. 4 is a flowchart showing a power supply method according to an embodiment of the present invention. The following description of the flowchart of FIG. 4 will be combined with the block diagram of FIG. 1 to illustrate in detail by way of example.

First, the power management unit 110 receives the wake-up command INS (step S41 ), and the voltage regulator 120 and the clock generator 130 respectively generate the supply voltage VS and the clock signal CLK according to the wake-up command INS (step S42 ). According to an embodiment of the present invention, the frequency of the clock signal CLK is changed from the first frequency F1 to the second frequency F2 within a predetermined time (ie, the second time T2 to the third time T3 ), wherein the first frequency F1 is less than the second frequency F2.

According to an embodiment of the present invention, the frequency of the clock signal CLK gradually increases from the first frequency F1 to the second frequency F2 within a predetermined time. According to another embodiment of the present invention, the clock signal CLK of the first frequency F1 is changed from the first frequency F1 to the second frequency F2 after a predetermined time has elapsed.

Next, the supply voltage VS and the clock signal CLK are provided to the digital circuit 140 (step S43 ), so that the digital circuit 140 is powered by the supply voltage VS and operates according to the clock signal CLK.

Although the embodiments of the present disclosure and their advantages have been disclosed above, it should be understood that those skilled in the art can make changes, substitutions and modifications without departing from the spirit and scope of the present disclosure. In addition, the protection scope of the present disclosure is not limited to the process, machine, manufacture, material composition, device, method, and steps in the specific embodiments described in the specification. Anyone with ordinary knowledge in the technical field can learn some implementations from the present disclosure. In the disclosure of the examples, it is understood that processes, machines, manufactures, compositions of matter, devices, methods and steps developed in the present or in the future, as long as substantially the same functions can be implemented or substantially the same results can be obtained in the embodiments described herein. Some embodiments of the present disclosure are used. Therefore, the protection scope of the present disclosure includes the above-mentioned processes, machines, manufactures, compositions of matter, devices, methods and steps. In addition, each claimed scope constitutes a separate embodiment, and the protection scope of the present disclosure also includes the combination of each claimed scope and the embodiments.

100: Electronics 110: Power Management Unit 120: Voltage regulator 130: Clock generator 140: Digital Circuits 201: Sleep Mode 202: wakeup mode 203: normal working mode 211: Low power mode 212: Convert mode 213: High Performance Mode 220: First Timing 320: Second Timing INS: wake-up command SC1: the first control signal SC2: The second control signal VS: Supply voltage CLK: clock signal F1: first frequency F2: Second frequency T1: The first time T2: Second time T3: The third time T4: Fourth time S41～S43: Step flow

FIG. 1 shows a block diagram of an electronic device according to an embodiment of the present invention; FIG. 2 shows a timing diagram of an electronic device according to an embodiment of the present invention; FIG. 3 is a timing diagram showing an electronic device according to another embodiment of the present invention; and FIG. 4 is a flowchart showing a power supply method according to an embodiment of the present invention.

100: Electronics

110: Power Management Unit

120: Voltage regulator

130: Clock generator

140: Digital Circuits

INS: wake-up command

SC1: the first control signal

SC2: The second control signal

VS: Supply voltage

CLK: clock signal

Claims (10)

An electronic device, comprising: a power management unit, which receives a wake-up command to generate a first control signal and a second control signal; a voltage regulator, which generates a supply voltage according to the first control signal; a clock generator a device that generates a clock signal with a first frequency according to the second control signal, and a predetermined time after generating the clock signal, the clock signal has a second frequency; and a digital circuit for receiving the The supply voltage provides power and operates according to the above-mentioned clock signal. The electronic device of claim 1, wherein the first frequency is lower than the second frequency, and when the clock generator generates the clock signal according to the first control signal, the clock signal has the first frequency , wherein after the above-mentioned clock signal is generated, the above-mentioned clock signal gradually rises from the above-mentioned first frequency to the above-mentioned second frequency after the above-mentioned predetermined time. The electronic device of claim 1, wherein when the power management unit receives the wake-up command, the electronic device recovers from a low power consumption mode to a normal operation mode, wherein the power management unit uses the first control signal, And wake up the voltage regulator to a high performance mode. The electronic device of claim 3, wherein when the electronic device operates in the low power consumption mode, the clock generator stops generating the clock signal. The electronic device of claim 1, wherein the digital circuit includes a central processing unit and a peripheral device. A power supply method for powering a digital circuit, comprising: receive a wake-up command; generating a supply voltage and a clock signal according to the wake-up command, wherein the clock signal changes from a first frequency to a second frequency at a predetermined time; and The supply voltage and the clock signal are provided to the digital circuit, so that the digital circuit is powered by the supply voltage and operates according to the clock signal. The power supply method of claim 6, wherein the first frequency is lower than the second frequency, and within the predetermined time, the clock signal gradually increases from the first frequency to the second frequency. The power supply method of claim 6, wherein the first frequency is lower than the second frequency, and when the clock generator generates the clock signal according to the first control signal, the clock signal has the first frequency , wherein the above-mentioned clock signal changes from the above-mentioned first frequency to the above-mentioned second frequency after the above-mentioned predetermined time after the above-mentioned clock signal is generated. The power supply method of claim 6, wherein before the step of receiving the wake-up command, the clock signal is not generated. The power supply method of claim 6, wherein the digital circuit includes a central processing unit and a peripheral device.

Images