TWI764475B - Enhancement Mode Gallium Nitride Device with P-type Doping Layer Electrode Offset - Google Patents

Abstract

The present invention provides an enhancement mode gallium nitride device with electrode offset of P-type doped layer, comprising: an aluminum gallium nitride layer, and a p-type gallium nitride doped layer formed on the aluminum gallium nitride layer ; And a gate metal, the P-type gallium nitride doped layer is displaced in parallel, so that part of the gate metal is plated on the P-type gallium nitride doped layer, and part of the gate metal is plated on the p-type gallium nitride doped layer. On the aluminum gallium nitride layer, the effects of reducing the gate leakage current and increasing the output current are achieved.

Description

Enhancement mode gallium nitride device with offset electrode of P-type doped layer

The present invention relates to an enhancement mode gallium nitride device with offset electrodes of P-type doped layers, in particular to a P-type doped gallium nitride device in which part of the gate electrode is plated on the doped layer and part of the gate electrode is plated on the aluminum gallium nitride layer Enhancement mode gallium nitride device with offset electrode.

Aluminum gallium nitride/gallium nitride enhancement mode high electron mobility transistors have attracted much attention in recent years. It is widely used in high-voltage, high-electronic components and high-efficiency power conversion systems. The large amount of two-dimensional electron gas generated by the heterojunction provides the component characteristics of high current and low impedance, and its superior material characteristics, as well as high breakdown. voltage, allowing the transistor to meet the needs of high frequency and high power operation. However, after considering the reliability of components and the need to simplify circuit design, enhancement-mode gallium nitride components are gradually replacing depletion-type components. In order to achieve the requirement of a threshold voltage greater than zero, many methods have been implemented, including gate injection. A transistor (gate injection transistor), a P-type doped layer doped with magnesium ions is grown above the energy barrier layer. This doped layer will raise the energy band of the channel region under the gate to above the Fermi level, resulting in The channel region cannot be occupied by electrons and forms a normally-off state. In order to solve the problem of current collapse, a P-type doped layer is added next to the drain electrode and conducts with the drain electrode, as shown in the second figure As shown, the current collapse voltage was successfully raised to 850V.

Another method to achieve an enhancement type device is to etch a part of the energy barrier layer to simplify the polarization effect and reduce the concentration of the two-dimensional electron gas to achieve an enhancement type device. In order to reduce the influence of gate leakage, increase A dielectric layer, as shown in the third figure.

Other enhancement-mode device fabrication methods, such as fluoride ion doping or selective oxidation of the barrier layer by N ₂ O plasma, have been proposed.

The conventional technology uses a layer of magnesium ion-doped P-type gallium nitride on the energy barrier layer to form an enhancement-mode gallium nitride element. Although it can successfully achieve the target that the threshold voltage is greater than zero, the principle is to deplete the P-type gallium nitride. The concentration of electron gas under GaN will therefore cause a significant drop in output current and, for power components, a drop in output power. In addition, in the application of high-power components, there is still the problem of excessive gate leakage. The forward gate leakage will reduce the gate voltage swing and cause driving losses. At the same time, the gate and p-type gallium nitride doping layer The Schottky junction between the gates will form a reverse biased state when a positive bias is applied to the gate, so the reverse gate leakage will cause energy loss when closing, and will also reduce the breakdown voltage.

Generally, the structure of using the P-type doped layer as the enhancement mode gallium nitride element is mostly only the residual P-type doped layer under the gate electrode. As shown in the fourth figure, the junction between the P-type doped layer and the aluminum gallium nitride can be seen. It is a p-i-n diode with two p-to-p connections. When the element is turned on, if the gate is given an excessive bias voltage, the depletion area of the junction will be reduced and the gate leakage will be generated, reducing the current output efficiency. In addition, the P-type doping The two-dimensional electron gas caused by the layer is excessively depleted, and the output current decreases.

The reason is that, in view of this, the inventor, adhering to years of rich experience in design, development and actual production in the related industry, researches and improves the existing structure and defects, and provides an enhancement mode gallium nitride device with a P-type doped layer electrode offset. , in order to achieve the purpose of better practical value.

In view of the above-mentioned shortcomings of the known technology, the main purpose of the present invention is to provide an enhancement mode gallium nitride device with offset P-type doping layer electrodes. The gallium nitride device is a new structure, which can effectively reduce the gate leakage current. As well as increasing output current, improving output power efficiency, high power amplifier linearity and reducing noise. .

In order to achieve the above object, according to a solution proposed by the present invention, an enhancement mode gallium nitride element with offset electrodes of a P-type doped layer is provided, which comprises: an aluminum gallium nitride layer, a p-type gallium nitride doped layer layer and a gate metal, wherein the p-type gallium nitride doped layer is formed on the aluminum gallium nitride layer; and the gate metal is parallel to the p-type gallium nitride doped layer, so that part of the The gate metal is plated on the P-type gallium nitride doped layer, and part of the gate metal is plated on the aluminum gallium nitride layer.

Preferably, a dielectric layer may be added between the gate metal and the P-type gallium nitride doped layer.

Preferably, the gate metal can be directly connected to the aluminum gallium nitride layer touch.

Preferably, the gate metal system can be used for parallel displacement of the P-type GaN doped layer through mask design.

Preferably, 50% of the gate metal system is plated on the P-type gallium nitride doped layer, and 50% of the gate metal system is plated on the aluminum gallium nitride layer.

Preferably, the P-type gallium nitride doped layer can be doped with magnesium ions.

The above summary, the following detailed description and the accompanying drawings are all for the purpose of further illustrating the manner, means and effect adopted by the present invention to achieve the predetermined object. The other objects and advantages of the present invention will be explained in the following descriptions and drawings.

1: GaN layer

2: Two-dimensional electron gas

3: Aluminum gallium nitride layer

4: P-type gallium nitride doped layer

5: Source

6: Drain pole

7: Gate

8: Dielectric layer

The first figure is a schematic diagram of the structure of the enhancement mode gallium nitride device with offset electrodes of the P-type doped layer of the present invention.

The second figure is a schematic diagram of a conventional hybrid drain-gate injection transistor.

The third figure is a schematic diagram of a conventional GaN enhancement mode device.

The fourth figure is a schematic diagram of the structure of a conventional enhancement mode gallium nitride device.

The following describes the embodiments of the present invention with specific examples, and those skilled in the art can easily understand the contents disclosed in this specification. Learn about the benefits and efficacy of this creation.

Please refer to the first figure, which is a schematic diagram of the enhancement mode gallium nitride device with offset P-type doped layer electrodes of the present invention. The present invention provides an enhancement mode GaN device design with offset P-type doped layers, which includes: : Gallium nitride layer 1 (GaN), two-dimensional electron gas 2 (2DEG), aluminum gallium nitride layer 3 (AlGaN), P-type gallium nitride doped layer 4 (P-GaN), source electrode 5 (S) , drain 6 (D), gate metal 7 (G) and dielectric layer 8, wherein the two-dimensional electron gas 2 is formed on the gallium nitride layer 1, and the aluminum gallium nitride layer 3 is formed on the two-dimensional electron gas 2, and the source electrode 5, the drain electrode 6 and the p-type gallium nitride doped layer 4 are formed on the aluminum gallium nitride layer 3, the p-type gallium nitride doped layer 4 of the present invention is doped with magnesium ions, And the gate metal 7 is parallelly displaced to the P-type gallium nitride doped layer 4, so that part of the gate metal 7 is plated on the P-type gallium nitride doped layer 4, and part of the gate metal 7 is plated on the nitride on the aluminum gallium layer 3.

In the above, compared with the traditional p-type gallium nitride enhancement mode element, the gate metal 7 is all designed on the p-type gallium nitride doped layer 4. The present invention designs the gate metal 7 to the p-type gallium nitride. The doping layer 4 is displaced in parallel, so that part of the gate metal 7 is on the p-type gallium nitride doped layer 4, and part of the gate metal 7 is plated on the aluminum gallium nitride layer 3, so as to reduce the gate caused by the p-i-n junction The leakage current path effectively reduces the energy loss caused by the gate leakage current.

In this embodiment, a dielectric layer 8 may be added between the gate metal 7 and the P-type gallium nitride doped layer 4 to reduce the gate leakage current.

In this embodiment, the gate metal 7 is in direct contact with the aluminum gallium nitride layer 3, so that the gate metal 7 can directly control the channel, and has the ability to generate more electricity. The effect of flow.

In this embodiment, the gate metal 7 is designed to perform parallel displacement to the P-type gallium nitride doped layer 4 through the mask design.

In this embodiment, 50% of the gate metal 7 series is plated on the P-type gallium nitride doped layer 4, and 50% of the gate metal 7 series is plated on the aluminum gallium nitride layer 4, which can be simultaneously It maintains the characteristics of the control element switching, and the effect of reducing the gate leakage current.

In summary, AlGaN/GaN high electron mobility field effect transistors are widely used in automotive electronics, power supplies, military communication systems, and in automotive electronics due to their high current density and high breakdown voltage. In the future, 5G mobile communication and the Internet era will play an important role. The gallium nitride optimized structure proposed by the present invention can effectively reduce the gate leakage current and increase the output current, improve the output power efficiency, the linearity of the high power amplifier and the effect of reducing noise.

In recent years, due to the rapid development of high technology, the specifications and demands in the fields of high-frequency communication and high-power components have been greatly increased. Among them, the high electron mobility transistor made of gallium nitride is regarded as the next generation to replace the role of metal oxide semiconductor because of its excellent material properties. However, for GaN transistors used in high-power components, the magnitude of the output current is bound to be an indicator. At the same time, the gate leakage current is also a factor that must be overcome. The gate leakage current will affect the performance and reliability of the components. The present invention utilizes offsetting the gate metal 7 and adding the dielectric layer 8 to effectively improve the gate leakage and increase the output current density. For the application of high-power components, in addition to reducing the energy loss when the components are turned off, the same It can also increase the gate voltage swing, thereby increasing the power tolerance. The magnitude of the gate leakage current is an important indicator for the quality of the power components, and is highly related to the output power efficiency, the linearity of the high power amplifier and the ability to reduce noise.

The above-mentioned embodiments are merely illustrative to illustrate the features and effects of the present invention, and are not intended to limit the scope of the substantial technical content of the present invention. Anyone skilled in the art can modify and change the above-mentioned embodiments without departing from the spirit and scope of creation. Therefore, the protection scope of the present invention should be as listed in the patent application scope described later.

1: GaN layer

2: Two-dimensional electron gas

3: Aluminum gallium nitride layer

4: P-type gallium nitride doped layer

5: Source

6: Drain pole

7: Gate

8: Dielectric layer

Claims (5)

An enhancement mode gallium nitride device with offset electrodes of a P-type doped layer, comprising: an aluminum gallium nitride layer; a p-type gallium nitride doped layer formed on the aluminum gallium nitride layer; and a The gate metal is shifted in parallel to the P-type gallium nitride doped layer, so that part of the gate metal is plated on the P-type gallium nitride doped layer, and part of the gate metal is plated on the nitride On the aluminum gallium layer, 50% of the gate metal system is plated on the P-type gallium nitride doped layer, and 50% of the gate metal system is plated on the aluminum gallium nitride layer. The enhancement mode gallium nitride device with offset P-type doped layer electrodes as described in item 1 of the claimed scope, wherein a dielectric layer is added between the gate metal and the P-type gallium nitride doped layer. The enhancement mode gallium nitride device with offset P-type doped layer electrodes as described in item 1 of the claimed scope, wherein the gate metal is in direct contact with the aluminum gallium nitride layer. The enhancement mode gallium nitride device with electrode offset of P-type doped layer as described in item 1 of the patent application scope, wherein the gate metal is designed to perform parallel displacement of the P-type gallium nitride doped layer through a mask design . The enhancement mode gallium nitride device with offset electrodes of the P-type doped layer as described in item 1 of the claimed scope, wherein the P-type gallium nitride doped layer is doped with magnesium ions.

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