TWI764189B - 包括內埋式半導體裝置的基板結構及其製造方法 - Google Patents

包括內埋式半導體裝置的基板結構及其製造方法

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Publication number
TWI764189B
TWI764189B TW109122847A TW109122847A TWI764189B TW I764189 B TWI764189 B TW I764189B TW 109122847 A TW109122847 A TW 109122847A TW 109122847 A TW109122847 A TW 109122847A TW I764189 B TWI764189 B TW I764189B
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Taiwan
Prior art keywords
conductive layer
conductive
electronic component
layer
carrier
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TW109122847A
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English (en)
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TW202135264A (zh
Inventor
陳建汎
廖玉茹
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日月光半導體製造股份有限公司
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Publication of TW202135264A publication Critical patent/TW202135264A/zh
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Abstract

本發明提供一種基板結構。該基板結構包括一互連結構、該互連結構上之一介電層、內埋於該介電層中之一電子組件，及穿過該介電層且鄰近於該電子組件而安置的一第一導孔。該互連結構包括具有一第一表面及與該第一表面相對之一第二表面的一載體、安置於該載體之該第一表面上的一第一導電層，及安置於該載體之該第二表面上的一第二導電層。該第一導電層及該第二導電層中的至少一者、及該第一導孔界定環繞該電子組件之一第一屏蔽結構。亦揭示一種製造一基板結構之方法。

Description

包括內埋式半導體裝置的基板結構及其製造方法
本發明大體而言係關於一種基板，且詳言之，係關於一種內埋有電子組件之基板。
內埋式基板技術將至少一個主動或被動電子組件納入基板之導電層內。導電層有助於內埋式電子組件的電互連或信號傳輸。內埋式基板被認為可以減小封裝尺寸，提高功率密度及改善裝置效能，因而變得愈來愈流行。
在一或多個實施例中，本發明提供一種基板結構。基板結構包括互連結構、互連結構上之介電層、內埋於介電層中之電子組件，及穿過介電層且鄰近於電子組件而安置的第一導孔。互連結構包括具有第一表面及與第一表面相對之第二表面的載體、安置於載體之第一表面上的第一導電層，及安置於載體之第二表面上的第二導電層。第一導孔及第一導電層及第二導電層中的至少一者界定環繞電子組件之第一屏蔽結構。
在一或多個實施例中，本發明提供一種半導體裝置封裝。半導體裝置封裝包括互連結構、互連結構上之介電層、內埋於介電層中之第一電子組件，及穿過介電層且鄰近於第一電子組件而安置的第一導孔。互連結構包括具有第一表面及與第一表面相對之第二表面的載體、安置於載體之第一表面上的第一導電層，及安置於載體之第二表面上的第二導電層。半導體裝置封裝進一步包括安置於第二導電層上之囊封層、內埋於囊封層中且電連接至第二導電層之第二電子組件。第一導電層及第一導孔界定環繞第一電子組件之第一屏蔽結構。
在一或多個實施例中，本發明提供一種製造基板結構之方法。該方法包括提供互連結構。互連結構包括具有第一表面及與第一表面相對之第二表面的載體、安置於載體之第一表面上的第一導電層，及安置於載體之第二表面上的第二導電層。該方法進一步包括將電子組件附接至互連結構，且鄰近於電子組件形成第一導孔。第一導孔電連接至第一導電層及第二導電層中的至少一者。
以下揭示內容提供用於實施所提供主題之不同特徵的許多不同實施例或實例。在下文描述組件及配置之具體實例。當然，此等組件及配置僅為實例且不意欲為限制性的。在本發明中，在以下描述中提及第一特徵形成在第二特徵上方或上可包括第一特徵與第二特徵直接接觸地形成的實施例，且亦可包括額外特徵可在第一特徵與第二特徵之間形成，使得第一特徵與第二特徵可能不直接接觸的實施例。另外，本發明可在各種實例中重複參考標號及/或字母。此重複係出於簡單及明晰之目的，且本身並不規定所論述之各種實施例及/或組態之間的關係。
下文詳細地論述本發明之實施例。然而，應瞭解，本發明提供可在廣泛多種特定情境中體現之許多適用的概念。所論述具體實施例僅為說明性的且並不限制本發明之範疇。
圖1為根據本發明之實施例的基板結構1之截面圖。基板結構1包括互連結構10、介電層11、12、電子組件13、14、導電層15、保護層16、電接點17、18。
互連結構10包括具有表面10d1及與表面10d1相對之表面10d2的載體10d。互連結構10進一步包括安置於表面10d1上之導電層10c1及安置於表面10d2上之導電層10c2。導孔10v穿過載體10d，且連接於導電層10c1及10c2之間。導孔10v朝向導電層10c1逐漸變窄。例如，導孔10v較接近於導電層10c1處的寬度實質上小於導孔10v較接近於導電層10c2處的寬度。
在一些實施例中，互連結構10可包括銅包覆層壓(CCL)基板。在一些實施例中，載體10d可包括封裝材料、預浸複合纖維(例如，預浸體)、硼磷矽玻璃(BPSG)、氧化矽、氮化矽、氮氧化矽、未經摻雜的矽玻璃(USG)、其中兩者或更多者的任何組合，或其類似者。在一些實施例中，載體10d可包括有機材料。在一些實施例中，載體10d可包括有機材料，該有機材料進一步包括諸如玻璃光纖之填充劑。在一些實施例中，載體10d可具有範圍為約35微米(μm)至約400 μm的厚度。
在一些實施例中，導電層10c1及10c2可各自包含銅(Cu)或其他導電材料，諸如鋁(Al)、鉻(Cr)、錫(Sn)、金(Au)、銀(Ag)、鎳(Ni)或不鏽鋼、另一金屬，或其中兩者或更多者的混合物、合金或其他組合。在一些實施例中，導電層10c1及10c2可各自具有範圍為約5 μm至約18 μm之厚度。
保護層18安置於導電層10c2上方，以囊封或覆蓋導電層10c2。在一些實施例中，保護層18可完全曝露或曝露至少一部分導孔10v及/或導電層10c2以用於電連接。在一些實施例中，保護層18可包括阻焊劑或防焊劑。
電子組件13及電子組件14安置於導電層10c1上方。電子組件13具有表面(或可被稱為主動表面)131、與表面131相對的表面(或可被稱為背面表面)132及在表面131與表面132之間延伸的側向表面(或可被稱為側向表面)133。
在一些實施例中，電子組件13可為晶片或晶粒，包括半導體基板、一或多個積體電路裝置及其中一或多個上覆互連結構。積體電路裝置可包括諸如電晶體之主動裝置，及/或諸如電阻器、電容器、電感器或其組合之被動裝置。
電子組件13經由介電層11附接至互連結構10。例如，介電層11可為或可包括膠或黏著層，且黏著於導電層10c1上之電子組件13的表面132。電子組件13在表面131上包括導電襯墊13p及導孔13v，以為基板結構1提供電互連或信號傳輸。電子組件14可具有與電子組件13類似的結構及配置，且下文出於簡單及明晰之目的省略掉類似描述。
介電層12安置於介電層11上，且環繞電子組件13及電子組件14。電子組件13及電子組件14內埋、囊封或覆蓋於介電層11及12中。
在一些實施例中，介電層11及介電層12中之每一者可包括層壓層或膜。在一些實施例中，介電層12可包括例如一或多個有機材料(例如，封裝材料、雙馬來醯亞胺三嗪(BT)、聚醯亞胺(PI)、聚苯并噁唑(PBO)、阻焊劑、味之素累積膜(ABF)、聚丙烯(PP)、環氧基材料，或其中兩者或更多者之組合)、無機材料(例如，矽、玻璃、陶瓷、石英，或其中兩者或更多者之組合)、液膜材料或乾膜材料，或其中兩者或更多者之組合。在一些實施例中，介電層11與介電層12之間的界面可經由掃描電子顯微鏡(SEM)或其他合適技術來觀測。在一些實施例中，第一介電層11的厚度可約為35 μm。
導電層15安置於介電層12上，且電連接至電子組件13之表面131上的導孔13v。在一些實施例中，導電層15可包括用於導電層10c1及10c2之如上文所列的材料。
保護層16安置於導電層15上，以完全曝露或曝露至少一部分導孔13v及/或導電層15以用於電連接。
電接點17(例如，焊球)安置於導孔13v及/或導電層15上，且可提供基板結構1與外部組件(例如，外部電路或電路板)之間的電連接。在一些實施例中，電接點17包括控制崩潰晶片連接(C4)凸塊、球狀柵格陣列(BGA)或平台柵格陣列(LGA)。
導孔11v安置於介電層11及12內。導孔11v穿過介電層11及12。導孔11v連接於導電層10c1及15之間。導孔11v經由導電層10c1與導孔10v連接。
如圖1中所示，屏蔽結構(標記為「SD1」)形成於基板結構1中，且環繞電子組件13及電子組件14。屏蔽結構SD1提供電磁干擾(EMI)保護以防止電子組件13及電子組件14受其他電子組件干擾，且反之亦然。例如，屏蔽結構SD1可由導電層10c2、導孔10v、導孔11v及導電層15界定。在一些實施例中，屏蔽結構SD1可包括兩個屏蔽結構，一個屏蔽結構環繞電子組件13，且另一屏蔽結構環繞電子組件14。這樣可以進一步防止電子組件13及電子組件14干擾到彼此。
在一些實施例中，導電層10c2可為導電薄膜。在一些實施例中，導電層10c2可接地。在一些實施例中，導電層10c2可未經圖案化。例如，導電層10c2中銅的覆蓋百分比(或密度)可高於導電層10c1中銅的覆蓋百分比(或密度)。
在一些實施例中，導電層10c1可為屏蔽結構的一部分，且導電層10c2可以圖案化。結果，屏蔽結構較接近於電子組件13及14，這必然會引入寄生電容。
導孔11v朝向導電層10c1逐漸變窄。例如，導孔11v較接近於導電層10c1處的寬度實質上小於導孔11v較接近於導電層15處的寬度。導孔11v及導孔10v朝向相反方向逐漸變窄。導孔11v及導孔10v彼此相向逐漸變窄。
在現有的一些做法中，不同於根據本發明具有內埋式電子組件(亦即，電子組件13)及內埋式屏蔽結構(亦即，屏蔽結構SD1)的基板結構1，基板結構1可封裝於封裝本體中，且屏蔽層或框可例如藉由模製及濺鍍操作而提供於封裝本體之外表面上。其操作成本高且費時。
比較而言，在本發明中，屏蔽結構SD1內建於基板結構1中，這樣減小封裝尺寸。屏蔽結構SD1的製造方式為在介電層12中形成導孔，以連接至互連結構10之導電層10c2及導孔10v。用於形成屏蔽結構SD1之成本低於用於在封裝本體之外表面上形成屏蔽層或框之成本。
在一些其他現有做法中，電子組件(諸如電子組件13)可安置於載體10d中。導孔10v及導電層10c2可提供EMI保護。然而，為了形成導孔，在鑽孔程序中對不同材料進行鑽孔，這樣可能導致載體10d中殘餘有大量玻璃纖維。此類殘餘玻璃纖維可能導致稍後形成的導孔斷開電連接。相比之下，在根據本發明之電子組件13安置於互連結構10上方的情況下，可以解決現有做法中的問題。
在基板結構1中，導電層10c2為屏蔽結構SD1的一部分且可接地，而導電層10c1經圖案化，且可提供信號傳輸。例如，導電層10c1經圖案化，且可包含用於信號傳輸的導電跡線部分10t。導電層10c2可包括接地層或屏蔽部分10s以提供EMI保護。
圖2A為根據本發明之實施例的EMI屏蔽機構之示意性透視圖。在一些實施例中，圖2A中之結構可為圖1中之基板結構1的一部分。出於簡單及明晰之目的，僅示出了導孔11v、電子組件13及導電層10c2。
如圖2A中所示，多個導孔(或導電柱)11v環繞電子組件13。導電柱11v經由互連結構10中之導孔(如圖1中所展示)電連接至導電層10c2，且為電子組件13提供EMI保護。
導電柱11v與電子組件13間隔開。導電柱11v鄰近於電子組件13而安置。導電柱11v與電子組件13側向間隔開。例如，電子組件13之表面133面朝導孔11v。
在一些實施例中，與互連結構10中之導孔10v(如圖1中所展示)相關聯的導電柱11v的數量、其結構及其部署型樣可取決於所要應用。
圖2B為根據本發明之另一實施例的EMI屏蔽機構之示意性透視圖。在一些實施例中，圖2B中之結構可為圖1中之基板結構1的一部分。出於簡單及明晰之目的，僅示出了導電壁11w、電子組件13及導電層10c2。
如圖2B中所示，導電壁11w環繞電子組件13。電子組件13之表面133面朝導電壁11w。導電壁11w經由互連結構10中之導孔10v(如圖1中所展示)電連接至導電層10c2，且為電子組件13提供EMI保護。
圖3為根據本發明之另一實施例的基板結構3之截面圖。在一些實施例中，圖3中之基板結構3類似於圖1中之基板結構1，且其間的差異在下文描述。
互連結構30包括導電層30c1及導電層30c2。導電層30c1部分圖案化。例如，導電層30c1中位於電子組件14正下方的部分(標記為「30t」)經圖案化。在一些實施例中，導電層30c1包括屏蔽部分30s及導電跡線部分30t。導電層30c1之屏蔽部分30s及導孔11v界定屏蔽結構(標記為「SD2」)，用於為電子組件13提供EMI保護。導電層30c1之導電跡線部分30t與屏蔽部分30s處於相同的位準或層。
類似於導電層30c1，導電層30c2部分圖案化。例如，導電層30c2中位於電子組件13正下方的部分(標記為「30t」)經圖案化。在一些實施例中，導電層30c2包括屏蔽部分30s及導電跡線部分30t。導電層30c2之屏蔽部分30s、導孔10v及導孔11v界定屏蔽結構(標記為「SD3」)，用於為電子組件14提供EMI保護。導電層30c2之導電跡線部分30t與屏蔽部分30s處於相同的位準或層。
屏蔽結構SD3及SD4進一步防止電子組件13及電子組件14干擾到彼此。
圖4為根據本發明之另一實施例的基板結構4之截面圖。在一些實施例中，圖4中之基板結構4類似於圖1中之基板結構1，且其間的差異在下文描述。
互連結構40包括導電層40c1及導電層40c2。導電層40c2、導孔10v及導孔11v界定屏蔽結構(標記為「SD1」)，用於為電子組件13及14提供EMI保護。導電層40c1及導孔11v界定屏蔽結構(標記為「SD5」)，用於為電子組件13及14提供EMI保護。屏蔽結構SD5形成於屏蔽結構SD1內。屏蔽結構SD1及SD5一起形成用於電子組件13及14之兩層屏蔽結構。
圖5A為根據本發明之另一實施例的基板結構5之截面圖。在一些實施例中，圖5A中之基板結構5類似於圖1中之基板結構1，且其間的差異在下文描述。
基板結構5包括安置於互連結構50上之電子組件51。電子組件51安置於互連結構50相對於電子組件13之相對側上。電子組件51經由電接點51c電連接至導電層50c2。囊封層52安置於保護層18之頂表面上，以覆蓋或囊封電子組件51。在一些實施例中，囊封層52包括具有填充劑之環氧樹脂、封裝材料(例如，環氧樹脂封裝材料或其他封裝材料)、聚醯亞胺、酚系化合物或材料、其中分散有聚矽氧之材料，或其組合。
圖5B為根據本發明之另一實施例的基板結構6之截面圖。基板結構6包括若干單元(諸如基板結構5)，該若干單元可藉由切割道彼此分開。
圖6為根據本發明之另一實施例的基板結構6之截面圖。互連結構50包括CCL基板，該CCL基板包括可藉由切割道彼此分開的若干單元。
圖6A、圖6B、圖6C、圖6D、圖6E、圖6F、圖6G、圖6H、圖6I及圖6J為根據本發明之一些實施例的在各製造階段的佈線結構之截面圖。為了更好地理解本發明之態樣，此等圖中的至少一些已經簡化。
參考圖6A，提供互連結構10。互連結構10包括具有表面10d1及與表面10d1相對之表面10d2的載體10d。互連結構10包括表面10d1上的導電層10c1及表面10d2上的導電層10c2。載體10d可包括介電層，且可包括諸如玻璃纖維之填充劑。
在本發明實施例中，互連結構10包括CCL基板，該CCL基板包括可藉由切割道彼此分開的若干單元。因為單元中之每一者在製造方法中經受相似或相同的製程，所以為方便起見，下文描述中僅示出及描述了例示性單元。
參考圖6B，例如在微影製程中，隨後在蝕刻製程中對導電層10c1進行圖案化，從而產生圖案化導電層。亦參考圖1，圖案化導電層可包括導電襯墊或導電跡線10t或這兩者，以有助於電互連或信號傳輸。接下來，介電層11形成於載體10d之表面10d1上，覆蓋導電跡線10t。用於第一介電層11之合適材料可係選自具有所要黏著性以有助於例如半導體裝置或電子組件之附接的材料。在一些實施例中，介電層11包括樹脂。此外，介電層11可能不含諸如玻璃纖維之填充劑。
然後，參考圖6C，電子組件13及14附接至介電層11。電子組件13及14的朝向是「面朝上」，其導電襯墊13p及14p背對介電層11。電子組件13及14可各自包括主動裝置或被動裝置。
參考圖6D，介電層12形成於介電層11上，覆蓋電子組件13及14。用於介電層12之合適材料類似於或等同於用於介電層11之材料。詳言之，類似介電層11，介電層12可包括不含玻璃纖維之樹脂。
參考圖6E，例如在層壓製程中，導電層15形成於介電層12之表面上。用於導電層15之合適材料可包括Cu。
隨後，參考圖6F，導電層15經圖案化，從而產生圖案化導電層15。圖案化導電層15曝露介電層12之第一部分(無編號)，該等第一部分的位置對應於導孔(諸如圖1中所展示之導孔11v)。另外，圖案化導電層15曝露介電層12之第二部分(無編號)，該等第二部分的位置對應於導電襯墊13p及14p。
隨後，第一開口11h例如在可使用二氧化碳(CO2 )雷射之雷射鑽孔程序中形成為曝露的第一部分，從而曝露圖案化導電層10c1中之導電跡線10t。第一開口12h朝向導電跡線10t延伸穿過介電層12及介電層11。另外，第二開口12h藉由使用例如噴砂程序形成為曝露的第二部分，從而曝露導電襯墊13p及14p。
另外，導電層10c2經圖案化，從而產生圖案化導電層10c2，該圖案化導電層曝露載體10d之若干部分。隨後，開口10h藉由使用例如雷射鑽孔自其曝露部分形成為載體10d，從而曝露導電跡線10t之若干部分。
在一些實施例中，開口10h及開口11h藉由使用雷射鑽孔而形成。在形成延伸穿過不含玻璃纖維之介電層的開口11h的過程中，以第一脈衝能量來施加雷射。比較而言，在形成延伸穿過填充有玻璃纖維之介電層的開口10h的過程中，以第二脈衝能量來施加雷射。第二脈衝能量高於第一脈衝能量。
接下來，參考圖6G，例如在電鍍程序中，導電材料形成於圖案化導電層15上。導電材料填充開口11h及開口12h，從而產生導孔11v及導孔13v及14v。在本發明實施例中，導孔11v朝向導電層10c1逐漸變窄。第一導電層亦安置於經圖案化第一導電箔p23上。
類似地，例如在電鍍程序中，導電材料形成於圖案化導電層10c2上。導電材料填充開口10h，從而產生導孔10v。
導電層10c2、導孔10v、導孔10v及導電層15界定環繞電子組件13及電子組件14之屏蔽結構。
在一些實施例中，晶種層(圖中未示出)可保形地安置於開口10h、開口11h及開口12h之側壁上。在一些實施例中，晶種層可藉由濺鍍鈦及銅(Ti/Cu)或鈦鎢合金(TiW)而形成。在一些實施例中，晶種層可藉由無電極電鍍Ni或Cu而形成。
接下來，參考圖6H，圖案化導電層15經受圖案化程序以形成孔15h，該等孔與此等導孔11v、13v及14v中之一些電隔離且界定用於電互連之導電跡線。
接下來，參考圖6I，對圖案化導電層15施加諸如防焊劑之保護層16，從而曝露導孔13v及導孔14v。保護層16有助於控制在焊接期間將要形成於曝露的導孔13v及導孔14v上之焊料球的移動。
隨後，參考圖6J，電接點17提供於曝露的導孔13v及導孔14v上。
在一些實施例中，電子組件(諸如圖5A中之電子組件51)可提供於互連結構10上，且電連接至導電層10c2。在一些實施例中，
參考圖7O，囊封層(諸如圖5A中之囊封層52)可形成於互連結構10上，以覆蓋或囊封電子組件。在一些實施例中，囊封層可藉由諸如轉注模製或壓縮模製之模製技術形成。在一些實施例中，可執行單體化以分離出個別基板結構或半導體裝置封裝裝置。可例如藉由使用劃片機、雷射或其他適當切割技術來執行單體化。
為便於描述，本文中可使用諸如「下方」、「之下」、「下部」、「上方」、「上部」、「左」、「右」及其類似者之空間相對術語來描述一個元件或特徵與另一元件或特徵之關係，如圖中所示出。除圖中所描繪的定向之外，空間相對術語亦意欲涵蓋裝置在使用或操作中的不同定向。設備可以其他方式定向(旋轉90度或處於其他定向)且本文中所使用的空間相對描述詞可同樣相應地進行解譯。應理解，當將元件稱為「連接」或「耦接」至另一元件時，其可直接連接或耦接至另一元件，或可存在介入元件。
如本文中所使用，術語「大致」、「實質上」、「大體」及「約」係用以描述及考慮小的變化。當與事件或情形結合使用時，術語可指事件或情形明確發生之個例以及事件或情形極近似於發生之個例。如本文中所使用，針對既定值或範圍，術語「約」通常指在既定值或範圍的±10%、±5%、±1%或±0.5%內。範圍可在本文中表達為自一個端點至另一端點或在兩個端點之間。本文中所揭示之所有範圍包括端點，除非另外規定。術語「實質上共面」可以指沿著相同平面相差不超過若干微米(μm)的兩個表面，諸如沿著相同平面相差不超過10 μm、5 μm、1 μm或0.5 μm。在稱數值或特性「實質上」相同時，該術語可指該等值處於該等值之平均值的±10%、±5%、±1%或±0.5%內。
前述內容概述本發明之若干實施例及詳細態樣的特徵。本發明中描述之實施例可易於用作設計或修改用於進行本文中引入之實施例的相同或類似目的及/或達成相同或類似優勢的其他製程及結構的基礎。此等等效構造並不脫離本發明之精神及範疇，且可在不脫離本發明之精神及範疇的情況下進行各種改變、替代及更改。
1:基板結構 3:基板結構 4:基板結構 5:基板結構 6:基板結構 10:互連結構 10c1:導電層 10c2:導電層 10d:載體 10d1:表面 10d2:表面 10h:開口 10s:屏蔽部分 10t:導電跡線部分 10v:導孔 11:介電層 11h:第一開口 11v:導孔 11w:導電壁 12:介電層 12h:第一開口 13:電子組件 13p:導電襯墊 13v:導孔 14:電子組件 14p:導電襯墊 14v:導孔 15:導電層 15h:孔 16:保護層 17:電接點 18:電接點 30:互連結構 30c1:導電層 30c2:導電層 30s:屏蔽部分 30t:導電跡線部分 40:互連結構 40c1:導電層 40c2:導電層 50:互連結構 50c2:導電層 51:電子組件 51c:電接點 52:囊封層 131:表面 132:表面 133:側向表面 SD1:屏蔽結構 SD2:屏蔽結構 SD3:屏蔽結構 SD4:屏蔽結構 SD5:屏蔽結構
當結合附圖閱讀時，自以下詳細描述容易理解本發明之態樣。應注意，各種特徵可能未按比例繪製。為論述清楚起見，可任意增大或減小各種特徵的尺寸。
圖1為根據本發明之實施例的基板結構之截面圖。
圖2A為根據本發明之實施例的電磁干擾(EMI)屏蔽機構之示意性透視圖。
圖2B為根據本發明之另一實施例的EMI屏蔽機構之示意性透視圖。
圖3為根據本發明之另一實施例的基板結構之截面圖。
圖4為根據本發明之又一實施例的基板結構之截面圖。
圖5A為根據本發明之又一實施例的半導體裝置封裝之截面圖。
圖5B為根據本發明之再一實施例的半導體裝置封裝之截面圖。
圖6A示出了根據本發明之一些實施例的製造基板結構之方法的一或多個階段。
圖6B示出了根據本發明之一些實施例的製造基板結構之方法的一或多個階段。
圖6C示出了根據本發明之一些實施例的製造基板結構之方法的一或多個階段。
圖6D示出了根據本發明之一些實施例的製造基板結構之方法的一或多個階段。
圖6E示出了根據本發明之一些實施例的製造基板結構之方法的一或多個階段。
圖6F示出了根據本發明之一些實施例的製造基板結構之方法的一或多個階段。
圖6G示出了根據本發明之一些實施例的製造基板結構之方法的一或多個階段。
圖6H示出了根據本發明之一些實施例的製造基板結構之方法的一或多個階段。
圖6I示出了根據本發明之一些實施例的製造基板結構之方法的一或多個階段。
圖6J示出了根據本發明之一些實施例的製造基板結構之方法的一或多個階段。
貫穿該等圖式及實施方式使用共附圖標號以指示相同或類似元件。結合隨附圖式，自以下實施方式，本發明將更顯而易見。
1:基板結構
10:互連結構
10c1:導電層
10c2:導電層
10d:載體
10d1:表面
10d2:表面
10s:屏蔽部分
10t:導電跡線部分
10v:導孔
11:介電層
11v:導孔
12:介電層
13:電子組件
13p:導電襯墊
13v:導孔
14:電子組件
14p:導電襯墊
14v:導孔
15:導電層
16:保護層
17:電接點
18:電接點
131:表面
132:表面
133:側向表面
SD1:屏蔽結構

Claims (21)

  1. 一種基板結構，其包含：一互連結構，其中該互連結構包括具有一第一表面及與該第一表面相對之一第二表面的一載體、安置於該載體之該第一表面上的一第一導電層，及安置於該載體之該第二表面上的一第二導電層；一第一介電層，位於該互連結構上；一第二介電層，位於該第一介電層上；一電子組件，內埋於該第二介電層中；及一第一導孔，穿過該第一介電層及該第二介電層且鄰近於該電子組件而安置；其中該第一導電層及該第二導電層中的至少一者、及該第一導孔界定環繞該電子組件之一第一屏蔽結構。
  2. 如請求項1之基板結構，其中該電子組件具有背對該互連結構之一主動表面、與該主動表面相對之一背面表面，及在該主動表面與該背面表面之間延伸的一側向表面；其中該電子組件之該側向表面面朝該第一導孔。
  3. 如請求項1之基板結構，其中該第一導電層包括用於信號傳輸之一導電跡線。
  4. 如請求項1之基板結構，其中該第一導電層包括用於界定該第一屏蔽結構之一屏蔽部分及用於信號傳輸之一導電跡線部分。
  5. 如請求項1之基板結構，其中該第一導孔朝向該第一導電層逐漸變窄。
  6. 如請求項1之基板結構，其進一步包含：連接於該第一導電層與該第二導電層之間的一第二導孔，其中該第二導孔朝向該第一導電層逐漸變窄。
  7. 如請求項6之基板結構，其中該第一導孔及該第一導電層界定環繞該電子組件之該第一屏蔽結構，且該第二導電層及該第二導孔界定環繞該電子組件之一第二屏蔽結構。
  8. 如請求項1之基板結構，其中該第一導孔包括導電柱或導電壁中的至少一者。
  9. 如請求項1之基板結構，其進一步包含：安置於該第二介電層上且與該第一導孔電連接之一導電層。
  10. 一種半導體裝置封裝，其包含：一互連結構，其中該互連結構包括具有一第一表面及與該第一表面相對之一第二表面的一載體、安置於該載體之該第一表面上的一第一導電層，及安置於該載體之該第二表面上的一第二導電層；一介電層，位於該第一導電層上； 一第一電子組件，內埋於該介電層中；一囊封層，安置於該第二導電層上；一第二電子組件，內埋於該囊封層中且電連接至該第二導電層；及一第一導孔，穿過該介電層且鄰近於該第一電子組件而安置；其中該第一導電層及該第一導孔界定環繞該第一電子組件之一第一屏蔽結構；及其中該第一電子組件具有背對該互連結構之一主動表面及與該主動表面相對之一背面表面，且其中該第一導孔超出該背面表面。
  11. 如請求項10之半導體裝置封裝，其中該第一電子組件具有在該主動表面與該背面表面之間延伸的一側向表面；其中該第一電子組件之該側向表面面朝該第一導孔。
  12. 如請求項10之半導體裝置封裝，其中該第一導電層包括用於信號傳輸之一導電跡線。
  13. 如請求項10之半導體裝置封裝，其中該第一導電層包括用於界定該第一屏蔽結構之一屏蔽部分及用於信號傳輸之一導電跡線部分。
  14. 如請求項10之半導體裝置封裝，其中該第一導孔朝向該第一導電層逐漸變窄。
  15. 如請求項10之半導體裝置封裝，其進一步包含： 連接於該第一導電層與該第二導電層之間的一第二導孔，其中該第二導孔朝向該第一導電層逐漸變窄。
  16. 如請求項15之半導體裝置封裝，其中該第一導孔及該第一導電層界定環繞該第一電子組件之該第一屏蔽結構，且該第二導電層及該第二導孔界定環繞該第一電子組件之一第二屏蔽結構。
  17. 如請求項15之半導體裝置封裝，其中該第一導孔及該第二導孔接觸該第一導電層的相對側。
  18. 如請求項10之半導體裝置封裝，其中該第一導孔包括導電柱或導電壁中的至少一者。
  19. 一種製造一基板結構之方法，其包含：提供一互連結構，其中該互連結構包括具有一第一表面及與該第一表面相對之一第二表面的一載體、安置於該載體之該第一表面上的一第一導電層，及安置於該載體之該第二表面上的一第二導電層；將一電子組件附接至該互連結構；及在將該電子組件附接至該互連結構後，形成一第一導孔鄰近於該電子組件，其中該第一導孔電連接至該第一導電層及該第二導電層中的至少一者。
  20. 如請求項19之方法，其進一步包含： 在該互連結構上形成一介電層；及圖案化該介電層，從而產生一第一開口，該第一開口曝露該第一導電層的一部分。
  21. 如請求項20之方法，其進一步包含：用一導電材料來填充該第一開口，從而產生第一導孔。
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