TWI761756B - Electronic package and substrate structure thereof - Google Patents
Electronic package and substrate structure thereof Download PDFInfo
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- TWI761756B TWI761756B TW109103375A TW109103375A TWI761756B TW I761756 B TWI761756 B TW I761756B TW 109103375 A TW109103375 A TW 109103375A TW 109103375 A TW109103375 A TW 109103375A TW I761756 B TWI761756 B TW I761756B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13005—Structure
- H01L2224/13008—Bump connector integrally formed with a redistribution layer on the semiconductor or solid-state body
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
Description
本發明係有關一種封裝基板,尤指一種特殊佈線設計之電子封裝件及其基板結構。 The present invention relates to a package substrate, in particular to an electronic package with special wiring design and its substrate structure.
隨著電子產業的蓬勃發展,大部份的電子產品均朝向小型化及高速化的目標發展,尤其是通訊產業的發展已普遍整合運用於各類電子產品,例如行動電話(Cell phone)、膝上型電腦(laptop)等。 With the vigorous development of the electronic industry, most electronic products are developing towards the goal of miniaturization and high-speed development, especially the development of the communication industry has been generally integrated and applied to various electronic products, such as cell phones, laptops, etc. Laptop, etc.
目前行動通訊裝置中,其封裝基板上均配置有被動元件,如電容,供作為直流阻流器(DC block),以抵抗靜電放電(Electrostatic Discharge,簡稱ESD),避免瞬間的大電壓之靜電破壞電路。具體地,習知封裝基板上係配置有一接點組,其包含一電源墊及一接地墊,以電性連接被動元件之正、負電極。 At present, in mobile communication devices, passive components, such as capacitors, are arranged on the packaging substrate to act as a DC block to resist Electrostatic Discharge (ESD) and avoid electrostatic damage caused by instantaneous high voltage. circuit. Specifically, a contact group is disposed on the conventional package substrate, which includes a power pad and a ground pad to electrically connect the positive and negative electrodes of the passive element.
然而,同一類型之行動通訊裝置中,依不同功能需求配置不同之被動元件,此時,該封裝基板之接點組無法滿足各種被動元件所需之電壓需求,故對於同一類型之行動通訊裝置,需開發不同電壓規格之封裝基板,因而增加製作封裝基板的時間及成本。 However, in the same type of mobile communication device, different passive components are configured according to different functional requirements. At this time, the contact group of the package substrate cannot meet the voltage requirements required by various passive components. Therefore, for the same type of mobile communication device, Package substrates with different voltage specifications need to be developed, thus increasing the time and cost of manufacturing the package substrate.
再者,如第1圖所示,雖有業者於該封裝基板1上形成多組電壓不同之接點組10(其包含一電源墊10b及一接地墊10a),以依需求將被動元件電性連接至於符合電壓需求之接點組10上,但習知封裝基板1上需增設佈設空間以配置多組接點組10,導致該封裝基板1之版面面積大幅增加,因而難以符合微小化之需求。
Furthermore, as shown in FIG. 1, although some manufacturers have formed a plurality of
因此,如何克服上述習知技術之問題,實已成為目前業界亟待克服之難題。 Therefore, how to overcome the above-mentioned problems of the prior art has actually become an urgent problem to be overcome in the current industry.
鑑於上述習知技術之種種缺失,本發明提供一種基板結構,係包括:板體;至少一第一電性接觸墊,係設於該板體上;以及複數第二電性接觸墊,係設於該板體上且沿該第一電性接觸墊之輪廓排設,以由該至少一第一電性接觸墊之其中一者配合該複數第二電性接觸墊之其中一者形成為接點組。 In view of various deficiencies in the above-mentioned prior art, the present invention provides a substrate structure, comprising: a board body; at least one first electrical contact pad disposed on the board body; and a plurality of second electrical contact pads disposed on the board body Arranged on the board and along the contour of the first electrical contact pads, one of the at least one first electrical contact pad cooperates with one of the plurality of second electrical contact pads to form a contact point group.
前述之基板結構中,該板體係具有用以電性連接該至少一第一電性接觸墊及/或該複數第二電性接觸墊之線路層。 In the aforementioned substrate structure, the board system has a circuit layer for electrically connecting the at least one first electrical contact pad and/or the plurality of second electrical contact pads.
前述之基板結構中,該複數第二電性接觸墊係對稱位於該至少一第一電性接觸墊之相對兩側。 In the aforementioned substrate structure, the plurality of second electrical contact pads are symmetrically located on opposite sides of the at least one first electrical contact pad.
前述之基板結構中,該複數第二電性接觸墊係對稱位於該至少一第一電性接觸墊之任意四個方位上。 In the aforementioned substrate structure, the plurality of second electrical contact pads are symmetrically located on any four orientations of the at least one first electrical contact pad.
前述之基板結構中,該複數第二電性接觸墊係為電源接點。例如,該複數第二電性接觸墊之至少兩者之電壓值係不相同。 In the aforementioned substrate structure, the plurality of second electrical contact pads are power contacts. For example, the voltage values of at least two of the plurality of second electrical contact pads are different.
前述之基板結構中,該至少一第一電性接觸墊係為接地接點。 In the aforementioned substrate structure, the at least one first electrical contact pad is a ground contact.
本發明亦提供一種電子封裝件,係包括:如前述之基板結構;以及電子元件,係設於該板體上並電性連接該至少一第一電性接觸墊之其中一者及電性連接該複數第二電性接觸墊之其中一者。 The present invention also provides an electronic package, comprising: the aforementioned substrate structure; and an electronic component disposed on the board and electrically connected to one of the at least one first electrical contact pad and electrically connected one of the plurality of second electrical contact pads.
前述之電子封裝件中,復包括設於該基板結構上之半導體晶片。 The aforementioned electronic package further includes a semiconductor chip disposed on the substrate structure.
前述之電子封裝件中,該電子元件係為被動元件。 In the aforementioned electronic package, the electronic components are passive components.
由上可知,本發明之電子封裝件及其基板結構,主要藉由將複數第二電性接觸墊沿該至少一第一電性接觸墊之外圍(輪廓)排設,以由該至少一第一電性接觸墊之其中一者可配合該複數第二電性接觸墊形成為接點組,使該電子元件之其中一側(如電源端)可依需求電性連接適合電壓值之其中一個第二電性接觸墊,而另一側電性連接該至少一第一電性接觸墊,故相較於習知技術,採用本發明之基板結構製作該電子封裝件時,無需額外製作多種不同規格之封裝基板,因而可減少製作封裝基板的時間及成本。 As can be seen from the above, the electronic package and its substrate structure of the present invention are mainly arranged by arranging a plurality of second electrical contact pads along the periphery (outline) of the at least one first electrical contact pad, so that the at least one first electrical contact pad can be One of the electrical contact pads can cooperate with the plurality of second electrical contact pads to form a contact group, so that one side (such as the power terminal) of the electronic device can be electrically connected to one of the suitable voltage values according to the requirements The second electrical contact pad is electrically connected to the other side of the at least one first electrical contact pad. Therefore, compared with the prior art, when the electronic package is fabricated using the substrate structure of the present invention, there is no need to additionally fabricate a variety of different The package substrate of the specification can reduce the time and cost of making the package substrate.
此外,當該第一電性接觸墊係為複數時,則能與對應之第二電性接觸墊形成複數個接點組。 In addition, when the first electrical contact pads are plural, a plurality of contact groups can be formed with the corresponding second electrical contact pads.
再者,藉由複數第二電性接觸墊沿該第一電性接觸墊之輪廓排設之設計,因而對應不同之電子元件僅需於該板體上佈設至少一第一電性接觸墊,故相較於習知封裝基板之多個接點組,本發明之基板結構能有效縮減該板體之版面面積,以符合微小化之需求。 Furthermore, through the design that the plurality of second electrical contact pads are arranged along the outline of the first electrical contact pad, it is only necessary to arrange at least one first electrical contact pad on the board for different electronic components, Therefore, compared with the plurality of contact groups of the conventional package substrate, the substrate structure of the present invention can effectively reduce the layout area of the board to meet the requirement of miniaturization.
1:封裝基板 1: Package substrate
10:接點組 10: Contact group
10a:接地墊 10a: Ground Pad
10b:電源墊 10b: Power Pad
2:基板結構 2: Substrate structure
20:板體 20: Board body
200:線路層 200: circuit layer
21:第一電性接觸墊 21: The first electrical contact pad
22a,22b,22c,22d:第二電性接觸墊 22a, 22b, 22c, 22d: second electrical contact pads
3:電子封裝件 3: Electronic packages
30:電子元件 30: Electronic Components
301:接地電極 301: Ground electrode
302:電源電極 302: Power electrode
第1圖係為習知封裝基板之上視平面示意圖。 FIG. 1 is a schematic top plan view of a conventional package substrate.
第2圖係為本發明之基板結構之上視平面示意圖。 FIG. 2 is a schematic top plan view of the substrate structure of the present invention.
第3圖係為本發明之電子封裝件之剖面示意圖。 FIG. 3 is a schematic cross-sectional view of the electronic package of the present invention.
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The following specific embodiments are used to illustrate the implementation of the present invention, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如“第一”、“第二”、“上”、及“一”等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。 It should be noted that the structures, proportions, sizes, etc. shown in the drawings in this specification are only used to cooperate with the contents disclosed in the specification for the understanding and reading of those who are familiar with the art, and are not intended to limit the implementation of the present invention. Therefore, it has no technical significance. Any modification of the structure, change of the proportional relationship or adjustment of the size should still fall within the scope of the present invention without affecting the effect and the purpose that the present invention can achieve. The technical content disclosed by the invention can be covered within the scope. At the same time, terms such as "first", "second", "on", and "one" quoted in this specification are only for the convenience of description and are not used to limit the scope of the present invention. , the change or adjustment of the relative relationship shall be regarded as the scope of the present invention without substantial changes in the technical content.
第2圖係為本發明之基板結構2之上視平面示意圖。如第2圖所示,所述之基板結構2係包括:一板體20、一設於該板體20上之至少一第一電性接觸墊21以及複數設於該板體20上之第二電性接觸墊22a,22b,22c,22d。
FIG. 2 is a schematic top plan view of the
所述之板體20係具有用以電性連接該至少一第一電性接觸墊21及/或該複數第二電性接觸墊22a,22b,22c,22d之至少一線路層200(如第3圖所示)。
The
於本實施例中,該板體20係為具有核心層與線路結構之封裝基板(substrate)或無核心層(coreless)之封裝基板,其係於介電材上形成線路層200,如扇出(fan out)型重佈線路層(redistribution layer,簡稱RDL),且介電材係為如聚對二唑苯(Polybenzoxazole,簡稱PBO)、聚醯亞胺(Polyimide,簡稱PI)、預浸材(Prepreg,簡稱PP)等。
In this embodiment, the
所述之至少一第一電性接觸墊21係為接地接點,其呈矩形。應可理解地,有關該至少一第一電性接觸墊21之形狀可依需求設計,並無特別限制。
The at least one first
所述之複數第二電性接觸墊22a,22b,22c,22d係為電源接點,其沿該至少一第一電性接觸墊21之外圍設置,以由該至少一第一電性接觸墊21(接地接點)配合該複數第二電性接觸墊22a,22b,22c,22d(電源接點)之其中一者形成為接點組。
The plurality of second
於本實施例中,該複數第二電性接觸墊22a,22b,22c,22d係對稱位於該至少一第一電性接觸墊21之相對兩側。例如,該複數第二電性接觸墊22a,22b,22c,22d係對稱位於該至少一第一電性接觸墊21之上下左右四個方位上。具體地,該複數第二電性接觸墊22a,22b,22c,22d之數量為四個,其以該至少一第一電性接觸墊21為中心對稱圍繞該至少一第一電性接觸墊21,使該複數第二電性接觸墊22a,22b,22c,22d與該至少一第一電性接觸墊21排設呈十字形。
In this embodiment, the plurality of second
再者,該複數第二電性接觸墊22a,22b,22c,22d之至少兩者之電壓值係不相同。例如,四個第二電性接觸墊22a,22b,22c,22d之每一者之電壓值均不相同。
Furthermore, the voltage values of at least two of the plurality of second
第3圖係為本發明之電子封裝件3之剖面示意圖。如第3圖所示,所述之電子封裝件3係包括:一基板結構2以及一設於該板體20上之電子元件30。
FIG. 3 is a schematic cross-sectional view of the
所述之電子元件30係為被動元件,如電容、電阻、電感或其它種類,其電性連接該複數第二電性接觸墊22a,22b,22c,22d之其中一者與該至少一第一電性接觸墊21。
The
另外,該電子封裝件3中亦可於該基板結構2上配置如控制晶片、邏輯晶片、功能晶片或其它晶片之半導體晶片(圖略),且可於該基板結構2上形成封裝層(圖略),以包覆該電子元件30及半導體晶片。
In addition, in the
綜上所述,本發明之電子封裝件3藉由該基板結構2之設計,使複數第二電性接觸墊22a,22b,22c,22d沿該至少一第一電性接觸墊21之外圍(輪廓)排設,以由至少一接地墊可配合複數個電源墊形成為接點組,故該電子元件30之其中一側(如電源電極302)可依需求電性連接適合電壓值之複數第二電性接觸墊22a,22b,22c,22d之其中一者,而該電子元件30之另一側(如接地電極301)則電性連接該至少一第一電性接觸墊21。因此,採用本發明之基板結構2製作該電子封裝件3時,無需額外開發多種不同規格之封裝基板,即可滿足各種電壓需求之電子元件30,故相較於習知技術,本發明能有效減少製作基板結構2的時間及成本。
To sum up, the
再者,本發明藉由複數第二電性接觸墊22a,22b,22c,22d沿該至少一第一電性接觸墊21之外圍(輪廓)排設之設計,因而對應不同之電子元件30僅需於該板體20上佈設至少一第一電性接觸墊21,故相較於習知封裝基板之多個接點組,本發明之基板結構2能有效縮減該板體20之版面面積,以符合微小化之需求。
Furthermore, the present invention uses the design that the plurality of second
此外,當該第一電性接觸墊21係為複數時,則能與對應之第二電性接觸墊22a,22b,22c,22d形成複數個接點組。
In addition, when the first
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。 The above embodiments are used to illustrate the principles and effects of the present invention, but not to limit the present invention. Any person skilled in the art can make modifications to the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the right of the present invention should be listed in the scope of the patent application described later.
2:基板結構 2: Substrate structure
20:板體 20: Board body
21:第一電性接觸墊 21: The first electrical contact pad
22a,22b,22c,22d:第二電性接觸墊 22a, 22b, 22c, 22d: second electrical contact pads
Claims (9)
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TW201724390A (en) * | 2015-08-17 | 2017-07-01 | 聯發科技股份有限公司 | Ball grid array and semiconductor package |
TW201818529A (en) * | 2016-11-14 | 2018-05-16 | 矽品精密工業股份有限公司 | Electronic package and method for fabricating the same |
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TW202131459A (en) | 2021-08-16 |
CN113224020A (en) | 2021-08-06 |
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