CN117116905A

CN117116905A - Semiconductor device and method for manufacturing the same

Info

Publication number: CN117116905A
Application number: CN202310573042.3A
Authority: CN
Inventors: 彭泰豪; 黄耀聪
Original assignee: MediaTek Inc
Current assignee: MediaTek Inc
Priority date: 2022-05-24
Filing date: 2023-05-19
Publication date: 2023-11-24

Abstract

The invention discloses a semiconductor device, comprising: a first layer structure; a second layer structure; the bridging crystal grain is arranged between the first layer structure and the second layer structure; the first system single chip is arranged on the second layer structure; the second system single chip is arranged on the second layer structure; the first system single chip and the second system single chip are electrically connected through the bridging crystal grain. According to the invention, the first system single chip and the second system single chip can be electrically connected through the bridging crystal grain, so that the electrical connection path of the first system single chip and the second system single chip is shorter, data can be transmitted at high speed, and higher communication efficiency is achieved.

Description

Semiconductor device and method for manufacturing the same

Technical Field

The present invention relates to the field of semiconductor technology, and more particularly, to a semiconductor device and a method for manufacturing the same.

Background

The semiconductor device may include a plurality of substrates and a plurality of chips, wherein the chips are disposed on different substrates, respectively. Therefore, how to communicate with each other between chips is a prominent issue in the industry.

Disclosure of Invention

In view of the above, the present invention provides a semiconductor device and a method for manufacturing the same, which solves the above-mentioned problems.

According to a first aspect of the present invention, there is disclosed a semiconductor device comprising:

a first layer structure;

a second layer structure;

the bridging crystal grain is arranged between the first layer structure and the second layer structure;

the first system single chip is arranged on the second layer structure; and

the second system single chip is arranged on the second layer structure;

the first system single chip and the second system single chip are electrically connected through the bridging crystal grain.

According to a second aspect of the present invention, there is disclosed a method of manufacturing a semiconductor device, comprising:

forming a first one of a first layer structure and a second layer structure on a first carrier;

disposing a bridging die on the first one;

forming a second of the first layer structure and the second layer structure on the bridging die, wherein the bridging die is disposed between the first layer structure and the second layer structure; and

and arranging a first system single chip and a second system single chip on the second layer structure, wherein the first system single chip and the second system single chip are electrically connected through the bridging crystal grain.

The semiconductor device of the present invention includes: a first layer structure; a second layer structure; the bridging crystal grain is arranged between the first layer structure and the second layer structure; the first system single chip is arranged on the second layer structure; the second system single chip is arranged on the second layer structure; the first system single chip and the second system single chip are electrically connected through the bridging crystal grain. According to the invention, the first system single chip and the second system single chip can be electrically connected through the bridging crystal grain, so that the electrical connection path of the first system single chip and the second system single chip is shorter, data can be transmitted at high speed, and higher communication efficiency is achieved.

Drawings

FIG. 1A is a top view of a semiconductor device according to one embodiment of the present invention;

FIG. 1B is a schematic cross-sectional view of the semiconductor device of FIG. 1A in the direction 1B-1B';

fig. 2 is a schematic cross-sectional view of a semiconductor device 200 according to another embodiment of the invention;

FIG. 3 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention;

fig. 4 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention;

fig. 5 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention;

fig. 6 is a schematic view showing a cross-sectional view of a semiconductor device according to another embodiment of the present invention;

fig. 7A is a top view of a semiconductor device according to another embodiment of the present invention;

FIG. 7B is a schematic cross-sectional view of the semiconductor device of FIG. 7A in the direction 7B-7B';

FIGS. 8A-8I are schematic diagrams illustrating a method of fabricating the semiconductor device of FIG. 1B;

fig. 9A to 9I are schematic views illustrating a method of manufacturing the semiconductor device of fig. 3; and

fig. 10A to 10H are schematic views showing a manufacturing method of the semiconductor device of fig. 5.

Detailed Description

In the following detailed description of the embodiments of the present invention, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice them, and it is to be understood that other embodiments may be utilized and that mechanical, structural and procedural changes may be made without departing from the spirit and scope of the present invention. The invention relates to a method for manufacturing a semiconductor device. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of embodiments of the present invention is defined only by the appended claims.

It will be understood that, although the terms "first," "second," "third," "primary," "secondary," etc. may be used herein to describe various components, elements, regions, layers and/or sections, these components, elements, regions, these layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first or primary component, region, layer or section discussed below could be termed a second or secondary component, region, layer or section without departing from the teachings of the present inventive concept.

Further, spatially relative terms such as "below," "under," "above," "over," and the like may be used herein for ease of description to describe one component or feature's relationship thereto. Another component or feature as shown. In addition to the orientations depicted in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, it will also be understood that when a "layer" is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

The terms "about", "approximately" and "approximately" generally mean within a range of ±20% of a specified value, or ±10% of the specified value, or ±5% of the specified value, or ±3% of the specified value, or ±2% of the specified value, or ±1% of the specified value, or ±0.5% of the specified value. The prescribed value of the present invention is an approximation. When not specifically described, the stated values include the meaning of "about," approximately, "and" about. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular terms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concepts. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It will be understood that when an "element" or "layer" is referred to as being "on," "connected to," "coupled to" or "adjacent to" another element or layer, it can be directly on, connected to, coupled to or adjacent to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to," or "directly adjacent to" another element or layer, there are no intervening elements or layers present.

Note that: (i) The same features will be denoted by the same reference numerals throughout the figures and not necessarily described in detail in each of the figures in which they appear, and (ii) a series of figures may show different aspects of a single item, each of which is associated with various reference labels that may appear in the entire sequence or may appear only in selected figures of the sequence.

Referring to fig. 1A and 1B, fig. 1A is a top view of a semiconductor device 100 according to an embodiment of the invention, and fig. 1B is a schematic cross-sectional view of the semiconductor device 100 in the direction 1B-1B' of fig. 1A. The semiconductor device 100 may be applied to a high bandwidth stack package (high bandwidth package on package, HBPoP), a Fan-out stack package (Fan-out package on package, fan-out PoP), or the like. In one embodiment, the semiconductor device 100 may be applied to a high bandwidth package, a fan-out package, or the like. The method and the device can provide high-bandwidth communication between the semiconductor components in the package, and are particularly suitable for high-bandwidth packaging.

As shown in fig. 1B, the semiconductor device 100 includes a first layer structure 110, a second layer structure 120, at least one bridge die 130, at least one first System on a Chip (SoC) 140, at least one first SoC 150, at least one underfill 155, at least one conductive post 160, at least one passive component 170, a first package (encapsulation body) 180, and at least one conductive contact 190. The bridging die 130 is disposed between the first layer structure 110 and the second layer structure 120. The first SoC 140 and the second SoC 150 are disposed on the second layer structure 120. In the present embodiment, the first SoC 140 and the second SoC 150 are electrically connected through the bridging die 130, so that the electrical connection paths of the first SoC 140 and the second SoC 150 are shorter, and data can be transmitted at high speed, with higher communication efficiency. As shown in fig. 1A, in a top view, the bridging die 130 may partially overlap the first SoC 140, and the bridging die 130 may partially overlap the second SoC 150, such that the bridging die 130 may be electrically connected to both the first SoC 140 and the second SoC 150 at a shorter distance.

As shown in fig. 1B, the first layer structure 110 is, for example, a redistribution layer (re-distributed layer, RDL) structure including a fan-out structure. For example, the first layer structure 110 includes at least one first conductive trace layer 111, at least one first conductive via layer 112, at least one first dielectric layer 113, and at least one first conductive contact 114, wherein adjacent two conductive trace layers 111 are spaced apart from one of the first dielectric layers 113, and adjacent two first conductive trace layers 111 are electrically connected through one of the first conductive via layers 112. The first conductive contact 114 is electrically connected to the first wire layer 111 or the first wire layer 111. The first conductive via layer 112 of the first layer structure 110 protrudes from the surface 113s of the outermost first dielectric layer 113. In addition, the first conductive contact 114 is, for example, a conductive bump, a conductive pad, or the like.

The first conductive line layer 111, the first conductive via layer 112, and the first conductive contact 114 may be formed of a material including, for example, copper, and the first dielectric layer 113 may be formed of a material such as Polyimide (PI). In one embodiment, the thickness of the wire layer 111 ranges from 4 micrometers (μm) to 8 μm, such as 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, etc., even more or less.

As shown in fig. 1B, the second layer structure 120 is, for example, an RDL structure including a fan-out structure. For example, the second layer structure 120 includes at least one second wire layer (conductive line layer) 121, at least one second conductive via layer 122, at least one second dielectric layer 123, and at least one second conductive contact 124, wherein two adjacent second wire layers 121 are separated from one of the second dielectric layers 123, and two adjacent second conductive line layers 121 are electrically connected through one of the second conductive via layers 122. The second conductive contact 124 has a surface 124s and the outermost second dielectric (dielectric) layer 123 has a surface 123s, wherein the surface 124s is flush with the surface 123 s. In the embodiment of the present invention, the first layer structure 110 and the second layer structure 120 are obviously different from the substrate structure and the printed circuit board structure, the second layer structure 120 may be used for fanning out pads of the SoC, and the first layer structure 110 may be used for fanning out the conductive vias 132 and the conductive pillars 160, so that the first layer structure 110 and the second layer structure 120 are fanning out structures and wiring structures.

In addition, the second wire layer 121, the second conductive via layer 122, and the second conductive contact 124 may be formed of a material such as copper, and the second dielectric layer 123 may be formed of a material such as Polyimide (PI). In one embodiment, the thickness of the second wire layer 121 ranges from 4 μm to 8 μm, e.g., 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, etc., even more or less, to improve design flexibility.

As shown in fig. 1B, the bridging die 130 electrically connects the first SoC 140 with the first SoC 150 through the first layer structure 110. For example, bridging die 130 includes a silicon-based (silicon-based) substrate 131, a plurality of conductive vias (or vias) 132, and a plurality of conductive contacts 133. The silicon substrate 131 has a first surface 131s1 and a second surface 131s2 opposite to the first surface 131s 1. The conductive via (or via) 132 is, for example, a through-silicon via (TSV). The conductive via 132 has a first surface 132s1 and a second surface 132s2 opposite to the first surface 132s1, wherein the first surface 132s1 and the second surface 132s2 are exposed to the first surface 131s1 and the second surface 131s2, respectively. The first surface 131s1 of the silicon-based substrate 131 is flush with the first surface 132s1 of the conductive via 132.

As shown in fig. 1B, the conductive via 132 electrically connects the first SoC 140 with the first SoC 150 through the second layer structure 120. For example, each conductive contact 133 is electrically connected to a corresponding conductive via 132, and the conductive via 132 is electrically connected to the second layer structure 120 through the corresponding conductive contact 133. In addition, the conductive via 132 is electrically connected to the first layer structure 110. Further, the conductive contacts 133 are formed on the same side adjacent to the second surface 131s2. The conductive contacts 133 are, for example, solder balls, conductive bumps, conductive pads, and the like.

Since the bridging die 130 is a silicon-based die, the bridging die 130 may provide a high density of I/O (input/output) contacts (e.g., a number of conductive vias 132 and/or a number of conductive contacts 133) to support the sum of the number of I/O contacts of the first SoC 140 and the number of I/O contacts of the second SoC 150. In one embodiment, the conductive via 132 may be used for signal connection and transmission, and the conductive via 132 may also be used for power/ground connection of the SoC, so that the bridging die 130 in this embodiment may be used not only for electrical connection (e.g. signal transmission) between the first SoC 140 and the first SoC150, but also for power/ground connection between the first SoC 140 and the first SoC150, so that not only the electrical connection path between the first SoC 140 and the first SoC150 is shorter, but also the power/ground connection path between the first SoC 140 and the first SoC150 is shorter, thereby comprehensively improving the performance of the semiconductor device. In one embodiment, the bridging die 130 may provide more connection channels and transmit a larger number of signals, thereby providing high-bandwidth electrical connection between the first SoC 140 and the first SoC150, so that the method of the embodiment of the present invention is suitable for high-bandwidth packaging or high-bandwidth semiconductor devices.

An SoC is an integrated circuit that integrates most or all of the components (or parts) of a computer or other electronic system. These components may include a central processing unit (central processing unit, CPU), memory interfaces, on-chip input/output devices, input/output interfaces, and auxiliary memory interfaces, typically all on a single substrate or microchip (microchip) along with other components such as a radio modem and a graphics processing unit (graphics processing unit, GPU). The SoC may contain digital, analog, mixed signals, and typically also radio frequency signal processing functions (otherwise it is considered only an application processor).

An underfill 155 is formed between the first SoC 140 and the second layer structure 120 to encapsulate the contact between the first SoC 140 and the second layer structure 120, and another underfill 155 is formed between the second SoC 150 and the second layer structure 120 to encapsulate the contact between the second SoC 150 and the second layer structure 120.

As shown in fig. 1B, in one embodiment, the first SoC 140 and the second SoC are not directly connected to each other, but are indirectly connected to each other through the bridging die 130 and the second layer structure 120.

As shown in fig. 1B, the conductive pillars 160 connect the first layer structure 110 and the second layer structure 120. For example, the conductive post 160 has a first surface 160s1 and a second surface 160s2 opposite the first surface 160s 1. The first surface 160s1 is electrically connected to the first conductive line layer 111 or the first conductive via layer 112 of the first layer structure 110. The second surface 160s2 is electrically connected to the second conductive line layer 121 or the second conductive via layer 122 of the second layer structure 120. The first surface 160s1 of the silicon-based substrate 131 is flush with the first surface 131s 1. The conductive pillars 160 may be used, for example, to transmit power, ground, or other signals, etc., that are connected to the first SoC 140 and the second SoC.

As shown in fig. 1B, the conductive pillar 160 further has a side 160w, the side 160w is covered by the first package 180, and the first surface 160s1 and the second surface 160s2 are not covered by the first package 180, so that the conductive pillar 160 can be directly connected (e.g., physically and electrically connected) with the conductive structure (e.g., wiring, via, etc.) in the first layer structure 110, and can be directly connected (e.g., physically and electrically connected) with the conductive structure (e.g., wiring, via, etc.) in the second layer structure 120. In one embodiment, the diameter or size of the conductive vias 132 may be smaller than the diameter or size of the conductive pillars 160 to accommodate different manufacturing and application requirements.

As shown in fig. 1B, the passive device 170 is, for example, an integrated passive device (Integrated Passive Device, IPD) disposed between the first layer structure 110 and the second layer structure 120. The passive device 170 is disposed side by side with the bridging die 130. The passive device 170 is, for example, a resistive, capacitive or inductive or a combination thereof lamp. The passive device 170 includes a substrate 171 and a plurality of conductive contacts 172. The substrate 171 is, for example, a silicon-based substrate. The substrate 171 has a first surface 171s1 and a second surface 171s2 opposite to the first surface 171s 1. A conductive contact 172 is formed on a side adjacent to the second surface 171s2 of the substrate 171. The conductive contact 172 may be electrically connected to the second layer structure 120. For example, the conductive contact 172 may be electrically connected to the second wire layer 121 or the second conductive via layer 122 of the second layer structure 120. The conductive contacts 172 are, for example, solder balls, conductive bumps, conductive pads, and the like. In one embodiment, the bridging die 130 is formed using a wafer (wafer) process, whereby the wires, vias, etc. in the bridging die 130 have fine line widths and fine pitches. In one embodiment, the passive devices 170 may also be formed during the wafer process, and thus may be formed during the same or similar process as the bridging die 130, thereby simplifying the manufacturing process. Of course, the passive device 170 may be formed in other processes or formed (e.g., purchased) for installation according to different design requirements.

As shown in fig. 1B, compared to the passive device 170 disposed under the first layer 110, the passive device 170 of the present embodiment is separated from the SoC by only one layer (e.g., the second layer 120), so that the voltage stabilizing effect can be improved (voltage drop can be reduced) by a shorter distance. In addition, since the passive component 170 is integrated in (disposed in) the first package 180, the SoC may have a greater thickness (e.g., about 700 microns), and accordingly, heat dissipation of the component (e.g., the SoC and/or memory die disposed on the second layer structure 120) may be increased. In one embodiment, for example, the height of the conventional stacked package structure may be higher, and in an embodiment, the first SoC 140 and the second SoC 150 are disposed side by side (instead of being disposed in a stacked manner), so that the upper limit of the height (thickness) of the first SoC 140 and/or the second SoC 150 may be higher, that is, the height (thickness) of the die of the first SoC 140 and/or the second SoC 150 may be set higher (or thicker), so as to improve the thermal capability (for example, the capability of accommodating heat), so that heat is easier to be dissipated, so as to improve the heat dissipation of the package, and ensure stable operation of the SoC, the die, and so on. In one embodiment, passive component 170 may cover the complete SoC in a top view; for example, passive components under the first SoC 140 are completely covered by the first SoC 140, and passive components under the second SoC 150 are completely covered by the second SoC 150. Therefore, the electric connection distance between the passive component below the corresponding SoC and the SoC is as short as possible, and the electric performance is improved. In the embodiment of the invention, the bridging die 130 and the passive component 170 are skillfully integrated in the first package 180, so that the integration degree of the components is improved, the whole semiconductor device structure is more stable, and the corresponding designs of the bridging die 130, the passive component 170 and the SoC in the embodiment of the invention can remarkably improve the performance of the semiconductor device and the signal transmission efficiency. Therefore, the design layout of the embodiment of the invention is more scientific and reasonable, and the applicability is wider.

As shown in fig. 1B, the first package 180 encapsulates the at least one bridging die 130, the at least one conductor pillar 160, and the at least one passive device 170. The first package 180 is, for example, a molding compound. The molding compound may be formed from a molding compound that includes, for example, a novolac-based resin, an epoxy-based resin, a silicone-based resin, or other suitable sealant. The molding compounds may also include suitable fillers, such as powdered SiO2. The molding compound may be applied using any of a variety of molding techniques, such as compression molding, injection molding, or transfer molding.

As shown in fig. 1B, the first package 180 has a first surface 180s1, wherein the first surface 180s1, the first surface 171s1, the first surface 160s1, the first surface 131s1 and the first surface 132s1 are flush with each other.

As described above, the semiconductor device 100 has a coplanar surface (coplaner surface) including at least two of a portion of the first package 180, a portion of the passive component 170, a portion of the conductive post 160, and a portion of the bridging die 130. In one embodiment, for example, at least two of the lower surface of the first package 180, the lower surface of the passive component 170, the lower surface of the conductive post 160, and the lower surface of the bridging die 130 are flush, forming a coplanar surface. The above structure of the present embodiment can ensure the stability and reliability of the contact and electrical connection between the conductive pillars 160, the conductive vias 132 bridging the die 130, and the like and the first layer structure 110, and the structural stability of the semiconductor device. In one embodiment, the lower surface (first surface 131s 1) of the bridging die 130 and the lower surface (first surface 171s 1) of the passive component 170 are flush with the lower surface (first surface 180s 1) of the first package 180, i.e., the first package 180 does not cover the lower surface (first surface 131s 1) of the bridging die 130 and the lower surface (first surface 171s 1) of the passive component 170. In one embodiment, the upper surface (second surface 131s 2) of the bridging die 130 and the upper surface of the passive component 170 are covered by the first encapsulant 180, so that the upper surface of the first encapsulant 180 is higher than the upper surface (second surface 131s 2) of the bridging die 130 and the upper surface of the passive component 170. In this way, the lower surfaces of the bridging die 130 and the passive component 170 are flush with the lower surface of the first package 180, and the upper surfaces of the bridging die 130 and the passive component 170 are covered by the first package 180, so that the structure of the semiconductor device is more stable by implementing the above structural manner through the process, and the first package 180 can protect and integrate the bridging die 130 and the passive component 170, thereby being more suitable for the structural manner that the first SoC 140 and the second SoC 150 are arranged side by side, and shortening the communication distance (or electrical path) between the socs and between the SoC and the passive component.

As shown in fig. 1B, a conductive contact 190 is formed on the first layer structure 110 and electrically connected to the first layer structure 110. For example, the conductive contact 190 is formed on the first conductive contact 114 of the first layer structure and is electrically connected to the first conductive contact 114 of the first layer structure 110. Further, the conductive contacts 190 may be solder balls, pre-solder, metal bumps, metal posts, and the like. In one embodiment, the bridging die 130, the passive component 170, the first package 180, the conductive pillars 160, and the like are formed between the first layer structure 110 and the second layer structure 120, and these components (the bridging die 130, the passive component 170, the first package 180, the conductive pillars 160, and the like) form a stable structure, which can make the mechanical structure of the entire semiconductor device stable, and as described above, the stable structure having the bridging die 130 and the passive component 170 therein can significantly improve the performance of the SoC, so that the semiconductor device of the embodiment of the present invention has high bandwidth, high performance, high heat dissipation efficiency, and high mechanical stability. In one embodiment, the bridging die 130 is not provided with active devices or devices (e.g., circuits, integrated circuits, transistors, etc.), but is provided with only electrical connection components such as conductive vias, etc., so that more electrical connection channels are possible. In one embodiment, the bridging die 130 is not disposed in either of the first layer structure 110 and the second layer structure 120, thereby reducing manufacturing complexity during manufacturing. In one embodiment, the passive components may be disposed on both sides of the bridging die 130, i.e., with passive components on both sides of the bridging die 130, respectively, to maintain structural balance as well as electrical performance integrity and balance. In one embodiment, one of the first SoC 140 and the second SoC 150 may be replaced with a memory package. In one embodiment, at least one of the first SoC 140 and the second SoC 150 may be replaced with a semiconductor die. In one embodiment, one of the first SoC 140 and the second SoC 150 may be replaced with a memory package and the other may be replaced with a semiconductor die (e.g., soC die). Of course, other modification designs can be made in the embodiment of the present invention, so as to improve the flexibility and design elasticity of the embodiment of the present invention.

Referring to fig. 2, fig. 2 is a schematic cross-sectional view of a semiconductor device 200 according to another embodiment of the invention. The semiconductor device 200 can be applied to HBPoP, inFO PoP, and the like.

As shown in fig. 2, the semiconductor device 200 includes a first layer structure 110, a second layer structure 120, at least one bridging die 130, at least one first SoC (System on Chip) 140, at least one first SoC 150, at least one underfill 155, at least one conductive pillar 160, at least one passive component 270, a first package 180, and at least one conductive contact 190. The bridging die 130 is disposed between the first layer structure 110 and the second layer structure 120. The first SoC 140 and the second SoC 150 are disposed on the second layer structure 120, and the first SoC 140 and the second SoC 150 are electrically connected through the bridging die 130.

Semiconductor device 200 includes the same or similar features as semiconductor device 100, except, for example, that passive component 270 is different from passive component 170.

In the present embodiment, the passive device 270 is a ceramic passive device such as a multilayer ceramic capacitor (Multi-layer Ceramic Capacitor, MLCC). The passive component 270 includes a first electrode 271 and a second electrode 272, wherein the first electrode 271 and the second electrode 272 are located on opposite sides of the passive component 270. The first electrode 271 and the second electrode 272 have two opposite end surfaces, and are electrically connected to the first layer structure 110 and the second layer structure 120, respectively. In one embodiment, for example, at least two of the lower surface of the first package 180, the lower surfaces of the first and second electrodes 271 and 272, the lower surface of the conductive pillars 160, and the lower surface of the bridging die 130 are flush, thereby forming a coplanar surface. The above structure of the present embodiment can ensure the stability and reliability of the contact and electrical connection between the conductive pillars 160, the conductive vias 132 bridging the die 130, and the like and the first layer structure 110, and the structural stability of the semiconductor device. In one embodiment, the lower surface of the bridging die 130 and the lower surfaces of the first electrode 271 and the second electrode 272 of the passive component 270 are flush with the lower surface of the first package 180, i.e., the lower surface of the bridging die 130 and the lower surfaces of the first electrode 271 and the second electrode 272 of the passive component 270 are not covered by the first package 180. In one embodiment, the upper surface of the bridging die 130 and the upper and lower surfaces of the passive component 270 are covered by the first package 180, so that the upper surface of the first package 180 is higher than the upper surface of the bridging die 130 and the upper surface of the passive component 270. In this way, the lower surfaces of the bridging die 130 and the first electrode 271 and the second electrode 272 of the passive component 270 are flush with the lower surface of the first package 180, and the upper surfaces and the lower surfaces of the bridging die 130 and the passive component 270 are covered by the first package 180, so that the structure of the semiconductor device is more stable by the process, and the first package 180 can protect and integrate the bridging die 130 and the passive component 270, thereby being more suitable for the structure that the first SoC 140 and the second SoC 150 are arranged side by side, and shortening the communication distance (or electrical path) between the socs and between the SoC and the passive component. In one embodiment, the bridging die 130, the passive component 270, the first package 180, the conductive pillars 160, and the like are formed between the first layer structure 110 and the second layer structure 120, and these components (the bridging die 130, the passive component 270, the first package 180, the conductive pillars 160, and the like) form a stable structure, which can make the mechanical structure of the entire semiconductor device stable, and as described above, the stable structure having the bridging die 130 and the passive component 270 therein can significantly improve the performance of the SoC, so that the semiconductor device of the embodiment of the present invention has high bandwidth, high performance, high heat dissipation efficiency, and high mechanical stability. In one embodiment, the bridging die 230 is not provided with active devices or devices (e.g., circuits, integrated circuits, transistors, etc.), but is provided with only electrical connection components such as conductive vias, etc., so that more electrical connection channels are possible. In one embodiment, the bridging die 130 is not disposed in either of the first layer structure 110 and the second layer structure 120, thereby reducing manufacturing complexity during manufacturing. In one embodiment, the passive components may be disposed on both sides of the bridging die 130, i.e., with passive components on both sides of the bridging die 130, respectively, to maintain structural balance as well as electrical performance integrity and balance. In one embodiment, one of the first SoC 140 and the second SoC 150 may be replaced with a memory package. In one embodiment, at least one of the first SoC 140 and the second SoC 150 may be replaced with a semiconductor die. In one embodiment, one of the first SoC 140 and the second SoC 150 may be replaced with a memory package and the other may be replaced with a semiconductor die (e.g., soC die). Of course, other modification designs can be made in the embodiment of the present invention, so as to improve the flexibility and design elasticity of the embodiment of the present invention.

Referring to fig. 3, fig. 3 is a schematic cross-sectional view of a semiconductor device 300 according to another embodiment of the invention. The semiconductor device 300 can be applied to HBPoP, inFO PoP, and the like.

As shown in fig. 3, the semiconductor device 300 includes a first layer structure 310, a second layer structure 120, at least one bridging die 330, at least one first SoC 140, at least one first SoC 150, at least one underfill 155, at least one conductive pillar 160, at least one passive component 370, a first package 180, and at least one conductive contact 190. The bridging die 330 is disposed between the first layer structure 310 and the second layer structure 120. The first SoC 140 and the second SoC 150 are disposed on the second layer structure 120, and the first SoC 140 and the second SoC 150 are electrically connected through the bridging die 330.

As shown in fig. 3, semiconductor device 300 includes the same or similar features as semiconductor device 100 except, for example, bridging die 330 of semiconductor device 300 is different from bridging die 130 of semiconductor device 100. The bridging die 330 may omit the conductive vias 132 as compared to the bridging die 130. The bridging die 330 may be electrically connected to the first layer structure 310 through the second layer structure 120 and the conductive pillars 160.

In addition, the passive device 370 includes a substrate 171, at least one conductive contact 172, and at least one conductive contact 373, wherein the conductive contact 373 is electrically connected to the conductive contact 172 and protrudes with respect to the conductive contact 172. The conductive contact 373 has a surface 373s. The bridging die 330 further includes at least one conductive contact 334, wherein the conductive contact 334 is formed on the conductive contact 133 and is electrically connected to the conductive contact 133, the conductive contact 334 protruding relative to the conductive contact 133. The conductive contact 334 has a surface 334s. The first package 180 also has a second surface 180s2 opposite the first surface 180s 1. The surface 373s of the passive device 370, the surface 334s of the bridging die 330, the second surface 160s2 of the conductive post 160, and the second surface 180s2 of the first package 180 are flush with each other.

As described above, the semiconductor device 300 has a coplanar surface including at least two of a portion of the first package 180, a portion of the passive component 370, a portion of the conductive post 160, and a portion of the bridging die 330. In one embodiment, for example, at least two of the lower surface of the first package 180, the lower surface of the passive component 370, the lower surface of the conductive post 160, and the lower surface of the bridging die 330 are flush, thereby forming a coplanar surface. The above structure of the present embodiment can ensure the stability and reliability of the contact and electrical connection with the first layer structure 110, such as the conductive pillars 160, and the contact and mounting of the bridging die 330 and the passive component 370, and the structural stability of the semiconductor device. In one embodiment, the lower surface of the bridging die 330 and the lower surface of the passive component 370 are flush with the lower surface of the first package 180, i.e., the first package 180 does not cover the lower surface of the bridging die 330 and the lower surface of the passive component 370. In one embodiment, the upper surface of the bridging die 330 and the upper surface of the passive component 370 are covered by the first package 180, and thus the upper surface of the first package 180 is higher than the upper surface of the bridging die 330 and the upper surface of the passive component 370. In this way, the lower surfaces of the bridging die 330 and the passive component 370 are flush with the lower surface of the first package 180, and the upper surfaces of the bridging die 330 and the passive component 370 are covered by the first package 180, so that the structure of the semiconductor device is more stable by implementing the above structural manner through the process, and the first package 180 can protect and integrate the bridging die 330 and the passive component 370, thereby being more suitable for the structural manner that the first SoC 140 and the second SoC 150 are arranged side by side, and shortening the communication distance (or electrical path) between the socs and between the SoC and the passive component.

As shown in fig. 3, the first layer structure 310 includes at least one first conductive line layer 111, at least one first conductive via (through hole) layer 112, at least one first dielectric layer 113, and at least one first conductive contact 314. The first conductive contact 314 has a surface 314s and the outermost first dielectric layer 113 has a surface 113s, wherein the surface 314s is flush with the surface 113 s. In addition, the first conductive contact 314 is, for example, a conductive bump, a conductive pad, or the like. In one embodiment, the bridging die 330, the passive component 370, the first package 180, the conductive pillars 160, and the like are formed between the first layer structure 110 and the second layer structure 120, and these components (the bridging die 330, the passive component 370, the first package 180, the conductive pillars 160, and the like) form a stable structure, which can make the mechanical structure of the entire semiconductor device stable, and as described above, the stable structure having the bridging die 330 and the passive component 370 therein can significantly improve the performance of the SoC, so that the semiconductor device of the embodiment of the present invention has high bandwidth, high performance, high heat dissipation efficiency, and high mechanical stability.

Referring to fig. 4, fig. 4 is a schematic cross-sectional view of a semiconductor device 400 according to another embodiment of the invention. The semiconductor device 400 can be applied to HBPoP, inFO PoP, and the like.

As shown in fig. 4, the semiconductor device 400 includes a first layer structure 310, a second layer structure 120, at least one bridging die 330, at least one first SoC 140, at least one first SoC 150, at least one underfill 155, at least one conductive pillar 160, at least one passive device 270, a first package 180, and at least one conductive contact 190. The bridging die 330 is disposed between the first layer structure 310 and the second layer structure 120. The first SoC 140 and the second SoC 150 are disposed on the second layer structure 120, and the first SoC 140 and the second SoC 150 are electrically connected through the bridging die 330.

The semiconductor device 400 includes the same or similar features as the semiconductor device 300, except that, for example, the passive component 170 of the semiconductor device 300 may be replaced by the passive component 270 of the semiconductor device 400. In one embodiment, for example, at least two of the lower surface of the first package 180, the lower surfaces of the passive component 270 heating the first and second electrodes, the lower surface of the conductive post 160, and the lower surface of the bridging die 330 are flush, thereby forming a coplanar surface. The above structure of the present embodiment can ensure the stability and reliability of the contact and electrical connection between the conductive pillars 160, the conductive vias 132 bridging the die 130, and the like and the first layer structure 110, and the structural stability of the semiconductor device. In one embodiment, the lower surface of the bridging die 330 and the lower surfaces of the first and second electrodes of the passive component 270 are flush with the lower surface of the first package 180, i.e., the lower surface of the bridging die 330 and the lower surfaces of the first and second electrodes of the passive component 270 are not covered by the first package 180. In one embodiment, the upper surface of the bridging die 330 and the upper and lower surfaces of the passive component 270 are covered by the first package 180, so that the upper surface of the first package 180 is higher than the upper surface of the bridging die 330 and the upper surface of the passive component 270. In this way, the lower surfaces of the first electrode and the second electrode of the bridging die 330 and the passive component 270 are flush with the lower surface of the first package 180, and the upper surfaces and the lower surfaces of the bridging die 330 and the passive component 270 are covered by the first package 180, so that the structure of the semiconductor device is more stable by the process, and the first package 180 can protect and integrate the bridging die 330 and the passive component 270, thereby being more suitable for the structure that the first SoC 140 and the second SoC 150 are arranged side by side, and shortening the communication distance (or electrical path) between the socs and between the SoC and the passive component. In one embodiment, the bridging die 330, the passive component 270, the first package 180, the conductive pillars 160, and the like are formed between the first layer structure 110 and the second layer structure 120, and these components (the bridging die 330, the passive component 270, the first package 180, the conductive pillars 160, and the like) form a stable structure, which can make the mechanical structure of the entire semiconductor device stable, and as described above, the stable structure having the bridging die 330 and the passive component 270 therein can significantly improve the performance of the SoC, so that the semiconductor device of the embodiment of the present invention has high bandwidth, high performance, high heat dissipation efficiency, and high mechanical stability.

Referring to fig. 5, fig. 5 is a schematic cross-sectional view of a semiconductor device 500 according to another embodiment of the invention. The semiconductor device 500 can be applied to HBPoP, inFO PoP, and the like.

As shown in fig. 5, the semiconductor device 500 includes a first layer structure 110, a second layer structure 120, at least one bridging die 130, at least one first SoC 140 and at least one first SoC 150, at least one conductive pillar 160, at least one passive component 170, a first package 180, at least one conductive contact 190, and a second package 580.

The semiconductor device 500 includes the same or similar features as the semiconductor device 100 except, for example, that the semiconductor device 500 further includes a second package 580. In addition, in the embodiments of fig. 1B, 2, 3, 4, etc., a second package may be provided to package the SoC.

As shown in fig. 5, the second package 580 is formed on the second layer structure 120 and encapsulates the first SoC 140 and the second SoC 150 to protect the first SoC 140 and the second SoC 150. The second package 580 is, for example, a molding compound. The molding compound may be formed from a molding compound that includes, for example, a novolac-based resin, an epoxy-based resin, a silicone-based resin, or other suitable sealant. The molding compounds may also include suitable fillers, such as powdered SiO 2. The molding material may be applied using any of a variety of molding techniques, such as compression molding, injection molding, or transfer molding.

In another embodiment, the semiconductor device 200 may further have a second package 580 for packaging the first SoC 140 and the second SoC 150 to protect the first SoC 140 and the second SoC 150.

Referring to fig. 6, fig. 6 is a schematic cross-sectional view of a semiconductor device 600 according to another embodiment of the invention. The semiconductor device 600 can be applied to HBPoP, inFO PoP, and the like.

As shown in fig. 6, the semiconductor device 600 includes a first layer structure 310, a second layer structure 120, at least one bridging die 330, at least one first SoC 140 and at least one first SoC 150, at least one conductive pillar 160, at least one passive device 370, a first package 180, at least one conductive contact 190, and a second package 580.

The semiconductor device 600 includes the same or similar features as the semiconductor device 300 except that, for example, the semiconductor device 600 further includes a second package 580 that encapsulates the first SoC 140 and the second SoC 150 for protecting the first SoC 140 and the second SoC 150.

In another embodiment, the semiconductor device 400 may further have a second package 580 for packaging the first SoC 140 and the second SoC 150 to protect the first SoC 140 and the second SoC 150.

Referring to fig. 7A and 7B, fig. 7A is a top view of a semiconductor device 700 according to another embodiment of the invention, and fig. 7B is a cross-sectional view taken along line 7B-7B' of the semiconductor device 700 of fig. 7A. The semiconductor device 700 may be applied to HB (high bandwidth) PoP (stacked package), fan-out PoP, or the like.

As shown in fig. 7B, the semiconductor device 700 includes a first layer structure 110, a second layer structure 120, at least one bridging die 130, at least one first SoC140 and at least one first SoC 150, at least one conductive pillar 160, at least one passive component 170, a first package 180, at least one conductive contact 190, and at least one memory die 640.

As shown in fig. 7B, the semiconductor device 700 includes the same or similar features as those of the semiconductor device 100, except that, for example, the semiconductor device 700 includes a memory die 640.

As shown in fig. 7B, a memory die 640 is disposed on the second layer structure 120. The first SoC140, the first SoC 150, and the memory die 640 are electrically connected to each other through the bridge die 640. In the present embodiment, the first SoC140, the second SoC 150 and the memory die 640 are not directly connected, but indirectly connected to the bridging die 130 through the second layer structure 120. The memory die 640 is, for example, a DRAM (dynamic random access memory ) or the like.

In another embodiment, the semiconductor apparatus 700 may further include the second package 580 of fig. 5 encapsulating the first SoC140, the first SoC 150, and the memory die 640 to protect the first SoC140, the first SoC 150, and the memory die 640.

In other embodiments, semiconductor device 200 may further include memory die 640 disposed on second layer structure 120, semiconductor device 300 may further include memory die 640 disposed on second layer structure 120, and semiconductor device 400 may further include memory die 640 disposed on second layer structure 120. In one embodiment, as shown in fig. 7A, in top view, the bridging die 130 may partially overlap the first SoC 140, the bridging die 130 may also partially overlap the second SoC150, and the bridging die 130 may also partially overlap the memory die 640, such that the bridging die 130 may be electrically connected to the first SoC 140, the second SoC150, and the memory die 640 at the same time, at a shorter distance. In one embodiment, the bridging die 130 may be used for signal connection and transmission, and the bridging die 130 may also be used for power/ground connection of the SoC and the memory die, so that the bridging die 130 in this embodiment may be used for not only electrical connection (e.g. signal transmission) of the first SoC 140, the first SoC150 and the memory die 640, but also electrical connection/ground connection of the first SoC 140, the first SoC150 and the memory die 640, so that not only electrical connection paths of the first SoC 140, the first SoC150 and the memory die 640 are shorter, but also electrical connection paths of the first SoC 140, the first SoC150 and the memory die 640 are shorter, and performance of the semiconductor device is comprehensively improved. In one embodiment, the bridging die 130 may provide more connection channels for transmitting a greater number of signals, thereby providing high bandwidth electrical connections for the first SoC 140, the first SoC150, and the memory die 640, and thus the manner of embodiments of the present invention is applicable to high bandwidth packages or high bandwidth semiconductor devices. In one embodiment, the conductive via 132 may be used for signal connection and transmission, and the conductive via 132 may also be used for power/ground connection of the SoC and the memory die 640, so that the bridge die 130 in this embodiment may be used for not only electrical connection (e.g., signal transmission) of the first SoC 140, the first SoC150 and the memory die 640, but also electrical connection/ground connection of the first SoC 140, the first SoC150 and the memory die 640, so that not only electrical connection paths of the first SoC 140, the first SoC150 and the memory die 640 are shorter, but also electrical connection paths of the first SoC 140, the first SoC150 and the memory die 640 are shorter, thereby comprehensively improving performance of the semiconductor device. In one embodiment, the bridging die 130 may provide more connection channels for transmitting a greater number of signals, thereby providing high bandwidth electrical connections for the first SoC 140, the first SoC150, and the memory die 640, and thus the manner of embodiments of the present invention is applicable to high bandwidth packages or high bandwidth semiconductor devices. In one embodiment, for example, the height of the conventional stacked package structure may be higher, and in an embodiment, the first SoC 140, the second SoC150 and the memory die 640 are disposed side by side (instead of being disposed in a stacked manner), so that the upper limit of the height (thickness) of the first SoC 140 and/or the second SoC150 may be higher, that is, the height (thickness) of the respective die in the first SoC 140 and/or the second SoC150 may be set higher (or thicker), so as to improve the thermal capability (for example, the capability of accommodating heat), so that the heat is easier to be dissipated, so as to improve the heat dissipation of the package, and ensure the stable operation of the SoC, the die, and other components. In one embodiment, passive component 170 may cover the complete SoC in a top view; for example, passive components under the first SoC 140 are completely covered by the first SoC 140, and passive components under the second SoC150 are completely covered by the second SoC 150. Therefore, the electric connection distance between the passive component below the corresponding SoC and the SoC is as short as possible, and the electric performance is improved. In the embodiment of the invention, the bridging die 130 and the passive component 170 are skillfully integrated in the first package 180, so that the integration degree of the components is improved, the whole semiconductor device structure is more stable, and the corresponding designs of the bridging die 130, the passive component 170 and the SoC in the embodiment of the invention can remarkably improve the performance of the semiconductor device and the signal transmission efficiency. Therefore, the design layout of the embodiment of the invention is more scientific and reasonable, and the applicability is wider. In one embodiment, memory die 640 may be replaced with a memory package. In one embodiment, at least one of the first SoC 140 and the second SoC150 may be replaced with a semiconductor die (e.g., a SoC die). Of course, other modification designs can be made in the embodiment of the present invention, so as to improve the flexibility and design elasticity of the embodiment of the present invention.

Referring to fig. 8A to 8I, fig. 8A to 8I are schematic views illustrating a manufacturing method of the semiconductor device 100 of fig. 1B.

As shown in fig. 8A, a second layer structure 120 (first) is formed on the first carrier 10 through a first release layer 20, wherein the second layer structure 120 includes at least one second conductive line layer 121, at least one second conductive via layer 122, at least one second dielectric layer 123 and at least one second conductive contact 124, wherein two adjacent second conductive line layers (conductive line layers) 121 are separated from one of the second dielectric layers 123, and the two adjacent second conductive line layers 121 can be electrically connected through one of the second conductive via layers 122. The second conductive contact 124 has a surface 124s and the outermost second dielectric layer 123 has a surface 123s, wherein the surface 124s and the surface 123s are flush with each other. The second conductive line layer 121, the second conductive path layer 122, and the second conductive contact 124 may be formed by plating or the like, and the second dielectric layer 123 may be formed by photolithography or the like, for example.

As shown in fig. 8B, at least one conductive pillar 160' is formed on the second layer structure 120 using a method such as electroplating. In addition, the conductive pillar 160' has a second surface 160s2, and the second surface 160s2 is formed on the second conductive line layer (conductive trace layer) 121 or the second conductive via layer 122 of the second layer structure 120 and electrically connected to the second conductive line layer (conductive trace layer) 121 or the second conductive via layer 122 of the second layer structure 120.

As shown in fig. 8C, at least one bridging die 130 'and at least one passive component 170' are disposed on the second layer structure 120 using, for example, SMT (Surface mount technology ).

The bridging die 130 'includes a silicon-based substrate 131', a plurality of conductive vias 132, and a plurality of conductive contacts 133. The silicon-based substrate 131 'has a first surface 131s1' and a second surface 131s2 opposite to the first surface 131s1', wherein the conductive via 132 is exposed to the second surface 131s2 but not to the first surface 131s1'. Each conductive contact 133 is electrically connected to a respective conductive via 132. The conductive via 132 may be electrically connected to the second layer structure 120 by a conductive contact 133.

The passive component 170 'includes a substrate 171' and a plurality of conductive contacts 172. The substrate 171' is, for example, a silicon-based substrate. The substrate 171' has a first surface 171s1' and a second surface 171s2 opposite to the first surface 171s 1'. A conductive contact 172 is formed on a side adjacent to the second surface 171s2 of the substrate 171. The conductive contact 172 may be electrically connected to the second layer structure 120. For example, the conductive contact 171 may be electrically connected to the conductive trace layer 121 or the second conductive via layer 122 of the second layer structure 120. The conductive contacts 172 are, for example, solder balls, conductive bumps, conductive pads, and the like.

As shown in fig. 8D, the first encapsulant material 180' encapsulates the at least one bridging die 130', the at least one passive component 170', the at least one conductive post 160', and the first encapsulant material 180' is formed over the second layer structure 120, such as by compression molding, injection molding, or transfer molding.

As shown in fig. 8E, a portion of the first package material 180', a portion of the bridging die 130', a portion of the passive component 170', and a portion of the conductive pillars 160' are removed, for example, using CMP (Chemical-Mechanical Planarization, chemical mechanical planarization), to form the first package 180, the bridging die 130, the passive device 170, and the conductive pillars 160, respectively. After removal, a coplanar surface is formed that includes at least two of a portion of the first package 180, a portion of the passive device 170, a portion of the conductive pillars 160, and a portion of the bridging die 130. For example, the removed first package 180 has a first surface 180s1, the bridge die 130 has a first surface 131s1, the conductive via 132 has a first surface 132s1, the passive device 170 has a first surface 171s1, and the conductive pillar 160 has a first surface 160s1, wherein the first surface 180s1, the first surface 131s1, the first surface 132s1, the first surface 171s1 and the first surface 160s1 are flush with each other.

As shown in fig. 8F, a first layer structure 110 (second) is formed over at least one bridging die 130, at least one conductive post 160, at least one passive component 170, and a first package 180. The first layer structure 110 (second) comprises at least one first wire layer 111, at least one first conductive via layer 112, at least one first dielectric layer 113 and at least one first conductive contact 114, wherein adjacent two first wire layers (conductive tracks) 111 are spaced apart from one of the first dielectric layers 113, and adjacent two first wire layers 111 may be electrically connected by one of the first conductive via layers 112. The first conductive contact 114 is electrically connected to the first conductive line layer 111 or the first conductive via layer 112 of the first layer structure 110 and protrudes with respect to the surface 113s of the outermost first dielectric layer 113. The first conductive line layer 111, the first conductive via layer 112, and the first conductive contact 114 may be formed by electroplating or the like, and the first dielectric layer 113 may be formed by photolithography or the like.

As shown in fig. 8F, at least one conductive contact 190 is formed on the first layer structure 110. For example, the conductive contact 190 is formed on the first conductive contact 114 of the first layer structure 110.

As shown in fig. 8G, the first carrier 10 of fig. 8F with the first release layer 20 is removed to expose the second dielectric layer 123 and the second conductive contact 124.

As shown in fig. 8H, the structure of fig. 8G is inverted so that the second dielectric layer 123 and the second conductive contact 124 face upward.

As shown in fig. 8I, at least one first SoC 140 and at least one second SoC 150 are disposed on the second layer structure 120 using, for example, SMT. The first SoC 140 and the second SoC 150 are electrically connected to the second conductive contact 124 of the second layer structure 120.

Then, the underfill 155 of fig. 1B is formed between the first SoC 140 of fig. 8I and the second layer structure 120 of fig. 8I to encapsulate the contact between the first SoC 140 of fig. 8I and the second layer structure 120, and the other underfill 155 of fig. 1B is formed between the second SoC 150 of fig. 8I and the second layer structure 120 of fig. 8I to encapsulate the contact between the second SoC 150 of fig. 8I and the second layer structure 120 of fig. 8I. Thus, the semiconductor device 100 is completed.

The semiconductor device 200 may be formed by the same or similar manufacturing method as the semiconductor device 100, and the same points will not be repeated.

Referring to fig. 9A to 9I, fig. 9A to 9I are schematic views illustrating a manufacturing method of the semiconductor device 300 of fig. 3.

As shown in fig. 9A, a first layer structure 310 (first) is formed on the first carrier 10 by the first release layer 20. The first layer structure 310 comprises at least one first wire layer (conductive line layer) 111, at least one first conductive via layer 112, at least one first dielectric layer 113 and at least one first conductive contact 314, wherein adjacent two first conductive line layers 111 are separated from one of the first dielectric layers 113 and adjacent two first conductive line layers 111 may be electrically connected by one of the first conductive via layers 112. The first conductive contact 314 is electrically connected to the first conductive trace layer 111 or the first conductive via layer 112 of the first layer structure 310. The first conductive contact 314 has a surface 314s and the outermost first dielectric layer 113 has a surface 113s, wherein the surface 314s is flush with the surface 113 s. The first conductive line layer 111, the first conductive path layer 112, and the first conductive contact 314 may be formed by electroplating or the like, and the first dielectric layer 113 may be formed by photolithography or the like, for example.

As shown in fig. 9B, at least one conductive pillar 160' is formed on the first layer structure 310 using a method such as electroplating. In addition, the conductive pillar 160' has a first surface 160s1, and the first surface 160s1 is formed on the first conductive line layer 111 or the first conductive via layer 112 of the first layer structure 310 and electrically connected to the first conductive line layer 111 or the first conductive via layer 112 of the first layer structure 310.

As shown in fig. 9C, at least one bridging die 330 'and at least one passive component 370' are disposed on the first layer structure 310 using, for example, SMT.

The passive device 370 comprises a substrate 171, at least one conductive contact 172 and at least one conductive contact 373', wherein the conductive contact 373' is electrically connected to the conductive contact 172 and protrudes with respect to the conductive contact 172. The bridging die 330 'includes a silicon-based substrate 131, a plurality of conductive contacts 133, and a plurality of conductive contacts 334'. A conductive contact 334' is formed on and electrically connected to the conductive contact 133 and protrudes with respect to the conductive contact 133.

As shown in fig. 9D, the at least one bridging die 330', the at least one passive component 370', the at least one conductive post 160', and the first encapsulant material 180' are formed over the first layer structure 310, for example, by using compression molding, injection molding, or transfer molding.

As shown in fig. 9E, a portion of the first package material 180', a portion of the bridging die 330', a portion of the passive component 370', and a portion of the conductive pillars 160' are removed, for example, using CMP, to form the first package 180, the bridging die 330, the passive device 370, and the conductive pillars 160, respectively. After removal, a coplanar surface is formed that includes at least two of a portion of the first package 180, a portion of the passive device 370, a portion of the conductive pillars 160, and a portion of the bridging die 330. For example, the removed first package 180 has a second surface 180s2, the conductive contact 334 bridging the die 330 has a surface 334s, the conductive contact 373 of the passive device 370 has a surface 373s, and the conductive post 160 has a second surface 160s2, wherein the surface 373s of the passive component 370, the surface 334s bridging the die 330, the second surface 160s2 of the conductive post 160 and the second surface 180s2 of the first package 180 are flush with each other.

As shown in fig. 9F, a second layer structure 120 (second) is formed over the bridging die 330, the conductive pillars 160, the first encapsulant 180, and the passive component 370.

As shown in fig. 9G, at least one first SoC 140 and at least one second SoC 150 are disposed on the second layer structure 120 using, for example, SMT. The first SoC 140 and the second SoC 150 are electrically connected to the second conductive contact 124 of the second layer structure 120.

As shown in fig. 9H, an underfill 155 is formed between the first SoC 140 and the second layer structure 120 to encapsulate contacts between the first SoC 140 and the second layer structure 120, and another underfill 155 is formed between the second SoC 150 and the second layer structure 120 to encapsulate contacts between the second SoC 150 and the second layer structure 120.

As shown in fig. 9I, the first carrier 10 of fig. 9H with the first release layer 20 is removed to expose the conductive contacts 314 of the first layer structure 310.

At least one conductive contact 190 is then formed on the first layer structure 310. For example, conductive contact 190 is formed on exposed first conductive contact 314 of first layer structure 310. To this end, the semiconductor device 300 is completed.

The semiconductor device 400 may be formed by the same or similar manufacturing method as the semiconductor device 300, and the same points are not described again.

Referring to fig. 10A to 10H, fig. 10A to 10H are schematic diagrams illustrating a method for manufacturing the semiconductor device 500 of fig. 5.

As shown in fig. 10A, the structure of fig. 8E is formed, and then the first layer structure 110 is formed on the at least one bridge chip 130, the at least one conductive pillar 160, the at least one passive component 170 and the first package 180.

As shown in fig. 10B, the second carrier 30 is disposed on the first layer structure 110 through the second release layer 40, wherein the protrusions of the first conductive contacts 114 of the first layer structure 110 are embedded in the release layer 40.

As shown in fig. 10C, the second carrier 10 of fig. 10B with the second release layer 20 is removed to expose the second dielectric layer 123 and the second conductive contact 124.

As shown in fig. 10D, the structure of fig. 10C is inverted so that the second conductive contact 124 faces upward.

As shown in fig. 10E, at least one first SoC 140 and at least one second SoC 150 are disposed on the second layer structure 120 by using, for example, SMT. The first SoC 140 and the second SoC 150 are electrically connected to the second conductive contact 124 of the second layer structure 120.

As shown in fig. 10F, an underfill 155 is formed between the first SoC 140 and the second layer structure 120 to encapsulate contacts between the first SoC 140 and the second layer structure 120, and another underfill 155 is formed between the second SoC 150 and the second layer structure 120 to encapsulate contacts between the second SoC 150 and the second layer structure 120.

As shown in fig. 10G, a second package 580 is formed on the second layer structure 120, encapsulating the first SoC140 and the second SoC 150.

As shown in fig. 10H, the second carrier 30 of fig. 10G with the second release layer 40 is removed to expose the first conductive contact 114 of the first layer structure 110.

At least one conductive contact 190 is then formed on the first layer structure 110 of fig. 10H. For example, the conductive contact 190 is formed on the first conductive contact 114 of the first layer structure 110 of fig. 10H. Thus, the semiconductor device 500 of fig. 5 is completed.

The semiconductor device 600 may be formed by the same or similar manufacturing method as the semiconductor device 500, and the same points are not described again.

The semiconductor device 700 may be formed by the same or similar manufacturing method as the semiconductor device 100, and the same points are not repeated.

Those skilled in the art will readily observe that numerous modifications and alterations of the apparatus and method may be made while maintaining the teachings of the present invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims

1. A semiconductor device, comprising:

a first layer structure;

a second layer structure;

The first system single chip is arranged on the second layer structure; and

the second system single chip is arranged on the second layer structure;

2. The semiconductor device according to claim 1, further comprising:

the first package encapsulates the bridging die.

3. The semiconductor device according to claim 1, further comprising:

and the second packaging body packages the first system single chip and the second system single chip.

4. The semiconductor device of claim 1, wherein the bridging die comprises a silicon-based substrate and a through silicon via formed in the silicon-based substrate, and the through silicon via electrically connects the first system-on-chip and the second system-on-chip.

5. The semiconductor device of claim 1, wherein the bridging die comprises a silicon substrate and conductive contacts formed on a same side of the silicon substrate and electrically connecting the first system-on-chip and the second system-on-chip.

6. The semiconductor device according to claim 1, further comprising:

A memory die disposed on the second layer structure;

wherein the first system-on-chip, the second system-on-chip, and the memory die are electrically connected to one another through the bridging die.

7. The semiconductor device according to claim 1, further comprising:

the passive component is arranged between the first layer structure and the second layer structure;

wherein the passive device is disposed side by side with the bridging die.

8. The semiconductor device of claim 1, wherein at least one of the first layer structure and the second layer structure comprises a redistribution layer structure.

9. The semiconductor device according to claim 1, further comprising:

and the conductive column is connected with the first layer structure and the second layer structure.

10. The semiconductor device of claim 9, wherein the semiconductor device has a coplanar surface disposed on the first layer structure, the coplanar surface comprising a portion of the conductive pillars and a portion of the bridging die.

11. The semiconductor device of claim 9, wherein the semiconductor device has a coplanar surface disposed on the second layer structure, the coplanar surface comprising a portion of the conductive pillars and a portion of the bridging die.

12. A method for manufacturing a semiconductor device, comprising:

disposing a bridging die on the first one;

13. The method of manufacturing as set forth in claim 12, further comprising:

placing a passive component on the first one;

wherein the passive device is disposed side by side with the bridging die.

14. The method of manufacturing as set forth in claim 13, further comprising:

a portion of the passive component and a portion of the bridging die are removed to form a coplanar surface.

15. The method of manufacturing of claim 12, wherein the bridging die comprises a silicon-based substrate and a plurality of through silicon vias formed in the silicon-based substrate, and the method of manufacturing further comprises:

Forming a first encapsulant material to encapsulate the bridged die; and

a portion of the first encapsulant material and a portion of the bridging die are removed to form a coplanar surface.

16. The method of manufacturing as set forth in claim 12, further comprising:

a second package is formed to encapsulate the first system-on-chip and the second system-on-chip.

17. The method of manufacturing as set forth in claim 12, further comprising:

when forming the first one of the first layer structure and the second layer structure on the first carrier, the first structure is the second layer structure.

Before the first system single chip and the second system single chip are arranged on the second layer structure, the bridging crystal grain and the first carrier are turned over, so that the second layer structure faces upwards.

18. The method of manufacturing as set forth in claim 12, further comprising:

forming the first structure of the first layer structure and the second layer structure on the first carrier, wherein the first structure is the first layer structure; and

the second of the first layer structure and the second layer structure is formed on the bridging die, the second being the second layer structure.

19. The method of manufacturing as set forth in claim 12, further comprising:

forming a conductive pillar on the first one; and

a portion of the conductive pillars and a portion of the bridging die are removed to form the coplanar surface.

20. The method of manufacturing as set forth in claim 12, further comprising:

disposing the second on the second carrier;

removing the first from the first carrier to expose the first; and

before the first system single chip and the second system single chip are arranged on the second layer structure, the first system single chip, the second carrier and the bridging crystal grain are turned over, so that the first system single chip faces upwards.