TWI761232B - Vertical light emitting diode die package with electrical detection position - Google Patents

Vertical light emitting diode die package with electrical detection position Download PDF

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TWI761232B
TWI761232B TW110121197A TW110121197A TWI761232B TW I761232 B TWI761232 B TW I761232B TW 110121197 A TW110121197 A TW 110121197A TW 110121197 A TW110121197 A TW 110121197A TW I761232 B TWI761232 B TW I761232B
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electrode
die
type
emitting diode
position contact
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TW202249311A (en
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陳復邦
張志強
黃長清
賴俊銘
黃文星
蔡增光
黃國欣
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聯嘉光電股份有限公司
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Abstract

本發明包含一發光二極體晶粒與一封裝載板,該發光二極體晶粒具有一半導體磊晶結構、一介面橫向延伸結構、一晶粒導電基座結構、一位於該半導體磊晶結構上方之N型電極與一位於該介面橫向延伸結構上的P型分流檢測電極,該晶粒導電基座結構具有位於下方側的ㄧP型主要電極,該封裝載板包含複數電極接點,其中透過該複數電極接點連接該N型電極、該P型分流檢測電極與該P型主要電極,而能夠以檢測電特性而評估該半導體磊晶結構與該晶粒導電基座結構內之一替代基板黏合層以及該P型主要電極與該封裝載板之間的一載板固晶黏合層之製程品質。且本發明亦將該複數電極接點連接至該封裝載板上方達成簡易與精準之電特性測試。The present invention includes a light-emitting diode die and a carrier board. The light-emitting diode die has a semiconductor epitaxial structure, an interface laterally extending structure, a die conductive base structure, and a semiconductor epitaxial structure. An N-type electrode above the structure and a P-type shunt detection electrode located on the interface laterally extending structure, the die conductive base structure has a P-type main electrode located on the lower side, the package carrier includes a plurality of electrode contacts, The N-type electrode, the P-type shunt detection electrode and the P-type main electrode are connected through the plurality of electrode contacts, so that one of the semiconductor epitaxial structure and the die conductive base structure can be evaluated by detecting electrical characteristics. Substitute the process quality of the substrate adhesive layer and a carrier die bonding adhesive layer between the P-type main electrode and the package carrier. In addition, the present invention also connects the plurality of electrode contacts to the top of the package carrier to achieve simple and accurate electrical characteristic testing.

Description

具有電性檢測位置之垂直式發光二極體晶粒封裝體Vertical light emitting diode die package with electrical detection position

本發明有關於發光二極體的晶粒結構,尤其有關於具有電性檢測點之垂直式發光二極體晶粒與其對應之封裝體。The present invention relates to a die structure of a light emitting diode, and more particularly, to a vertical light emitting diode die with electrical detection points and a corresponding package.

發光二極體(LED),為一種可以利用半導體之電子與電洞複合產生高亮度的光源。產品可使用於高光度殺菌(紫外光)、車用頭燈與尾燈(藍黃紅光)、投影機光源(藍綠紅)、紅外線安防偵測(紅外線)。優秀的高功率LED元件除了高發光度與發光密度外,也需要有良好的信賴度。以汽車頭燈模組為例,一旦LED失效,會影響夜間安全,以車用LED之高標準規範,即使1ppm之微量失效,在汽車業也是需要改善,所以元件準確的光電特性檢測性非常重要。A light emitting diode (LED) is a light source that can generate high brightness by recombining electrons and holes in semiconductors. Products can be used for high-light sterilization (ultraviolet light), vehicle headlights and taillights (blue-yellow-red light), projector light sources (blue-green-red), and infrared security detection (infrared). In addition to high luminosity and luminous density, excellent high-power LED components also need to have good reliability. Taking the car headlight module as an example, once the LED fails, it will affect the safety at night. With the high standard of automotive LEDs, even if a small amount of 1ppm fails, it needs to be improved in the automotive industry, so the accurate photoelectric characteristics of the components are very important. .

如圖1所示,在一實施例中,一垂直式LED晶粒1於SMD封裝時,為將P電極2透過一載板固晶黏合層4A黏合於封裝載板3的固晶導電底座4上,而N電極5則藉由打線讓金導線6電性連接至打線端點7上,固晶導電底座4與打線端點7分別透過導通金屬8而電性連接位於封裝載板3另一側的陽極9A(Anode)與陰極9B(Cathode)。As shown in FIG. 1 , in an embodiment, when a vertical LED die 1 is packaged in an SMD package, the P electrode 2 is bonded to the die-bonding conductive base 4 of the package carrier 3 through a die-bonding adhesive layer 4A of the carrier board. On the other hand, the N electrode 5 is electrically connected to the wire bonding terminal 7 by the gold wire 6 through the wire bonding. Anode 9A (Anode) and cathode 9B (Cathode) on the side.

對於垂直式LED來說,垂直式LED晶粒1的主體結構由上至下包含一半導體磊晶結構1A、一介面結構1B與一晶粒導電基座結構1C等三部分。For a vertical LED, the main structure of the vertical LED die 1 includes three parts from top to bottom: a semiconductor epitaxial structure 1A, an interface structure 1B and a die conductive base structure 1C.

其中,該半導體磊晶結構1A由上而下依序為N型半導體、發光層、P型半導體。該晶粒導電基座結構1C由上而下依序為結構金屬層、替代基板黏合層1C1、高導熱替代基板。該介面結構1B一般為具有局部或全面之金屬以歐姆接觸方式連接該半導體磊晶結構1A的P型半導體與該晶粒導電基座結構1C的結構金屬層。該高導熱替代基板的下方為該P電極2。The semiconductor epitaxial structure 1A is an N-type semiconductor, a light-emitting layer, and a P-type semiconductor in order from top to bottom. The die conductive base structure 1C is composed of a structural metal layer, a substitute substrate adhesive layer 1C1, and a high thermal conductivity substitute substrate in sequence from top to bottom. The interface structure 1B is generally a structural metal layer with partial or full metal that connects the P-type semiconductor of the semiconductor epitaxial structure 1A and the die conductive base structure 1C in an ohmic contact manner. Below the high thermal conductivity substitute substrate is the P electrode 2 .

晶粒導電基座結構1C主要以下方之高導熱替代基板為主要支撐結構,其利用該替代基板黏合層1C1以晶圓級方式於晶片製程中與上方之結構金屬層黏合,通常使用金屬共晶方式(Eutectic bonding)(如金錫共晶(AuSn Eutectic bonding))進行金屬黏合,其平整貼合製程存在良率問題,若當於黏合製程受到不良之原料與製程而形成不平整面、孔洞或汙染時會異常增加阻抗,導致晶粒於高電流操作下形成不均勻電流造成局部熱點,導致光效降低與信賴度降低。The die conductive base structure 1C mainly uses the high thermal conductivity substitute substrate below as the main support structure, and uses the substitute substrate adhesive layer 1C1 to bond with the upper structural metal layer in the wafer process in a wafer-level manner, usually using a metal eutectic. For metal bonding using Eutectic bonding (such as AuSn Eutectic bonding), there is a yield problem in the flat bonding process. If the bonding process is subjected to poor materials and processes, uneven surfaces, holes or When polluted, the impedance will increase abnormally, resulting in the formation of uneven current in the die under high current operation, resulting in local hot spots, resulting in reduced light efficiency and reduced reliability.

另外,垂直式LED晶粒1與封裝載板3需要使用載板固晶黏合層4A以達到導電固晶黏合,(通常亦使用金屬共晶(Eutectic bonding)方式進行金屬固晶導電黏合,若垂直式LED晶粒底部不平整與貼合粒子汙染(particle),也會造成底部接面於高電流操作下電阻升高,形成局部熱點,導致元件燒毀。In addition, the vertical LED die 1 and the package carrier 3 need to use the carrier die bonding layer 4A to achieve conductive die bonding, (usually metal eutectic bonding is also used for metal die bonding. The uneven bottom of the LED die and the contamination of the attached particles will also cause the resistance of the bottom junction to increase under high current operation, forming a local hot spot and causing the component to burn out.

最後,需進行垂直式LED封裝製程的元件的光電性量測,可以利用陽極(Anode)9A與陰極(Cathode)9B作為測試接點並配合使用一測試儀器檢進行檢測,以滿足車用LED之高標準規範。Finally, for the optoelectronic measurement of the components that need to be carried out in the vertical LED packaging process, the anode (Anode) 9A and the cathode (Cathode) 9B can be used as test contacts and a test instrument can be used for detection to meet the requirements of automotive LEDs. High standard specification.

然而,習知檢測垂直式LED晶粒1時,當發現異常高電壓電特性(高Vf),其為半導體磊晶結構、介面結構與晶粒導電基座結構之整體電特性,無法確認異常來源為半導體磊晶結構部分或是晶粒導電基座結構部分之替代基板黏合層與載板固晶黏合層4A。However, when detecting the vertical LED die 1 in the prior art, abnormal high voltage electrical characteristics (high Vf) are found, which are the overall electrical characteristics of the semiconductor epitaxial structure, the interface structure and the die conductive base structure, and the source of the abnormality cannot be identified. It is a substitute for the substrate adhesive layer and the carrier die bonding layer 4A for the semiconductor epitaxial structure part or the die conductive base structure part.

另外對於半導體層之微量電壓與電流之二極體特性,由於晶粒導電基座結構之雜訊影響,無法精準量測其於順向偏壓與逆向偏壓之微小電特性,造成磊晶品質判斷不易。In addition, for the diode characteristics of the trace voltage and current of the semiconductor layer, due to the influence of the noise of the conductive base structure of the die, it is impossible to accurately measure the tiny electrical characteristics of the forward bias voltage and reverse bias voltage, resulting in epitaxial quality. Judgment is not easy.

爰此,本發明之主要目的在於揭露具有多個電性測試位置接點之垂直式發光二極體晶粒封裝體,以滿足半導體磊晶結構、介面結構、晶粒導電基座結構與封裝載板之間的各層的精確電特性測試。Therefore, the main purpose of the present invention is to disclose a vertical light emitting diode die package with a plurality of electrical test position contacts to meet the requirements of semiconductor epitaxial structure, interface structure, die conductive base structure and package carrier structure. Accurate electrical characterization of layers between boards.

本發明為一種具有電性檢測位置之垂直式發光二極體晶粒封裝體,其包含一發光二極體晶粒與一封裝載板,其中該發光二極體晶粒具有一晶粒導電基座結構、一介面橫向延伸結構一半導體磊晶結構、一N型電極與一P型分流檢測電極。其中該晶粒導電基座結構具有一位於下方側的P型主要電極,該P型主要電極以平面固晶導電方式與該封裝載板電性相連。本發明之該介面橫向延伸結構,其包含依序堆疊的一高濃度P型半導體層、一歐姆接觸層與一高導電金屬層所構成。該晶粒導電基座結構遠離該P型主要電極的一側設置該介面橫向延伸結構,於該介面橫向延伸結構的上方平面分別設置該半導體磊晶結構與該P型分流檢測電極。該半導體磊晶結構與該晶粒導電基座結構之間為藉由該介面橫向延伸結構達到歐姆接觸。The present invention is a vertical light-emitting diode die package with an electrical detection position, which comprises a light-emitting diode die and a carrier board, wherein the light-emitting diode die has a die conductive base A seat structure, an interface lateral extension structure, a semiconductor epitaxial structure, an N-type electrode and a P-type shunt detection electrode. The die conductive base structure has a P-type main electrode located on the lower side, and the P-type main electrode is electrically connected to the package carrier in a planar die-bonding conductive manner. The lateral extension structure of the interface of the present invention comprises a high concentration P-type semiconductor layer, an ohmic contact layer and a high conductive metal layer which are sequentially stacked. The side of the die conductive base structure away from the P-type main electrode is provided with the interface laterally extending structure, and the semiconductor epitaxial structure and the P-type shunt detection electrode are respectively provided on the upper plane of the interface laterally extending structure. An ohmic contact is achieved between the semiconductor epitaxial structure and the die conductive base structure through the interface laterally extending structure.

該半導體磊晶結構遠離該晶粒導電基座結構的一側設置該N型電極。本發明之該晶粒導電基座結構更具有一結構金屬層、一替代基板黏合層與一高導熱替代基板,其中該結構金屬層位於該介面橫向延伸結構之下方,該結構金屬層之下方以該替代基板黏合層黏合該高導熱替代基板,該高導熱替代基板的下方設置該P型主要電極。該介面橫向延伸結構最下方的該高導電金屬層需為化性穩定與有利於歐姆接觸材料,才能與該晶粒導電基座結構最上方的該結構金屬層相連接,而該結構金屬層需為化性穩定與有利於後續金屬共晶(Eutectic bonding)的材料。The N-type electrode is disposed on a side of the semiconductor epitaxial structure away from the die conductive base structure. The die conductive base structure of the present invention further has a structural metal layer, a substitute substrate adhesive layer and a high thermal conductivity substitute substrate, wherein the structural metal layer is located under the laterally extending structure of the interface, and below the structural metal layer The substitute substrate adhesive layer is bonded to the high thermal conductivity substitute substrate, and the P-type main electrode is disposed below the high thermal conductivity substitute substrate. The highly conductive metal layer at the bottom of the laterally extending structure of the interface needs to be chemically stable and favorable for ohmic contact, so as to be connected to the structure metal layer at the top of the die conductive base structure, and the structure metal layer needs to be It is a material that is chemically stable and beneficial to subsequent eutectic bonding.

該高導熱替代基板位於該晶粒導電基座結構內為主要結構支撐層,藉由該替代基板黏合層以金屬共晶黏合(Eutectuc Bonding),將該高導熱替代基板與上方包含該半導體磊晶結構之該結構金屬層相連結,該高導熱替代基板之下方為該P型主要電極。The high thermal conductivity substitute substrate is located in the die conductive base structure as the main structural support layer, and the high thermal conductivity substitute substrate is bonded with the semiconductor epitaxial above by the substitute substrate bonding layer by metal eutectic bonding (Eutectuc Bonding). The structural metal layer of the structure is connected, and the P-type main electrode is under the high thermal conductivity substitute substrate.

而該封裝載板具有位於兩側的一上側平面與一下側平面,該下側平面設置一陽極與一陰極,而該上側平面設置一主元件第一電極、一主元件第二電極、一主元件第三電極、一電性測試第一位置接點、一電性測試第二位置接點與一電性測試第三位置接點,其中該N型電極與該主元件第一電極為以一晶粒第一打線金屬電性連接,該P型分流檢測電極與該主元件第二電極為以一晶粒第二打線金屬電性連接,該P型主要電極則透過一載板固晶黏合層直接黏結該主元件第三電極而電性連接。而該電性測試第一位置接點電性連接該主元件第一電極與該陰極,該電性測試第二位置接點電性連接該主元件第二電極,該電性測試第三位置接點電性連接該主元件第三電極與該陽極。The package carrier has an upper plane and a lower plane on both sides, an anode and a cathode are arranged on the lower plane, and a first electrode of a main element, a second electrode of a main element, a main element are arranged on the upper plane The third electrode of the element, an electrical test first position contact, an electrical test second position contact and an electrical test third position contact, wherein the N-type electrode and the first electrode of the main element are connected by a The first wire bonding metal of the die is electrically connected, the P-type shunt detection electrode and the second electrode of the main element are electrically connected with a second wire bonding metal of the die, and the P-type main electrode is passed through a carrier board. The third electrode of the main element is directly bonded to be electrically connected. The first position contact of the electrical test is electrically connected to the first electrode of the main element and the cathode, the second position of the electrical test is electrically connected to the second electrode of the main element, and the third position of the electrical test is connected to the cathode. The point is electrically connected to the third electrode of the main element and the anode.

據此,該電性測試第一位置接點透過該主元件第一電極而電性連接該N型電極,該電性測試第二位置接點透過該主元件第二電極而電性連接該P型分流檢測電極,而該N型電極與該P型分流檢測電極之間的電特性即為該半導體磊晶結構與該介面橫向延伸結構的電特性。Accordingly, the electrical test first position contact is electrically connected to the N-type electrode through the main element first electrode, and the electrical test second position contact is electrically connected to the P through the main element second electrode type shunt detection electrode, and the electrical characteristics between the N-type electrode and the P-type shunt detection electrode are the electrical characteristics of the semiconductor epitaxial structure and the interface laterally extending structure.

故透過於該電性測試第一位置接點與該電性測試第二位置接點進行檢測可得知該半導體磊晶結構與該介面橫向延伸結構之電特性,尤其可精準測得半導體磊晶結構(二極體)於順向偏壓與逆向偏壓下之微量電性精準數值,可更有效的評估該半導體磊晶結構的磊晶製程品質。Therefore, the electrical characteristics of the semiconductor epitaxial structure and the interface laterally extending structure can be known by detecting the first position contact of the electrical test and the second position contact of the electrical test, especially the semiconductor epitaxial structure can be accurately measured The precise value of the trace electrical properties of the structure (diode) under forward bias and reverse bias can more effectively evaluate the epitaxial process quality of the semiconductor epitaxial structure.

又該電性測試第三位置接點透過該主元件第三電極而電性連接該P型主要電極,故透過於該電性測試第二位置接點與該電性測試第三位置接點進行檢測可得知該晶粒導電基座結構以及該P型主要電極與該主元件第三電極之間的該載板固晶黏合層的電特性,進而能夠評估該替代基板黏合層與該載板固晶黏合層的製程品質。In addition, the third position contact of the electrical test is electrically connected to the P-type main electrode through the third electrode of the main element, so the electrical test is carried out through the second position contact of the electrical test and the third position contact of the electrical test The electrical characteristics of the die conductive base structure and the carrier die bonding layer between the P-type main electrode and the third electrode of the main element can be obtained by testing, and then the substitute substrate bonding layer and the carrier can be evaluated. Process quality of die-bonding bonding layers.

為俾使  貴委員對本發明之特徵、目的及功效,有著更加深入之瞭解與認同,茲列舉一較佳實施例並配合圖式說明如後:In order to make your members have a more in-depth understanding and recognition of the features, purposes and effects of the present invention, hereby enumerates a preferred embodiment and cooperates with the drawings to describe as follows:

請參閱圖2與圖3所示,為本發明第一實施例,其包含一發光二極體晶粒10與一封裝載板30,其中該發光二極體晶粒10具有一晶粒導電基座結構11、一介面橫向延伸結構12、一半導體磊晶結構13、一N型電極14與一P型分流檢測電極15,其中該晶粒導電基座結構11具有位於下方側的一P型主要電極16,該晶粒導電基座結構11遠離該P型主要電極16的一側設置該介面橫向延伸結構12,於該介面橫向延伸結構12的上方平面分別該半導體磊晶結構13與該P型分流檢測電極15,該半導體磊晶結構13與該晶粒導電基座結構11之間為藉由該介面橫向延伸結構12達到歐姆接觸,該半導體磊晶結構13遠離該晶粒導電基座結構11的一側設置該N型電極14。Please refer to FIG. 2 and FIG. 3 , which is a first embodiment of the present invention, which includes a light-emitting diode die 10 and a carrier board 30 , wherein the light-emitting diode die 10 has a die conductive base The base structure 11, an interface lateral extension structure 12, a semiconductor epitaxial structure 13, an N-type electrode 14 and a P-type shunt detection electrode 15, wherein the die conductive base structure 11 has a P-type main Electrode 16, the side of the die conductive base structure 11 away from the P-type main electrode 16 is provided with the interface lateral extension structure 12, and the semiconductor epitaxial structure 13 and the P-type lateral extension structure 12 are respectively on the upper plane of the interface lateral extension structure 12. The shunt detection electrode 15 is in ohmic contact between the semiconductor epitaxial structure 13 and the die conductive base structure 11 through the interface lateral extension structure 12 , and the semiconductor epitaxial structure 13 is far away from the die conductive base structure 11 The N-type electrode 14 is provided on one side.

該封裝載板30具有位於兩側的一上側平面301與一下側平面302,該下側平面302設置一陽極313與一陰極311,而該上側平面301設置一主元件第一電極41、一主元件第二電極42、一主元件第三電極43、一電性測試第一位置接點51、一電性測試第二位置接點52與一電性測試第三位置接點53,其中該N型電極14與該主元件第一電極41為以一晶粒第一打線金屬61電性連接,該P型分流檢測電極15與該主元件第二電極42為以一晶粒第二打線金屬62電性連接,該P型主要電極16則透過一載板固晶黏合層431(固晶導電膠或金屬)直接黏結該主元件第三電極43而電性連接。該電性測試第一位置接點51電性連接該主元件第一電極41與該陰極311,該電性測試第二位置接點52電性連接該主元件第二電極42,該電性測試第三位置接點53電性連接該主元件第三電極43與該陽極313。The package carrier 30 has an upper plane 301 and a lower plane 302 on two sides. An anode 313 and a cathode 311 are disposed on the lower plane 302 , and a main element first electrode 41 and a main element are disposed on the upper plane 301 . The element second electrode 42 , a main element third electrode 43 , an electrical test first position contact 51 , an electrical test second position contact 52 and an electrical test third position contact 53 , wherein the N The P-type electrode 14 and the first electrode 41 of the main element are electrically connected with the first wire bonding metal 61 of a die, and the P-type shunt detection electrode 15 and the second electrode 42 of the main element are the second wire bonding metal 62 of a die. For electrical connection, the P-type main electrode 16 is electrically connected by directly bonding the third electrode 43 of the main element through a die-bonding adhesive layer 431 (die-bonding conductive adhesive or metal) on a carrier board. The electrical test first position contact 51 is electrically connected to the main element first electrode 41 and the cathode 311, the electrical test second position contact 52 is electrically connected to the main element second electrode 42, the electrical test The third position contact 53 is electrically connected to the third electrode 43 of the main element and the anode 313 .

在實際結構上,該封裝載板30可以選用陶瓷基板(氮化鋁、氧化鋁、碳化矽)、銅基板、BT(Bismaleimide Triazine)板等等,該封裝載板30可以採用單層板或是多層板。該主元件第一電極41與該陰極311透過一貫穿該封裝載板30的載板金屬第一導通金屬71而電性連接,該主元件第三電極43與該陽極313透過一貫穿該封裝載板30的載板金屬第二導通金屬73而電性連接。另,該封裝載板30可以是多層板結構,該電性測試第一位置接點51與該主元件第一電極41之間、該電性測試第二位置接點52與該主元件第二電極42之間以及該電性測試第三位置接點53與該主元件第三電極43之間的電性連接方式,可以使用埋藏於該封裝載板30內的金屬導電層303、304、305(如圖3所繪製)來電性連接,且該金屬導電層303、304、305亦可形成於該封裝載板30的該上側平面301(如圖7所示)。In actual structure, the package carrier 30 can be a ceramic substrate (aluminum nitride, aluminum oxide, silicon carbide), a copper substrate, a BT (Bismaleimide Triazine) board, etc. The package carrier 30 can be a single-layer board or a Multilayer board. The main element first electrode 41 and the cathode 311 are electrically connected through a carrier metal first conductive metal 71 penetrating the package carrier 30 , and the main element third electrode 43 and the anode 313 are electrically connected through a carrier metal first conducting metal 71 penetrating the package carrier 30 . The carrier metal of the board 30 is electrically connected to the second conductive metal 73 . In addition, the package carrier 30 can be a multilayer board structure, the electrical testing first position contact 51 and the main element first electrode 41, the electrical testing second position contact 52 and the main element second The electrical connection between the electrodes 42 and the electrical connection between the electrical test third position contact 53 and the main element third electrode 43 can use the metal conductive layers 303 , 304 , 305 buried in the package carrier 30 . (drawn in FIG. 3 ) are electrically connected, and the metal conductive layers 303 , 304 , 305 can also be formed on the upper plane 301 of the package carrier 30 (as shown in FIG. 7 ).

請再參閱圖4所示,在一實施例中,該半導體磊晶結構13包含依序堆疊的一P型半導體13A、一活性層13B與一N型半導體13C,其中該N型電極14位於該N型半導體13C上,而該晶粒導電基座結構11更具有依序堆疊的一高導熱替代基板11A、一替代基板黏合層11B與一結構金屬層11C。該P型半導體13A與該P型分流檢測電極15分別位於該介面橫向延伸結構12的不同位置上。該介面橫向延伸結構12包含依序堆疊的一高導電金屬層12A、一歐姆接觸層12B與一高濃度P型半導體導電層12C,並該P型分流檢測電極15位於該介面橫向延伸結構12的邊緣外側。該高導電金屬層12A位於該結構金屬層11C之上方,該P型半導體13A與該P型分流檢測電極15分別位於該高濃度P型半導體導電層12C上。在此實施例中,常用於四元(鋁、鎵、銦、磷)LED,該高濃度P型半導體導電層12C可以為p-GaP,該歐姆接觸層12B可為歐姆接觸金屬12B1搭配透明材料12B2,並歐姆接觸金屬12B1為複數柱狀(BeAu柱狀)結構(如圖4所示的斜線框)接觸連接上下兩層,或者該歐姆接觸金屬12B1亦可以為歐姆接觸導通區塊;該高導電金屬層12A則為Ag/TiW/Pt。Referring to FIG. 4 again, in one embodiment, the semiconductor epitaxial structure 13 includes a P-type semiconductor 13A, an active layer 13B and an N-type semiconductor 13C stacked in sequence, wherein the N-type electrode 14 is located on the On the N-type semiconductor 13C, the die conductive base structure 11 further has a high thermal conductivity substitute substrate 11A, a substitute substrate adhesive layer 11B and a structural metal layer 11C stacked in sequence. The P-type semiconductor 13A and the P-type shunt detection electrode 15 are respectively located at different positions of the interface laterally extending structure 12 . The interface lateral extension structure 12 includes a highly conductive metal layer 12A, an ohmic contact layer 12B and a high concentration P-type semiconductor conductive layer 12C stacked in sequence, and the P-type shunt detection electrode 15 is located on the interface lateral extension structure 12 . outside the edge. The highly conductive metal layer 12A is located above the structural metal layer 11C, and the P-type semiconductor 13A and the P-type shunt detection electrode 15 are respectively located on the high-concentration P-type semiconductor conductive layer 12C. In this embodiment, commonly used in quaternary (aluminum, gallium, indium, phosphor) LEDs, the high-concentration P-type semiconductor conductive layer 12C can be p-GaP, and the ohmic contact layer 12B can be an ohmic contact metal 12B1 with a transparent material 12B2, and the ohmic contact metal 12B1 is a complex columnar (BeAu columnar) structure (as shown in the oblique line frame in FIG. 4 ) to contact and connect the upper and lower layers, or the ohmic contact metal 12B1 can also be an ohmic contact conduction block; the high The conductive metal layer 12A is Ag/TiW/Pt.

請再參閱圖5所示,在另一實施例中,該P型分流檢測電極15可以直接位於該歐姆接觸層12B上。此結構通常用於氮化物藍光LED(鋁、鎵、銦、氮),該高濃度P型半導體導電層12C可以為p-GaN或p-InGaN;該歐姆接觸層12B為ITO,該高導電金屬層12A則為Ag與TiW。Referring to FIG. 5 again, in another embodiment, the P-type shunt detection electrode 15 may be directly located on the ohmic contact layer 12B. This structure is usually used for nitride blue LED (aluminum, gallium, indium, nitrogen), the high concentration p-type semiconductor conductive layer 12C can be p-GaN or p-InGaN; the ohmic contact layer 12B is ITO, the high conductive metal Layer 12A is Ag and TiW.

請再參閱圖6所示,在另一實施例中,該P型分流檢測電極15亦可以直接位於該高導電金屬層12A上。此結構通常用於氮化物藍光LED,該高濃度P型半導體導電層12C可以為p-GaN或p-InGaN;該歐姆接觸層12B為Ag,該高導電金屬層12A則為TiW或Pt或其混和物。Referring to FIG. 6 again, in another embodiment, the P-type shunt detection electrode 15 may also be directly located on the high conductive metal layer 12A. This structure is usually used for nitride blue LEDs, the high-concentration p-type semiconductor conductive layer 12C can be p-GaN or p-InGaN; the ohmic contact layer 12B is Ag, and the high-conductive metal layer 12A is TiW or Pt or its mixture.

具有該P型分流檢測電極15電性檢測之垂直式發光二極體晶粒與搭配之具有檢測位置之該封裝載板30設計如下。再參閱圖7所示,該封裝載板30的上側平面301可以具有一固晶底座33而作為該主元件第三電極43,該發光二極體晶粒10的P型主要電極16(圖7未顯露)導電固晶於該固晶底座33,該N型電極透過該晶粒第一打線金屬61電性連接該主元件第一電極41,該P型分流檢測電極15透過該晶粒第二打線金屬62電性連接該主元件第二電極42。且該封裝載板30的上側平面301亦可以具有二個不同的打線端點34A、34B,該二個不同的打線端點34A、34B分別作為該主元件第一電極41與該主元件第二電極42使用。The vertical light-emitting diode die with the P-type shunt detection electrode 15 for electrical detection and the package carrier 30 with the detection position are designed as follows. Referring to FIG. 7 again, the upper plane 301 of the package carrier 30 may have a die-bonding base 33 as the third electrode 43 of the main element, the P-type main electrode 16 of the light-emitting diode die 10 ( FIG. 7 ) (not shown) conductive die-bonding on the die-bonding base 33, the N-type electrode is electrically connected to the first electrode 41 of the main element through the first wire bonding metal 61 of the die, and the P-type shunt detection electrode 15 passes through the second die of the die The wire bonding metal 62 is electrically connected to the second electrode 42 of the main element. And the upper plane 301 of the package carrier 30 may also have two different wire bonding terminals 34A, 34B, and the two different wire bonding terminals 34A, 34B are respectively used as the first electrode 41 of the main element and the second electrode of the main element. Electrode 42 is used.

請再參閱圖8所示,該封裝載板30的下側平面302除了設置該陰極311與該陽極313之外,亦可以設置一增高層315,該增高層315的高度為與陰極311、該陽極313等高,可以增加滿足後續製程的需求。Referring again to FIG. 8 , in addition to the cathode 311 and the anode 313 , the lower plane 302 of the package carrier 30 can also be provided with an elevated layer 315 , and the height of the elevated layer 315 is equal to that of the cathode 311 and the anode 313 . The anode 313 is of the same height, which can be increased to meet the needs of subsequent processes.

請參閱圖9與圖10所示,為本發明第二實施例,與第一實施例相較之下,該封裝載板30更包含一副元件第一電極81、一副元件第二電極84與一電性測試第四位置接點54,其中該副元件第一電極81電性連接該電性測試第一位置接點51,該副元件第二電極84電性連接該電性測試第四位置接點54,且該副元件第一電極81與該副元件第二電極84之間電性連接一齊納二極體85。在實際實施上,該副元件第一電極81與該電性測試第一位置接點51之間為藉由該金屬導電層303而電性連接,而該副元件第二電極84與該電性測試第四位置接點54之間為藉由一金屬導電層306而電性連接。Please refer to FIG. 9 and FIG. 10 , which are the second embodiment of the present invention. Compared with the first embodiment, the package carrier 30 further includes a first electrode 81 of a sub-element and a second electrode 84 of a sub-element and an electrical test fourth position contact 54, wherein the secondary element first electrode 81 is electrically connected to the electrical test first position contact 51, and the secondary element second electrode 84 is electrically connected to the electrical test fourth A Zener diode 85 is electrically connected between the first electrode 81 of the sub-element and the second electrode 84 of the sub-element. In actual implementation, the first electrode 81 of the sub-element and the electrical testing first position contact 51 are electrically connected through the metal conductive layer 303 , and the second electrode 84 of the sub-element is electrically connected to the electrical test In the test, the contacts 54 at the fourth position are electrically connected through a metal conductive layer 306 .

又該齊納二極體85可以選用雙向齊納二極體(Bi-directional Zener Diodes),其包含不同向設置的單向齊納二極體85A與單向齊納二極體85B(如圖9所繪製)。或者亦可僅使用單向齊納二極體85A,若為單向齊納二極體85A(Zener Diode),則該單向齊納二極體85A需以相反極性並聯該發光二極體晶粒10。And this Zener diode 85 can choose bidirectional Zener Diodes (Bi-directional Zener Diodes), it comprises the unidirectional Zener diode 85A and the unidirectional Zener diode 85B which are arranged in different directions (as shown in the figure). 9 drawn). Alternatively, only the unidirectional zener diode 85A can be used. If it is a unidirectional zener diode 85A (Zener Diode), the unidirectional zener diode 85A needs to be connected in parallel with the light-emitting diode crystal with opposite polarity. 10 grains.

於本發明第二實施例中,發光二極體封裝結構電路會有4個測試接點,即該電性測試第一位置接點51、該電性測試第二位置接點52、該電性測試第三位置接點53與該電性測試第四位置接點54,如圖9所示,其中選擇該電性測試第一位置接點51與該電性測試第四位置接點54進行測試,可供測試該齊納二極體85是否正常運作。選擇該電性測試第二位置接點52與該電性測試第三位置接點53進行測試,可以得知該替代基板黏合層11B以及該P型主要電極16與該封裝載板30之間的該載板固晶黏合層431的電特性。In the second embodiment of the present invention, the light-emitting diode package structure circuit has four test contacts, namely, the electrical test first position contact 51, the electrical test second position contact 52, the electrical test Test the third position contact 53 and the electrical test fourth position contact 54, as shown in FIG. 9, wherein the electrical test first position contact 51 and the electrical test fourth position contact 54 are selected for testing , which can be used to test whether the Zener diode 85 operates normally. By selecting the electrical test second position contact 52 and the electrical test third position contact 53 for testing, it can be known that the substitute substrate adhesive layer 11B and the connection between the P-type main electrode 16 and the package carrier 30 are Electrical characteristics of the die-bonding adhesive layer 431 of the carrier.

選擇該電性測試第一位置接點51與該電性測試第二位置接點52進行測試,可精準檢測該半導體磊晶結構13於順向偏壓與逆向偏壓下之微量電壓與電流之特性。Selecting the electrical test first position contact 51 and the electrical test second position contact 52 for testing can accurately detect the difference between the trace voltage and current of the semiconductor epitaxial structure 13 under forward bias and reverse bias. characteristic.

並在該齊納二極體85存在下,亦可量測該發光二極體晶粒10的小電流順向Vf,以及該發光二極體晶粒10之逆向偏壓下的漏電流是否有異常增大,而逆偏漏電流增大的成因為半導體缺陷擴大,可為封裝製程中機械應力與熱應力或產品加嚴測試進入高溫爐老化或施加ESD測試等等。And in the presence of the Zener diode 85, the small current forward Vf of the light emitting diode die 10 can also be measured, and whether the leakage current of the light emitting diode die 10 under the reverse bias voltage is there. Abnormal increase, and the reason for the increase of reverse bias leakage current is the expansion of semiconductor defects, which can be mechanical stress and thermal stress in the packaging process or product tightening test, entering high temperature furnace aging or applying ESD test, etc.

而在測試完畢之後,該電性測試第二位置接點52、該電性測試第三位置接點53與該電性測試第四位置接點54之間可以透過一導電金屬90而電性連接在一起。該導電金屬90可以使用打線製程的金導線,或是以半導體薄膜製成來形成。After the test is completed, the electrical test second position contact 52 , the electrical test third position contact 53 and the electrical test fourth position contact 54 can be electrically connected through a conductive metal 90 . together. The conductive metal 90 can be formed by using gold wires in a wire bonding process, or by using semiconductor thin films.

另為了保護該封裝載板30上的元件,在測試完畢之後,如圖3所示,可以更包含一封裝材91,該封裝材91覆蓋封裝該封裝載板30的該上側平面301,因而可保護該封裝載板30上的元件。In addition, in order to protect the components on the package carrier board 30, after the test is completed, as shown in FIG. 3, a package material 91 may be further included. Components on the package carrier 30 are protected.

或者,如圖10所示,可以更包含一第一封裝材92與一第二封裝材93,其為先藉由該第一封裝材92覆蓋該發光二極體晶粒10、該晶粒第一打線金屬61、該晶粒第二打線金屬62、該齊納二極體85、該主元件第一電極41、該主元件第二電極42、該主元件第三電極43、該副元件第一電極81與該副元件第二電極84。Alternatively, as shown in FIG. 10 , a first encapsulation material 92 and a second encapsulation material 93 may be further included. The first encapsulation material 92 covers the light-emitting diode die 10 and the die is first A wire bonding metal 61 , the die second wire bonding metal 62 , the Zener diode 85 , the main element first electrode 41 , the main element second electrode 42 , the main element third electrode 43 , the secondary element first electrode 43 An electrode 81 and a second electrode 84 of the secondary element.

再利用尚未封裝的該電性測試第一位置接點51、該電性測試第二位置接點52、該電性測試第三位置接點53與該電性測試第四位置接點54進行測試,可以解決習知於封裝製程時,該晶粒第一打線金屬61、該晶粒第二打線金屬62會被該封裝材91(如圖3所示)或該第一封裝材92(如圖10所示)拉扯而間接拉扯,可能破壞該發光二極體晶粒10,使其形成微裂痕或薄膜剝離,造成失效或不穩定的問題。Then use the electrical testing first position contact 51 , the electrical testing second position contact 52 , the electrical testing third position contact 53 and the electrical testing fourth position contact 54 that have not yet been packaged for testing , which can solve the problem that during the conventional packaging process, the first wire bonding metal 61 of the die and the second wire bonding metal 62 of the die will be covered by the packaging material 91 (as shown in FIG. 3 ) or the first packaging material 92 (as shown in FIG. 3 ). 10) pulling and indirect pulling may damage the light-emitting diode die 10, causing it to form micro-cracks or film peeling, resulting in failure or instability.

而在測試完畢之後,同樣的,該電性測試第二位置接點52、該電性測試第三位置接點53與該電性測試第四位置接點54之間可以透過該導電金屬90而電性連接在一起。最後讓該第二封裝材93覆蓋該導電金屬90、該電性測試第一位置接點51、該電性測試第二位置接點52、該電性測試第三位置接點53與該電性測試第四位置接點54,而完成整體的封裝製程。After the test is completed, similarly, the conductive metal 90 can pass through the conductive metal 90 between the electrical test second position contact 52 , the electrical test third position contact 53 and the electrical test fourth position contact 54 . electrically connected together. Finally, let the second package material 93 cover the conductive metal 90 , the electrical test first position contact 51 , the electrical test second position contact 52 , the electrical test third position contact 53 and the electrical test The fourth position contact 54 is tested to complete the overall packaging process.

另,若元件失效,可以單獨拆卸該第二封裝材93與拆除導電金屬90或使其斷路,其不會傷害該發光二極體晶粒10,因而可重新檢測,查出元件失效的真因。In addition, if the element fails, the second encapsulation material 93 and the conductive metal 90 can be disassembled separately or disconnected, which will not damage the light-emitting diode die 10, so it can be re-tested to find out the real cause of the element failure. .

請參閱圖11所示,為本發明第二實施例封裝載板俯視示意圖。其與圖7相較之下,更設置該電性測試第四位置接點54、該副元件第一電極81、該副元件第二電極84與該齊納二極體85,其中該齊納二極體85電性連接該副元件第一電極81與該副元件第二電極84,該副元件第一電極81與該主元件第一電極41為同一個該打線端點34A構成,另一個打線端點34B為主元件第二電極42,該副元件第二電極84則為由另一個打線端點34C構成,且該副元件第二電極84與該電性測試第四位置接點54為透過該金屬導電層306電性連接。Please refer to FIG. 11 , which is a schematic top view of the package carrier according to the second embodiment of the present invention. Compared with FIG. 7 , the fourth position contact 54 for electrical testing, the first electrode 81 of the sub-element, the second electrode 84 of the sub-element and the Zener diode 85 are further provided, wherein the Zener The diode 85 is electrically connected to the first electrode 81 of the auxiliary element and the second electrode 84 of the auxiliary element. The first electrode 81 of the auxiliary element and the first electrode 41 of the main element are formed by the same bonding terminal 34A, and the other The wire bonding terminal 34B is the main component second electrode 42, the secondary component second electrode 84 is formed by another wire bonding terminal 34C, and the secondary component second electrode 84 and the electrical test fourth position contact 54 are It is electrically connected through the metal conductive layer 306 .

如上所述,本發明的特點至少包含:As mentioned above, the features of the present invention include at least:

1.該P型分流檢測電極位於該半導體磊晶結構與該晶粒導電基座結構之介面處的該介面橫向延伸結構上,只要電性測試第二位置接點連結該P型分流檢測電極,即可以量測該半導體磊晶結構與該晶粒導電基座結構之分別的電性特性,以達到精確之半導體元件特性測試,進一步提升信賴度。1. The P-type shunt detection electrode is located on the laterally extending structure of the interface at the interface of the semiconductor epitaxial structure and the die conductive base structure, as long as the electrical test second position contact is connected to the P-type shunt detection electrode, That is, the respective electrical properties of the semiconductor epitaxial structure and the die conductive base structure can be measured, so as to achieve accurate semiconductor device characteristic testing and further improve reliability.

2.該電性測試第一位置接點、該電性測試第二位置接點、該電性測試第三位置接點集中設置於該封裝載板的該上側平面,可方便探針由上向下接觸量測,較為方便與準確,且於測試後,多測試點之端點連結簡單穩定,不會影響LED元件的特性。2. The first position contact point of the electrical test, the second position contact point of the electrical test, and the third position contact point of the electrical test are centrally arranged on the upper plane of the package carrier board, which can facilitate the probe from top to bottom The lower contact measurement is more convenient and accurate, and after the test, the endpoints of the multiple test points are connected simply and stably, which will not affect the characteristics of the LED components.

3.於實施例2中,利用增加該電性測試第四位置接點,可在該齊納二極體存在下測得該發光二極體晶粒於逆向偏壓下之電特性,亦可在施加高溫老化與ESD測試後判斷是否有逆偏漏電流,有助於該發光二極體晶粒10的信賴度提升。3. In Example 2, by adding a fourth position contact for the electrical property test, the electrical properties of the light-emitting diode die under reverse bias can be measured in the presence of the Zener diode, or After applying high temperature aging and ESD test, it is determined whether there is reverse bias leakage current, which helps to improve the reliability of the light emitting diode die 10 .

4.於實施例2中,可以測試該齊納二極體的功能是否正常,避免因為該齊納二極體失效而導致整體元件之失效。4. In Embodiment 2, it is possible to test whether the function of the Zener diode is normal, so as to avoid the failure of the whole device due to the failure of the Zener diode.

習知 1:垂直式LED晶粒 1A:半導體磊晶結構 1B:介面結構 1C:晶粒導電基座結構 1C1:替代基板黏合層 2:P電極 3:封裝載板 4:固晶導電底座 4A:載板固晶黏合層 5:N電極 6:金導線 7:打線端點 8:導通金屬 9A:陽極 9B:陰極 本發明 10:發光二極體晶粒 11:晶粒導電基座結構 11A:高導熱替代基板 11B:替代基板黏合層 11C:結構金屬層 12:介面橫向延伸結構 12A:高導電金屬層 12B:歐姆接觸層 12B1:歐姆接觸金屬 12B2:透明材料 12C:高濃度P型半導體導電層 13:半導體磊晶結構 13A:P型半導體 13B:活性層 13C:N型半導體 14:N型電極 15:P型分流檢測電極 16:P型主要電極 30:封裝載板 301:上側平面 302:下側平面 303、304、305、306:金屬導電層 311:陰極 313:陽極 315:增高層 33:固晶底座 34A、34B、34C:打線端點 41:主元件第一電極 42:主元件第二電極 43:主元件第三電極 431:載板固晶黏合層 51:電性測試第一位置接點 52:電性測試第二位置接點 53:電性測試第三位置接點 54:電性測試第四位置接點 61:晶粒第一打線金屬 62:晶粒第二打線金屬 71:載板金屬第一導通金屬 73:載板金屬第二導通金屬 81:副元件第一電極 84:副元件第二電極 85:齊納二極體 85A、85B:單向齊納二極體 90:導電金屬 91:封裝材 92:第一封裝材 93:第二封裝材acquaintance 1: Vertical LED Die 1A: Semiconductor epitaxial structure 1B: Interface Structure 1C: Die conductive base structure 1C1: Alternative Substrate Bonding Layer 2: P electrode 3: Package carrier board 4: Solid crystal conductive base 4A: carrier board die bonding layer 5:N electrode 6: Gold wire 7: Line endpoints 8: Conductive metal 9A: Anode 9B: Cathode this invention 10: Light Emitting Diode Die 11: Die conductive base structure 11A: High thermal conductivity alternative substrate 11B: Alternative Substrate Adhesive Layer 11C: Structural metal layer 12: Interface horizontal extension structure 12A: Highly conductive metal layer 12B: Ohmic Contact Layer 12B1: Ohmic Contact Metal 12B2: Transparent Materials 12C: high concentration P-type semiconductor conductive layer 13: Semiconductor epitaxial structure 13A: P-type semiconductor 13B: Active layer 13C: N-type semiconductor 14: N-type electrode 15: P-type shunt detection electrode 16: P-type main electrode 30: Package carrier board 301: Upper side plane 302: Lower side plane 303, 304, 305, 306: metal conductive layer 311: Cathode 313: Anode 315: Increase the floor 33: Solid crystal base 34A, 34B, 34C: wire end points 41: The first electrode of the main element 42: The second electrode of the main element 43: The third electrode of the main element 431: carrier board die-bonding adhesive layer 51: Electrical test first position contact 52: Electrical test second position contact 53: Electrical test third position contact 54: Electrical test fourth position contact 61: Die first wire bonding metal 62: Die second wire bonding metal 71: The first conductive metal of the carrier metal 73: carrier metal second conductive metal 81: Sub-element first electrode 84: Secondary element second electrode 85: Zener Diode 85A, 85B: Unidirectional Zener Diode 90: Conductive metal 91: Packaging material 92: The first packaging material 93: Second packaging material

圖1,為習知發光二極體封裝結構斷面示意圖。 圖2,為本發明第一實施例的封裝結構電路示意圖。 圖3,為本發明第一實施例的封裝結構斷面示意圖。 圖4,為本發明一實施例的晶粒結構斷面示意圖。 圖5,為本發明另一實施例的晶粒結構斷面示意圖。 圖6,為本發明另一實施例的晶粒結構斷面示意圖。 圖7,為本發明第一實施例封裝載板俯視示意圖。 圖8,為本發明第一實施例封裝載板仰視示意圖。 圖9,為本發明第二實施例的封裝結構電路示意圖。 圖10,為本發明第二實施例的封裝結構斷面示意圖。 圖11,為本發明第二實施例封裝載板俯視示意圖。 FIG. 1 is a schematic cross-sectional view of a conventional light-emitting diode package structure. FIG. 2 is a schematic diagram of a package structure circuit according to the first embodiment of the present invention. FIG. 3 is a schematic cross-sectional view of the package structure according to the first embodiment of the present invention. FIG. 4 is a schematic cross-sectional view of a grain structure according to an embodiment of the present invention. FIG. 5 is a schematic cross-sectional view of a crystal grain structure according to another embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of a crystal grain structure according to another embodiment of the present invention. FIG. 7 is a schematic top view of a package carrier according to the first embodiment of the present invention. FIG. 8 is a schematic bottom view of the package carrier board according to the first embodiment of the present invention. FIG. 9 is a schematic diagram of a package structure circuit according to a second embodiment of the present invention. FIG. 10 is a schematic cross-sectional view of the package structure according to the second embodiment of the present invention. FIG. 11 is a schematic top view of a package carrier board according to the second embodiment of the present invention.

10:發光二極體晶粒 10: Light Emitting Diode Die

11:晶粒導電基座結構 11: Die conductive base structure

12:介面橫向延伸結構 12: Interface horizontal extension structure

13:半導體磊晶結構 13: Semiconductor epitaxial structure

14:N型電極 14: N-type electrode

15:P型分流檢測電極 15: P-type shunt detection electrode

16:P型主要電極 16: P-type main electrode

30:封裝載板 30: Package carrier board

301:上側平面 301: Upper side plane

302:下側平面 302: Lower side plane

303、304、305:金屬導電層 303, 304, 305: Metal conductive layer

311:陰極 311: Cathode

313:陽極 313: Anode

41:主元件第一電極 41: The first electrode of the main element

42:主元件第二電極 42: The second electrode of the main element

43:主元件第三電極 43: The third electrode of the main element

431:載板固晶黏合層 431: carrier board die-bonding adhesive layer

51:電性測試第一位置接點 51: Electrical test first position contact

52:電性測試第二位置接點 52: Electrical test second position contact

53:電性測試第三位置接點 53: Electrical test third position contact

61:晶粒第一打線金屬 61: Die first wire bonding metal

62:晶粒第二打線金屬 62: Die second wire bonding metal

71:載板金屬第一導通金屬 71: The first conductive metal of the carrier metal

73:載板金屬第二導通金屬 73: carrier metal second conductive metal

90:導電金屬 90: Conductive metal

91:封裝材 91: Packaging material

Claims (15)

一種具有電性檢測位置之垂直式發光二極體晶粒封裝體,其包含: 一發光二極體晶粒,該發光二極體晶粒具有一晶粒導電基座結構、一介面橫向延伸結構、一半導體磊晶結構、一N型電極與一P型分流檢測電極,其中該晶粒導電基座結構具有位於下方側的一P型主要電極,該晶粒導電基座結構遠離該P型主要電極的一側設置該介面橫向延伸結構,於該介面橫向延伸結構的上方平面分別設置該半導體磊晶結構與該P型分流檢測電極,該半導體磊晶結構與該晶粒導電基座結構之間為藉由該介面橫向延伸結構達到歐姆接觸,該半導體磊晶結構遠離該晶粒導電基座結構的一側設置該N型電極;該晶粒導電基座結構更具有一結構金屬層、一替代基板黏合層與一高導熱替代基板,該結構金屬層位於該介面橫向延伸結構之下方,該結構金屬層之下方以該替代基板黏合層黏合該高導熱替代基板,該高導熱替代基板的下方設置該P型主要電極; 一封裝載板,該封裝載板具有位於兩側的一上側平面與一下側平面,該下側平面設置一陽極與一陰極,而該上側平面設置一主元件第一電極、一主元件第二電極、一主元件第三電極、一電性測試第一位置接點、一電性測試第二位置接點與一電性測試第三位置接點,其中該N型電極與該主元件第一電極為以一晶粒第一打線金屬電性連接,該P型分流檢測電極與該主元件第二電極為以一晶粒第二打線金屬電性連接,該P型主要電極則透過一載板固晶黏合層直接黏結該主元件第三電極而電性連接,而該電性測試第一位置接點電性連接該主元件第一電極與該陰極,該電性測試第二位置接點電性連接該主元件第二電極,該電性測試第三位置接點電性連接該主元件第三電極與該陽極。 A vertical light-emitting diode die package with an electrical detection position, comprising: a light-emitting diode die, the light-emitting diode die has a die conductive base structure, an interface lateral extension structure, a semiconductor epitaxial structure, an N-type electrode and a P-type shunt detection electrode, wherein the The die conductive base structure has a P-type main electrode located on the lower side, the side of the die conductive base structure away from the P-type main electrode is provided with the interface laterally extending structure, and the upper plane of the interface laterally extending structure is respectively The semiconductor epitaxial structure and the P-type shunt detection electrode are arranged, the semiconductor epitaxial structure and the die conductive base structure achieve ohmic contact through the interface lateral extension structure, and the semiconductor epitaxial structure is far away from the die The N-type electrode is arranged on one side of the conductive base structure; the die conductive base structure further has a structural metal layer, a substitute substrate adhesive layer and a high thermal conductivity substitute substrate, and the structural metal layer is located between the laterally extending structure of the interface Below, the high thermal conductivity substitute substrate is bonded with the substitute substrate adhesive layer below the structural metal layer, and the P-type main electrode is arranged below the high thermal conductivity substitute substrate; A package carrier, the package carrier has an upper side plane and a lower side plane located on both sides, an anode and a cathode are arranged on the lower side plane, and a main element first electrode and a main element second electrode are arranged on the upper side plane. electrode, a main element third electrode, an electrical test first position contact, an electrical test second position contact and an electrical test third position contact, wherein the N-type electrode and the main element first The electrode is electrically connected with a first wire bonding metal of a die, the P-type shunt detection electrode and the second electrode of the main element are electrically connected with a second wire bonding metal of a die, and the P-type main electrode is passed through a carrier board The die-bonding adhesive layer directly bonds the third electrode of the main element to be electrically connected, and the electrical test first position contact is electrically connected to the main element first electrode and the cathode, and the electrical test second position contact is electrically connected. The second electrode of the main element is electrically connected, and the electrical test third position contact is electrically connected to the third electrode of the main element and the anode. 如請求項1所述的垂直式發光二極體晶粒封裝體,其中該封裝載板更包含一副元件第一電極、一副元件第二電極與一電性測試第四位置接點,其中該副元件第一電極電性連接該電性測試第一位置接點,該副元件第二電極電性連接該電性測試第四位置接點,且該副元件第一電極與該副元件第二電極之間電性連接一齊納二極體。The vertical light-emitting diode die package as claimed in claim 1, wherein the package carrier further comprises a first electrode of a sub-element, a second electrode of a sub-element, and a fourth position contact for electrical testing, wherein The first electrode of the sub-element is electrically connected to the first position contact of the electrical test, the second electrode of the sub-element is electrically connected to the fourth position of the electrical test, and the first electrode of the sub-element is connected to the first position of the sub-element A Zener diode is electrically connected between the two electrodes. 如請求項2所述的垂直式發光二極體晶粒封裝體,其中該齊納二極體為單向二極體,且該齊納二極體以相反極性並聯該發光二極體晶粒。The vertical light-emitting diode die package as claimed in claim 2, wherein the Zener diode is a unidirectional diode, and the Zener diode is connected in parallel with the light-emitting diode die with opposite polarities . 如請求項2所述的垂直式發光二極體晶粒封裝體,其中該電性測試第二位置接點、該電性測試第三位置接點與該電性測試第四位置接點之間透過一導電金屬而電性連接在一起。The vertical light-emitting diode die package as claimed in claim 2, wherein the electrical test second position contact, the electrical test third position contact and the electrical test fourth position contact They are electrically connected together through a conductive metal. 如請求項4所述的垂直式發光二極體晶粒封裝體,其中更包含一封裝材,該封裝材覆蓋封裝該封裝載板的該上側平面。The vertical light-emitting diode die package as claimed in claim 4, further comprising an encapsulation material covering the upper plane for encapsulating the package carrier. 如請求項2所述的垂直式發光二極體晶粒封裝體,其中更包含一第一封裝材,該第一封裝材覆蓋該發光二極體晶粒、該晶粒第一打線金屬、該晶粒第二打線金屬、該齊納二極體、該主元件第一電極、該主元件第二電極、該主元件第三電極、該副元件第一電極與該副元件第二電極。The vertical light-emitting diode die package according to claim 2, further comprising a first packaging material, the first packaging material covering the light-emitting diode die, the die first wire bonding metal, the die The second wire bonding metal of the die, the Zener diode, the first electrode of the main element, the second electrode of the main element, the third electrode of the main element, the first electrode of the auxiliary element and the second electrode of the auxiliary element. 如請求項6所述的垂直式發光二極體晶粒封裝體,其中該電性測試第二位置接點、該電性測試第三位置接點與該電性測試第四位置接點之間透過一導電金屬電性連接。The vertical light-emitting diode die package as claimed in claim 6, wherein the electrical test second position contact, the electrical test third position contact and the electrical test fourth position contact It is electrically connected through a conductive metal. 如請求項7所述的垂直式發光二極體晶粒封裝體,其中更包含一第二封裝材,該第二封裝材覆蓋該導電金屬、該電性測試第一位置接點、該電性測試第二位置接點、該電性測試第三位置接點與該電性測試第四位置接點。The vertical light-emitting diode die package as claimed in claim 7, further comprising a second packaging material, the second packaging material covering the conductive metal, the electrical property testing first position contact, the electrical property The second position contact for testing, the third position contact for electrical testing and the fourth position contact for electrical testing are tested. 如請求項1所述的垂直式發光二極體晶粒封裝體,其中該主元件第一電極與該陰極透過一貫穿該封裝載板的載板金屬第一導通金屬而電性連接,該主元件第三電極與該陽極透過一貫穿該封裝載板的載板金屬第二導通金屬而電性連接。The vertical light-emitting diode die package as claimed in claim 1, wherein the first electrode of the main element and the cathode are electrically connected through a carrier metal first conducting metal penetrating the package carrier, and the main element is electrically connected to the cathode. The third electrode of the element and the anode are electrically connected through a carrier metal second conductive metal penetrating the package carrier. 如請求項1所述的垂直式發光二極體晶粒封裝體,其中該半導體磊晶結構包含依序堆疊的一P型半導體、一活性層與一N型半導體,其中該N型電極位於該N型半導體上,且該P型半導體與該P型分流檢測電極分別位於該介面橫向延伸結構的不同位置上。The vertical light-emitting diode die package as claimed in claim 1, wherein the semiconductor epitaxial structure comprises a P-type semiconductor, an active layer and an N-type semiconductor sequentially stacked, wherein the N-type electrode is located on the On the N-type semiconductor, the P-type semiconductor and the P-type shunt detection electrode are respectively located at different positions of the laterally extending structure of the interface. 如請求項10所述的垂直式發光二極體晶粒封裝體,其中該介面橫向延伸結構包含依序堆疊的一高導電金屬層、一歐姆接觸層與一高濃度P型半導體導電層,並該P型分流檢測電極位於該介面橫向延伸結構的邊緣外側。The vertical light-emitting diode die package as claimed in claim 10, wherein the interface laterally extending structure comprises a high-conductivity metal layer, an ohmic contact layer and a high-concentration P-type semiconductor conductive layer stacked in sequence, and The P-type shunt detection electrode is located outside the edge of the laterally extending structure of the interface. 如請求項11所述的垂直式發光二極體晶粒封裝體,其中該高導電金屬層位於該結構金屬層之上方,該P型半導體與該P型分流檢測電極分別位於該高濃度P型半導體導電層上。The vertical light-emitting diode die package as claimed in claim 11, wherein the high-conductivity metal layer is located above the structural metal layer, and the P-type semiconductor and the P-type shunt detection electrode are respectively located on the high-concentration P-type on the semiconductor conductive layer. 如請求項11所述的垂直式發光二極體晶粒封裝體,其中該高導電金屬層位於該結構金屬層之上方,該P型半導體位於該高濃度P型半導體導電層上,而該P型分流檢測電極位於該歐姆接觸層上。The vertical light emitting diode die package as claimed in claim 11, wherein the highly conductive metal layer is located above the structural metal layer, the P-type semiconductor is located on the high-concentration P-type semiconductor conductive layer, and the P A type shunt detection electrode is located on the ohmic contact layer. 如請求項11所述的垂直式發光二極體晶粒封裝體,其中該高導電金屬層位於該結構金屬層之上方,該P型半導體位於該高濃度P型半導體導電層上,而該P型分流檢測電極位於該高導電金屬層上。The vertical light emitting diode die package as claimed in claim 11, wherein the highly conductive metal layer is located above the structural metal layer, the P-type semiconductor is located on the high-concentration P-type semiconductor conductive layer, and the P Type shunt detection electrodes are located on the highly conductive metal layer. 如請求項11所述的垂直式發光二極體晶粒封裝體,其中該歐姆接觸層可為歐姆接觸金屬搭配透明材料,並該歐姆接觸金屬為複數柱狀結構。The vertical light-emitting diode die package as claimed in claim 11, wherein the ohmic contact layer can be an ohmic contact metal and a transparent material, and the ohmic contact metal has a plurality of columnar structures.
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