JP7197645B1 - Light emitting diode package with multiple test terminals and parallel connection components - Google Patents

Abstract

A light-emitting diode package in which the electrical characteristics of each light-emitting diode chip and parallel-connected sub-components can be individually measured even after they are die-bonded. The present invention includes a packaging carrier (20) and electrical test first, second and third position contacts (31, 32, 33) on the packaging carrier, the packaging carrier having an upper plane and a lower bottom plane, the upper component plane being provided with main component first and second electrodes (41, 42) and secondary component first and second electrodes (43, 44); A position contact 31 is connected to a main part first electrode 41 and a sub-part first electrode 43, an electrical test second position contact 32 is connected to a sub-part second electrode 44, and an electrical test third position contact 33 is connected to the main part. It is connected to the component second electrode. Thus, the electrical characteristics of each of the main component light emitting diode chip and parallel-connected subcomponents can be individually measured at the electrical test first, second and third position contacts. [Selection drawing] Fig. 6

Description

TECHNICAL FIELD The present invention relates to a light emitting diode package structure, and more particularly to a light emitting diode package with multiple test terminals and parallel connection components.

A light emitting diode (LED) is a light source that obtains high brightness by combining electrons and holes in a semiconductor. Related products include high-intensity sterilization (ultraviolet light), automobile headlights and taillights (blue light, yellow light, red light), light sources for projectors (blue light, green light, red light), danger detection by infrared light (infrared light). can be used for High-power LED components with excellent performance require not only high brightness and high illumination, but also high reliability. For example, in a car headlight module, safety driving at night is affected if the LEDs become inoperative. In the case of automotive LEDs, even as little as 1 ppm deactivation is in need of improvement by automotive industry standards.

According to the LED chip structure, LEDs are divided into various types. In addition to low-cost horizontal chips, flip-chip and vertical high-power LED chips with complex processes have been developed in the field of high-power large-size chips. For example, Patent Document 1 discloses a flip-chip (FLIP-CHIP) type LED chip structure. Patent Document 2 discloses a vertical LED chip structure. Patent Document 3 discloses a technical proposal using a plurality of contacts using a vertical LED, in which an N electrode is used as a lower electrode, and a plurality of contacts with insulating sidewalls are composed of a P-type semiconductor layer and a quantum well layer. The perpendicular passage into the N-type semiconductor layer distributes the operating current evenly in the N-type semiconductor layer and provides a side edge to the P-electrode for use in wire bonding during the packaging process.

In the past, the failure of LEDs was mainly caused by the leakage current generated by wafer defects. Process stresses pulling the semiconductor layers, or thermal stresses in high temperature processes or packaging adhesives pulling microcracks or film delamination to create higher leakage currents. , the package becomes inoperable or unreliable.

For example, FIG. 1 is a schematic circuit diagram of a conventional package. As shown in FIG. 2, which is a schematic cross-sectional view of a conventional light emitting diode package structure, when the LED chip 1 is SMD packaged, the P electrode 2 is attached to the die bonding base of the packaging carrier 3 by the carrier die bonding adhesive layer 4A. 4, the gold wire 6 of the N electrode 5 is electrically connected to the wire bonding terminal 7 by wire bonding, and the die bonding base 4 is an anode located on the other side of the packaging carrier 3 via the conductive metal 8. The wire bonding terminal 7 is electrically connected to the cathode 9B (Cathode) of the cathode 9A (Anode). A Zener diode 1A (Zener diode) may be connected in parallel to the LED chip 1 in order to prevent the components from being damaged by strong static electricity.

In order to meet the requirements of high reliability, the anode 9A and cathode 9B of the LED chip 1 after packaging can be detected by test equipment as test contacts, which can meet the high standards of automotive LEDs. .

However, when detecting the LED chip 1, if the malfunction of the component is serious, it can be known from the forward voltage Vf and the luminance, but if there is a fine crack in the semiconductor, it is necessary to know the reverse bias characteristic. (eg, Ir). When the Zener diode 1A is connected in parallel to the LED chip 1, the electrical characteristics (for example, the leakage current Ir) under the reverse bias voltage cannot be measured, and the optical or electrical characteristics under the forward bias voltage operation cannot be measured. Reliability and detectability of the LED chip 1 may be compromised due to the need to measure physical properties (eg, brightness, wavelength, Vf).

In addition to the parallel-connected Zener diode 1A, if there are other parallel-connected subcomponents in the circuit, they may interfere with the measurement of the electrical characteristics of the LED chip 1. FIG. If the leakage current of the LED chip 1 under reverse bias operation cannot be accurately measured, it is considered that the reliability of the LED chip 1 after the packaging process and the evaluation by the deterioration test are greatly hindered.

US Registered Patent No. US8183579B2 U.S. Registered Patent No. US8546831 U.S. Registered Patent No. US8319250

SUMMARY OF THE INVENTION The main object of the present invention is to disclose a light emitting diode package having a plurality of test terminals and parallel-connected parts, wherein the light-emitting diode chip as the main part and the parallel-connected sub-parts are the die. After bonding, the electrical characteristics of each of the light emitting diode chip, which is the main component, and the parallel-connected subcomponents can be measured.

The present invention is a light-emitting diode package with a plurality of test terminals and parallel-connected parts, wherein the light-emitting diode chip as the main part and the parallel-connected sub-parts are die-bonded, the packaging carrier, the electrical test first position contact, An electrical test second position contact and an electrical test third position contact are included. The packaging carrier has an upper component plane and a lower SMD electrode plane located on both sides, and the upper component plane includes a main component first electrode, a main component second electrode and a subcomponent first electrode. , and a sub-component second electrode, the main component first electrode and the main component second electrode are electrically connected to the main component light emitting diode chip, and the sub-component first electrode and the sub-component second electrode are electrically connected to the main component light emitting diode chip. The two electrodes are electrically connected to the parallel-connected subcomponents, and depending on the embodiment, the electrically connected may be die bonding, wire bonding, etc., as long as they are electrically connected. There is no problem, and the main part first electrode and the sub-part first electrode are electrically connected. The electrical test first location contact is provided on the packaging carrier and electrically connected to the main component first electrode and the subcomponent first electrode, and the electrical test second location contact is provided on the packaging carrier. and electrically connected to the sub-component second electrode, and the electrical test third position contact is provided on the packaging carrier and electrically connected to the main component second electrode.

In this manner, the light emitting diode chip as the main component is die-bonded by the main component first electrode and the main component second electrode, and the parallel connection sub-component is die-bonded by the sub-component first electrode and the sub-component second electrode. In the invention, after the light emitting diode chip as the main component and the sub-component are connected to the important structure by the die bonding process, the light emitting diode chip as the main component and the parallel connection can be electrically tested by the first, second and third position contacts. It is possible to measure the electrical characteristics of each of the connecting sub-parts, and finally connect the electrical test second and third position contacts, the connection process is simple and safe, so the main part is light emission. Diode chip reliability is preserved.

FIG. 1 is a schematic circuit diagram of a conventional package. FIG. 2 is a schematic cross-sectional view of a conventional light emitting diode package structure. FIG. 3 is a front structural schematic view of the packaging carrier according to the present invention. FIG. 4 is a structural schematic view of the back side of the packaging carrier according to the present invention. FIG. 5 is a schematic circuit diagram of a package structure according to the present invention. FIG. 6 is a front structural schematic diagram of a packaging carrier according to an embodiment of the present invention. FIG. 7 is a schematic cross-sectional view of a package structure according to one embodiment of the present invention. FIG. 8 is a schematic cross-sectional view of another package structure according to one embodiment of the present invention. FIG. 9 is a schematic diagram 1 of circuit connection according to an embodiment of the present invention. FIG. 10 is a second schematic diagram of circuit connection according to an embodiment of the present invention. FIG. 11 is a structural schematic diagram of a packaging carrier according to another embodiment of the present invention. FIG. 12 is a structural schematic diagram of a packaging carrier according to another embodiment of the present invention. FIG. 13 is a circuit schematic diagram of a package structure according to a further embodiment of the present invention. FIG. 14 is a structural schematic diagram of a packaging carrier according to another embodiment of the present invention.

For a better understanding of the features, objects and advantages of the present invention, preferred embodiments will be described with reference to the drawings.
As shown in FIGS. 3, 4 and 5, the present invention is a light-emitting diode package having a plurality of test terminals and parallel-connected parts, in which a light-emitting diode chip 10 as a main part and a parallel-connected sub-part 11 are die-bonded. , a packaging carrier 20 , an electrical test first position contact 31 , an electrical test second position contact 32 and an electrical test third position contact 33 .

As shown in FIGS. 6 and 7, the packaging carrier 20 has an upper component plane 21 located on both sides and a lower bottom SMD electrode plane 22. On the upper component plane 21, a main component first electrode 41; A main component second electrode 42, a subcomponent first electrode 43, and a subcomponent second electrode 44 are provided. The sub-component first electrode 43 and the sub-component second electrode 44 are used to die-bond the parallel-connected sub-component 11, and the main component first electrode 41 and the sub-component first electrode 43 are electrically connected.

Also, an electrical test first position contact 31 is provided on the packaging carrier 20 and electrically connected to the main component first electrode 41 and the subcomponent first electrode 43 . An electrical test second position contact 32 is provided on the packaging carrier 20 and electrically connected to the subcomponent second electrode 44 . An electrical test third position contact 33 is provided on the packaging carrier 20 and electrically connected to the main part second electrode 42 .

In terms of actual structure, the packaging carrier 20 may be selected from a ceramic substrate (aluminum nitride, aluminum oxide, silicon carbide), a copper substrate, a BT (bismaleimide triazine) board, etc., and the packaging carrier 20 may be a single-layer board. or a multi-layer plate. An electrical test first position contact 31 , an electrical test second position contact 32 and an electrical test third position contact 33 are provided on the upper component plane 21 . A carrier first external electrode 51 , a carrier second external electrode 52 , and a carrier relay electrode 53 are provided on the lower bottom SMD electrode plane 22 . And the first external electrode 51 of the carrier is electrically connected to the main part first electrode 41 , the sub-part first electrode 43 and the electrical test first position contact 31 through the first electrode conduction hole 61 . The second external electrode 52 of the carrier is electrically connected to the main part second electrode 42 and the electrical test third position contact 33 through the second electrode conducting hole 62 . The relay electrode 53 of the carrier is electrically connected to the subcomponent second electrode 44 and the electrical test second position contact 32 through the relay electrode conduction hole 63 of the carrier. In addition, a raising layer 54 may be provided on the lower bottom SMD electrode plane 22 (see FIG. 4), and the height of the raising layer 54 is the first outer electrode 51 of the carrier, the second outer electrode 52 of the carrier, and the height of the second outer electrode 52 of the carrier. It is equal to the height of the carrier relay electrode 53, which satisfies the requirements of subsequent processes.

Also, the electrical test first position contact 31, the main part first electrode 41 and the sub-part first electrode 43 may be electrically connected by a metal conductive layer 64 (see FIG. 7) built in the packaging carrier 20. good. The electrical test second position contact 32 and the subcomponent second electrode 44 may also be electrically connected with a metal conductive layer 64 embedded in the packaging carrier 20 . The electrical test third position contact 33 is electrically connected to the main part second electrode 42 by means of the metal conductive layer 64 (see FIG. 7) embedded in the packaging carrier 20. It may be And the metal conductive layer 64 may be formed on the upper component plane 21 of the packaging carrier 20 (see FIG. 6).

In the present invention, the light-emitting diode chip 10, which is the main component, is any one selected from horizontal light-emitting diodes, flip-chip light-emitting diodes, vertical light-emitting diodes, and vertical light-emitting diodes with multiple contacts (for example, Patent Document 3). A single LED chip or multiple LED chips connected in series can be used as the LED chip 10, which is the main component, to increase the brightness of the emitted light. A cross section of the package structure according to the present invention is shown in FIG. The main component light emitting diode chip 10 is a vertical light emitting diode, and the main component light emitting diode chip 10 includes an upper N-type electrode 101 and a lower P-type electrode 102. The P-type electrode 102 is The carrier die bonding adhesive layer 103 is die-bonded to the main component second electrode 42 , and the N-type electrode 101 is connected to the main component first electrode 41 by wire bonding using a gold wire 65 . The parallel-connected subcomponent 11 is one selected from a Zener diode, a capacitor, and a light-emitting diode chip, and can realize various functions. The forward voltage (Vf) of the connection subcomponent 11 should be close to the forward voltage (Vf) of the light emitting diode chip 10, which is the main component. If the parallel-connected sub-component 11 is a Zener diode, you may choose Bi-directional Zener Diodes, or you may choose Uni-directional Zener Diodes. Zener Diode), the parallel-connected sub-component 11 should be connected in parallel with the main component light-emitting diode chip 10 with the opposite polarity.

As shown in FIG. 5 , there are three test contacts in the circuit of the light emitting diode package structure, which are the electrical test first position contact 31 , the electrical test second position contact 32 and the electrical test third position contact 33 . When the electrical test first position contact 31 and the electrical test second position contact 32 are selected for testing, they can be used to test whether the parallel connection subcomponent 11 operates with normal electrical characteristics. . When the electrical test first position contact 31 and the electrical test third position contact 33 are selected for testing, when the parallel connection sub-component 11 exists, the light emitting diode chip 10 as the main component under a small current It is possible to measure the forward voltage Vf and the leakage current under the reverse bias voltage operation of the light emitting diode chip 10 which is the main component. , degradation in a high-temperature furnace, ESD testing, and the like.

After the test is completed, electrical test second location contact 32 and electrical test third location contact 33 are electrically connected via conductive metal 66 . The conductive metal 66 may use gold wire in a wire bonding process, or may be formed as a semiconductor film.

In order to protect the components on the packaging carrier 20, the present invention further applies a packaging material 70 to cover and package the upper component plane 21 of the packaging carrier 20, as shown in FIG. may include components on the packaging carrier 20, such as the main component light emitting diode chip 10, the electrical test first position contact 31, the electrical test second position contact 32, the electrical test third position contact 33. , the main part first electrode 41, the main part second electrode 42, the sub-part first electrode 43, the sub-part second electrode 44, etc. can be protected.

As shown in FIG. 8, in another embodiment, the present invention may further include a first packaging material 71 and a second packaging material 72, the first packaging material 71 being the main part of the light emitting diode chip 10; The parallel connection subcomponent 11, the main component first electrode 41, the main component second electrode 42, the subcomponent first electrode 43 and the subcomponent second electrode 44 are covered.

In addition, if a test is performed using the first electrical test position contact 31, the second electrical test position contact 32, and the third electrical test position contact 33, which are not packaged, the gold wire 65 is removed during the packaging process. When pulled by the packaging material, the light-emitting diode chip 10, which is the main component, is indirectly pulled and destroyed. It can solve the traditional problem of being unstable.

After the test is completed, electrical test second location contact 32 and electrical test third location contact 33 are electrically connected via conductive metal 66 . Finally, the second packaging material 72 covers the conductive metal 66, the first electrical test position contact 31, the second electrical test position contact 32 and the third electrical test position contact 33, and the whole packaging process is completed. complete. Also, if the main component, the light emitting diode chip 10, becomes inoperable, only the second packaging material 72 is removed and the connection lead 66 is removed or cut off. is avoided, and if detected again, the cause of the non-operation of the component can be easily and effectively determined.

In one embodiment, the electrical test first position contact 31, the electrical test second position contact 32 and the electrical test third position contact 33 are the lower bottom SMD electrode plane 22 of the packaging carrier 20, as shown in FIG. may be provided in As for the actual structure, the first external electrode 51 of the carrier is directly used as the first electrical test position contact 31, the relay electrode 53 of the carrier is used as the second electrical test position contact 32, and the second external electrode 52 of the carrier. may be the electrical test third position contact 33 . After the test is completed, the lower bottom SMD electrode plane 22 of the packaging carrier 20 covers the circuit board 80 , and the second external electrodes 52 of the carrier and the relay electrodes 53 of the carrier are soldered on the lower bottom SMD electrode plane 22 by solder paste 81 . electrically connected. Thus, a plurality of packaging carriers 20 may be arranged in parallel, and in this structure, the circuit board 80 is connected to the carrier first external electrodes 51 and the carrier second external electrodes 52 of the plurality of packaging carriers 20 respectively. It has a plurality of circuit board extension electrodes 82 that are electrically connected and can be used in subsequent processes.

As shown in FIG. 10, in one embodiment, the carrier first external electrode 51, the carrier second external electrode 52 and the carrier relay electrode 53 may extend to the circuit board upper plane 83 of the circuit board 80, Further, the second external electrode 52 of the carrier and the relay electrode 53 of the carrier are electrically connected via the conductive film 81A on the upper plane 83 of the circuit board.

In the above embodiment, a vertical light emitting diode is selected as the light emitting diode chip 10, which is the main component. Explain each.

As shown in FIG. 11, when a flip-chip type light emitting diode is selected as the main component light emitting diode chip 10A and a flip chip type light emitting diode is selected as the parallel connection sub-component 11A, the main component light emitting diode chip 10A is selected. , the parallel-connected subcomponents 11A may be die-bonded to the packaging carrier 20 in a flip-chip manner, respectively.

As shown in FIG. 12, when a vertical light emitting diode with a plurality of contacts is selected as the main component light emitting diode chip 10B and a capacitor is selected as the parallel connection subcomponent 11B, the main component light emitting diode chip 10B is die-bonded to the main component first electrode 41, and the P-type electrode 102 of the light-emitting diode chip, which is the main component, is connected to the gold wire 65 by wire bonding. may be electrically connected to the main part second electrode 42 by the . And as shown in FIG. 12, it only has a first electrode conduction hole 61 and a second electrode conduction hole 62, and the electrical test second position contact 32 and the electrical test third position contact 33 are conductive after testing. are electrically connected by a conductive metal 66 (wire bonding or metal film), so that the relay electrode conduction hole 63 of the carrier may be omitted.

As shown in FIG. 13, it is a circuit schematic diagram of a package structure according to a further embodiment of the present invention. In this embodiment, the light-emitting diode chip 10C, which is the main component, may be formed by connecting a plurality of light-emitting diode chips 10C1, 10C2, and 10C3 in series. In another embodiment, the main light emitting diode chip may be a plurality of light emitting diode chips connected in parallel. In this embodiment, for example, in FIG. 13, when the three light emitting diode chips 10C1, 10C2 and 10C3 connected in series operate at the same forward current as a single LED chip, the light emitting diode chips 10C1, 10C2 and The overall voltage (Vf) of 10C3 (the main light-emitting diode chip 10C) is three times that of a single LED chip, and its luminous efficiency is also three times that of a single LED chip. For this reason, a conventional automotive headlight package typically includes a plurality of LED chips connected in series in order to obtain more light output at a higher voltage.

In a circuit in which the light emitting diode chips 10C1, 10C2 and 10C3 are connected in series, if a part is damaged and a leakage current is generated, one of the light emitting diode chips 10C1, 10C2 and 10C3 in the series connection circuit A normal chip cannot detect the leakage current of a damaged chip. Therefore, electrical test position contacts 33B, 33C may be added between the different light emitting diode chips 10C1, 10C2 and 10C3, respectively, to overcome this drawback, as shown in FIG. An electrical test location contact 33B is added between light emitting diode chips 10C1 and 10C2, and an electrical test location contact 33C is added between light emitting diode chips 10C2 and 10C3.

As shown in FIG. 13, the leakage current characteristic of the light emitting diode chip 10C1 can be measured by measuring the third electrical test position contact 33 and the electrical test position contact 33B. Similarly, by measuring electrical test position contact 33B and electrical test position contact 33C, the leakage current characteristics of light emitting diode chip 10C2 can be measured. Similarly, by measuring the electrical test position contact 33C and the electrical test first position contact 31, the leakage current characteristics of the light emitting diode chip 10C3 can be measured. If more LED chips are connected in series, the above method can be applied mutatis mutandis.

As shown in FIG. 14, it is a structural schematic diagram of a packaging carrier according to a further embodiment of the present invention. In this embodiment, the light-emitting diode chip 10C1 is die-bonded to the main component chip A second electrode 42A, and the N-electrode 12C1 of the light-emitting diode chip 10C1 is wire-bonded to the die-bonding base P of the main component chip B second electrode 42B. It is connected to electrode terminal 42B1 and electrically connected to electrical test location contact 33B.

The light emitting diode chip 10C2 is die-bonded to the main component chip B second electrode 42B, and the N electrode 12C2 of the light emitting diode chip 10C2 is wire-bonded to the die bonding base P electrode terminal 42C1 of the main component chip C second electrode 42C. and electrically connected to the electrical test position contact 33C.

The light-emitting diode chip 10C3 is die-bonded to the second electrode 42C of the main component chip C, and the N-electrode 12C3 of the light-emitting diode chip 10C3 is connected to the first electrode 41 of the main component by wire bonding, parallel to the Zener diode 11C, which is a sub-component. connected to

In this embodiment, the five test contacts of the packaging carrier are an electrical test first position contact 31, an electrical test second position contact 32, an electrical test third position contact 33, an electrical test position contact 33B and an electrical test position contact 33B. Five double row probes can be used to make programmed measurements, including test location contacts 33C.

As can be seen from the above content, the present invention has at least the following advantages.
1. In the present invention, the light-emitting diode chip, which is the main component, can be a horizontal light-emitting diode, a flip-chip light-emitting diode, a vertical light-emitting diode, or a vertical light-emitting diode with multiple contacts, and operates as a single LED chip. It can operate as multiple LED chips connected in series, which has a wide application range and meets both packaging and test usage requirements.

2. Electrical test Using the first, second, and third position contacts to measure the electrical characteristics of each of the main light-emitting diode chip and the parallel-connected sub-component, Test the reverse bias electrical characteristics (e.g., leakage current Ir) of light-emitting diode chips as components to identify components damaged by defects in chip raw materials, mechanical stress in the packaging process, thermal stress, and electrostatic forces. Conventional problems can be solved, and the reliability of the main component, the light-emitting diode chip, is maintained.

3. By providing the electrical test first, second and third position contacts in the upper component plane or the lower bottom SMD electrode plane of the packaging carrier, various connection configurations of the test contacts can be realized.

4. Due to the design of the secondary packaging, which is packaged step by step with the first packaging material and the second packaging material, during the packaging process, the metal undergoing wire bonding becomes the main part when pulled by the packaging material. To solve the conventional problem that a light-emitting diode chip is indirectly pulled and destroyed to form a fine crack or a film is peeled off, which degrades the performance of a component but cannot be detected. can be done.

5. With the design of secondary packaging, when the component becomes inoperable, only the secondary packaging material can be removed to remove or cut off the connection lead, thus avoiding damage to the main component, the light-emitting diode chip. If it is detected again, the cause of non-operation of the component can be easily and effectively determined.

1 Semiconductor Device 1A Zener Diode 2 P Electrode 3 Packaging Carrier 4 Die Bonding Base 5 N Electrode 6 Gold Wire 7 Wire Bonding Terminal 8 Conductive Metal 9A Anode 9B Cathode 10, 10A, 10B, 10C Light Emitting Diode Chip 10C1, 10C2, 10C3 Light emitting diode chip 101 N-type electrode 102 P-type electrode 11, 11A, 11B Parallel connected subcomponents 12C1, 12C2, 12C3 N electrode 20 Packaging carrier 21 Upper component plane 22 Lower bottom SMD electrode plane 31 Electrical test first position contact 32 electrical test second position contact 33 electrical test third position contact 33B, 33C electrical test position contact 41 main component first electrode 42 main component second electrode 42A main component chip A second electrode 42B main component chip B second electrode Electrode 42B1 P-electrode terminal of die-bonding base 42C Second electrode of main component chip C 42C1 P-electrode terminal of die-bonding base 103 Die-bonding adhesive layer 43 Sub-component first electrode 44 Sub-component second electrode 51 First external electrode of carrier 52 Second external electrode of carrier 53 Relay electrode of carrier 54 Raising layer 61 First electrode conduction hole 62 Second electrode conduction hole 63 Relay electrode conduction hole of carrier 64 Metal conductive layer 65 Gold wire 66 Conductive metal 70 Packaging material 71 First packaging material 72 Second packaging material 80 Circuit board 81 Solder paste 81A Conductive film 82 Circuit board extension electrode 83 Circuit board upper plane

Claims (11)

A light-emitting diode package having a plurality of test terminals and parallel-connected components, in which a light-emitting diode chip as a main component and parallel-connected sub-components are die-bonded,
It has an upper part plane and a lower SMD electrode plane located on both sides, and the upper part plane has a main part first electrode, a main part second electrode, a sub-part first electrode and a sub-part second electrode. The light emitting diode chip as the main component is die-bonded by the main component first electrode and the main component second electrode, and the parallel connection sub-component is formed by the sub-component first electrode and the sub-component second electrode. a packaging carrier on which a component is die-bonded and the main component first electrode and the subcomponent first electrode are electrically connected;
an electrical test first position contact provided on the bottom SMD electrode plane and electrically connected to the main part first electrode and the sub-part first electrode;
an electrical test second position contact provided on the lower bottom SMD electrode plane and electrically connected to the sub-component second electrode;
and an electrical test third position contact provided on the lower bottom SMD electrode plane and electrically connected to the main component second electrode. A first external electrode of a carrier, a second external electrode of a carrier, and a relay electrode of a carrier are further provided on the bottom SMD electrode plane, and the first external electrode of the carrier is connected through a first electrode conduction hole. the second external electrode of the carrier is electrically connected to the main part second electrode through a second electrode conduction hole, 2. The light emitting diode package of claim 1 , wherein the relay electrode of the carrier is electrically connected to the second electrode of the sub-part through a relay electrode conduction hole of the carrier. wherein the lower bottom SMD electrode plane of the packaging carrier covers a circuit board, and the second external electrodes of the carrier and the relay electrodes of the carrier are electrically connected by solder paste on the lower bottom SMD electrode plane. 3. The light emitting diode package of claim 2 . The bottom SMD electrode plane of the packaging carrier is provided on a circuit board, and the first external electrode of the carrier, the second external electrode of the carrier and the relay electrode of the carrier are on the circuit board upper plane of the circuit board. 3. The light emitting diode package of claim 2 , wherein the second external electrode of the carrier and the relay electrode of the carrier are electrically connected through a conductive film on the upper plane of the circuit board. . 3. The light emitting diode chip as the main component is one selected from a horizontal light emitting diode, a flip chip light emitting diode, a vertical light emitting diode and a vertical light emitting diode with a plurality of contacts. 2. The light emitting diode package according to 1. The light emitting diode package of claim 1, wherein the material of the packaging carrier is one selected from a ceramic substrate, a BT plate, a copper substrate and a silicon carbide substrate. 2. The light emitting diode package as claimed in claim 1, wherein said light emitting diode chip as said main component comprises a plurality of light emitting diode chips connected in series. 8. The light emitting diode package of claim 7 , wherein an electrical test position contact is added between the different light emitting diode chips respectively. 2. The light-emitting diode package as claimed in claim 1, wherein said light-emitting diode chip as said main component comprises a plurality of light-emitting diode chips connected in parallel. When the parallel-connected subcomponent is one selected from Zener diodes, capacitors, and light-emitting diode chips, and when the parallel-connected subcomponent is a light-emitting diode chip, the forward voltage of the parallel-connected subcomponent is 2. The light emitting diode package as claimed in claim 1, wherein the forward voltage is close to the forward voltage of the main light emitting diode chip. 11. The method according to claim 10 , wherein when said parallel-connected sub-component is a Zener diode and is unidirectional, said parallel-connected sub-component is connected in parallel with said main component light-emitting diode chip with opposite polarity. A light emitting diode package as described.

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