TWI761123B - 封裝結構 - Google Patents

封裝結構 Download PDF

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Publication number
TWI761123B
TWI761123B TW110108807A TW110108807A TWI761123B TW I761123 B TWI761123 B TW I761123B TW 110108807 A TW110108807 A TW 110108807A TW 110108807 A TW110108807 A TW 110108807A TW I761123 B TWI761123 B TW I761123B
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Taiwan
Prior art keywords
protrusions
electrodes
package structure
electrode
power device
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TW110108807A
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English (en)
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TW202211391A (zh
Inventor
邱聖哲
李仁智
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台達電子工業股份有限公司
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Publication of TW202211391A publication Critical patent/TW202211391A/zh
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Publication of TWI761123B publication Critical patent/TWI761123B/zh

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Abstract

本發明提供一種封裝結構，包括：一導線架；一功率裝置，包括一基板、一主動層、複數個第一電極、複數個第二電極、以及一第三電極，該等第一電極的電位與該等第二電極的電位不同，且該等第一電極與該等第二電極彼此以交錯方式排列；複數個第一突出物，設置於每一該等第一電極上；複數個第二突出物，設置於每一該等第二電極上，該等第一突出物與該等第二突出物連接至該導線架；一導電單元，該導電單元的第一側連接至該功率裝置的該基板，該導電單元連接至該導線架；以及一封裝材料，覆蓋該功率裝置與該導線架，該導電單元的第二側露出該封裝材料。

Description

封裝結構
本發明係有關於一種封裝結構，特別是有關於一種具有多個突出物的封裝結構，該等突出物具有不同極性，彼此以交錯方式排列，設置於導線架與功率裝置之間。
覆晶封裝(flip chip packaging)描述了將晶粒(die)電性連接至封裝載體(package carrier)的方法，例如，作為封裝載體的基板或導線架(leadframe)提供了從晶粒至封裝體外部的連接。在標準封裝製程中，使用導線形成晶粒與載體之間的內連接。晶粒以面朝上貼附於載體，之後，將導線先與晶粒接合，再環繞並接合至載體。一般來說，導線的長度介於1-5釐米，直徑介於15-35微米。
與之不同，在覆晶封裝中，藉由直接置於晶粒表面的導電凸塊(conductive bump)形成晶粒與載體之間的內連接。將含凸塊的晶粒翻轉面朝下放置，使凸塊直接連接於載體。一般來說，凸塊的高度介於60-100微米，直徑介於80-125微米。覆晶連接(flip chip connection)一般以兩種方式形成: 使用焊錫(solder)或使用導電黏著劑。
覆晶內連接(flip chip interconnection)的使用提供了使用者許多可能的優點：訊號電感減小，因內連接長度大幅縮短(0.1釐米vs 1-5釐米)，使得訊號路徑的電感大幅降低，此為高速通訊與切換裝置的關鍵因素；電力/接地電感減小，可將電力直接引入晶粒核心，不須被路由至邊緣，此可大幅降低核心電力的雜訊，提高矽的效能；訊號密度高，可使用晶粒的整個表面作為內連接，而不僅限於邊緣，此類似於QFP封裝與BGA封裝之間的比較，因覆晶態樣可連接晶粒表面，使其在相同晶粒尺寸上可支撐數量龐大的內連接；以及晶粒微縮，相對於受焊墊限制的晶粒(晶粒尺寸由接合墊所須的邊緣空間所決定)，可減小晶粒尺寸，節省矽成本。然而，由於晶粒僅透過導電凸塊直接連接至載體，使得晶粒與載體之間的距離不足，導致崩潰電壓下降。
此外，相對於傳統以打線接合(wire bonding)貼覆晶粒的方法，高功率封裝以及例如金氧半場效電晶體(MOSFETs)、絕緣閘雙極電晶體(insulated gate bipolar transistors，IGBTs)、以及切換差分輸出結構(switched output differential structure，SODs)的分離裝置使用銅金屬連接片(copper clip)將晶粒連接至基礎基板及/或導線架。金屬連接片接合技術(clip bonding technology)以實心銅橋(solid copper bridge)取代晶粒與導線架之間的標準打線接合連接。
然而，在金屬連接片接合封裝(clip bonding package)中使用的實心銅橋(例如: 銅金屬連接片)亦被封裝材料所包覆封裝，導致被封裝的銅金屬連接片的散熱效果不佳。
因此，開發一種利用覆晶及金屬連接片接合技術所形成且可提升崩貴電壓(breakdown voltage)及實現良好散熱效果的封裝結構是眾所期待的。
根據本發明的一實施例，提供一種封裝結構，包括：一導線架；一功率裝置，包括一基板、一主動層、複數個第一電極、複數個第二電極、以及一第三電極，該主動層設置於該基板上，該等第一電極、該等第二電極與該第三電極設置於該主動層上，其中該等第一電極的電位與該等第二電極的電位不同，且該等第一電極與該等第二電極彼此以交錯方式排列；複數個第一突出物，設置於每一該等第一電極上；複數個第二突出物，設置於每一該等第二電極上，其中該等第一突出物與該等第二突出物連接至該導線架；一導電單元，具有一第一部分、一第二部分與一上表面，其中該導電單元的該第一部分連接至該功率裝置的該基板，以及該導電單元的該第二部分連接至該導線架；以及一封裝材料，覆蓋該功率裝置與該導線架，其中一部分的該導電單元的該上表面露出該封裝材料。
在部分實施例中，該功率裝置為一側向功率元件。在部分實施例中，該等第一電極包括源極，該等第二電極包括汲極，以及該第三電極包括一閘極。
在部分實施例中，該等第一突出物與該等第二突出物由銅、錫、金、或其組合所構成。在部分實施例中，該等第一突出物與該等第二突出物包括圓柱體。在部分實施例中，該等第一突出物與該等第二突出物具有一直徑，該直徑至少為65微米。在部分實施例中，該等第一突出物具有一第一間距，該第一間距至少為40微米。在部分實施例中，該等第二突出物的間距與該等第一突出物的該第一間距相同。在部分實施例中，該第一間距小於或等於該等第一突出物與該等第二突出物的該直徑。在部分實施例中，該等第一突出物與該等第二突出物具有一第二間距，該第二間距至少為65微米。在部分實施例中，該第二間距大於或等於該第一間距的1.6倍。
在部分實施例中，該導電單元包括銅。在部分實施例中，該導電單元包括金屬連接片(clip)。在部分實施例中，該功率裝置的該基板具有一第一表面積，該導電單元的該上表面露出該封裝材料的該部分具有一第二表面積，且該第二表面積大於或等於該第一表面積的1.2倍。
在部分實施例中，本發明封裝結構更包括複數個金屬墊，設置於該導線架與該等第一突出物與該等第二突出物之間。在部分實施例中，該等金屬墊由銅、銀、金、錫、或其組合所構成。在部分實施例中，該等金屬墊具有一寬度，該寬度小於或等於該等第一突出物與該等第二突出物的該直徑。
在部分實施例中，該導線架與該功率裝置具有一第三間距，該第三間距至少為60微米。
在部分實施例中，本發明封裝結構更包括一圖案化鈍化層，覆蓋該主動層以及一部分的該等第一電極與該等第二電極。在部分實施例中，本發明封裝結構更包括一圖案化高分子層，覆蓋該圖案化鈍化層以及一部分的該等第一電極與該等第二電極形成複數個開口。在部分實施例中，本發明封裝結構更包括複數個金屬層，設置於該等開口的側壁與底部，並電性連接該等第一電極與該等第二電極。在部分實施例中，該等第一突出物與該等第二突出物藉由該等金屬層連接至該等第一電極與該等第二電極。
在本發明的一實施例中，利用覆晶技術藉由多個突出物(例如，銅柱)將功率元件設置於導電架上以連接源極與汲極。具有低電位的源極(第一突出物)與具有高電位的汲極(第二突出物)彼此以交錯方式排列。設置在不同電極上具有不同極性的突出物之間的間距大約大於或等於設置在同一電極上具有相同極性的突出物之間的間距的1.6倍。本發明元件的配置與尺寸具有以下優點：相鄰突出物之間獲得窄間距；由於取代傳統打線接合連接，降低了寄生電感的影響；藉由具有適當高度的突出物增加了功率元件與導線架之間的距離(至少60微米或以上)，提升崩潰電壓；以及封裝產品具有高可靠度。
在側向功率元件中，源極與汲極位在半導體基板的同一側，電流從高電位的汲極經主動層流至低電位的源極，不須流經半導體基板，可避免元件操作時半導體基板產生寄生電阻及電感。此外，導電單元(例如，金屬連接片)從半導體基板延伸至導線架，取代了傳統須採用兩導線從半導體基板兩端點延伸至導線架的打線接合(wire bonding)，可有效降低整體封裝尺寸。
再者，具有露出導電單元的封裝結構(亦即，具有至少一部分導電單元未被封裝材料覆蓋的封裝結構，例如，導電單元露出部分的表面積大約大於或等於功率裝置基板背表面積的1.2倍)可實現良好的雙向散熱，提升元件效能。
請參閱第1-5圖，根據本發明的一實施例，提供一種封裝結構10。第1圖為封裝結構10的剖面圖。第2圖為封裝結構10的部分上視圖。第3圖為沿第2圖A-A’剖面線所得封裝結構10的部分剖面圖。第4圖為第1圖的部分放大圖。第5圖為封裝結構10的爆炸圖。
如第1圖所示，封裝結構10包括導線架12、功率裝置14、複數個第一突出物16、複數個第二突出物18、複數個第三突出物20、導電單元22、以及封裝材料24。功率裝置14的詳細結構揭露於第2、3圖。功率裝置14包括基板26、主動層28、複數個第一電極30、複數個第二電極32、以及第三電極34。主動層28設置於基板26上。第一電極30、第二電極32與第三電極34設置於主動層28上。在本實施例中，第一電極30、第二電極32與第三電極34包括條狀電極。在其他實施例中，第一電極30、第二電極32與第三電極34包括其他適合的形狀，用於後續多個突出物的配置。「條狀電極」是指電極從基板26的一側延伸至與基板26相對側相鄰的位置。第一電極30的電位與第二電極32的電位不同，例如，第一電極30為低電位，第二電極32為高電位。值得注意的是，具有低電位的第一電極30與具有高電位的第二電極32彼此以交錯方式排列，也就是，一具有低電位的第一電極30、一具有高電位的第二電極32、另一具有低電位的第一電極30、另一具有高電位的第二電極32等彼此以交錯方式排列配置於主動層28上。第一突出物16設置於每一第一電極30上，以形成設置於每一條狀第一電極30上的一排第一突出物16。第二突出物18設置於每一第二電極32上，以形成設置於每一條狀第二電極32上的一排第二突出物18。第三突出物20設置於第三電極34上，以形成設置於條狀第三電極34上的一排第三突出物20。同樣地，由於第一突出物16與第二突出物18分別連接至不同電位的電極，因此，第一突出物16的電位(極性)與第二突出物18的電位(極性)不同，例如，第一突出物16為低電位，第二突出物18為高電位。值得注意的是，具有低電位的第一突出物16與具有高電位的第二突出物18彼此以交錯方式排列，也就是，一排具有低電位的第一突出物16、一排具有高電位的第二突出物18、另一排具有低電位的第一突出物16、另一排具有高電位的第二突出物18等彼此以交錯方式分別排列配置於第一電極30與第二電極32上。
在部分實施例中，功率裝置14可包括側向功率元件(lateral power component)，例如，氮化鎵主動元件。在部分實施例中，第一電極30可包括源極，第二電極32可包括汲極，以及第三電極34可包括閘極。
在部分實施例中，第一突出物16、第二突出物18與第三突出物20可由銅、錫、金、或其組合所構成。在本實施例中，第一突出物16、第二突出物18與第三突出物20為圓柱體。在部分實施例中，第一突出物16、第二突出物18與第三突出物20可包括其他適合的形狀。有關元件的詳細尺寸揭露於第2-4圖。當第一突出物16、第二突出物18與第三突出物20為圓柱體時，第一突出物16、第二突出物18與第三突出物20的直徑D至少為65微米。第一突出物16的第一間距S1至少為40微米。第二突出物18的間距與第一突出物16的第一間距S1相同。同樣地，第三突出物20的間距與第一突出物16的第一間距S1相同。「第一間距S1」是指設置在同一電極上具有相同極性的突出物之間的間距。第一間距S1大約小於或等於第一突出物16、第二突出物18與第三突出物20的直徑D。此外，第一突出物16的其中之一與第二突出物18的其中之一的第二間距S2至少為65微米。「第二間距S2」是指設置在不同電極上具有不同極性的突出物之間的間距。第二間距S2大約大於或等於第一間距S1的1.6倍。導線架12與功率裝置14的第三間距H至少為60微米。
在第1圖中，功率裝置14藉由第一突出物16、第二突出物18與第三突出物20連接至導線架12。導電單元22包括與功率裝置14的基板26接觸的第一部分、與導線架12接觸的第二部分、上表面22b、以及下表面22a。導電單元22的第一部分藉由導電單元22的部分下表面22a連接至功率裝置14的基板26。導電單元22的第二部分藉由導電單元22的部分下表面22a連接至導線架12，形成接腳23。在部分實施例中，導電單元22可包括多個接腳連接導線架12。封裝材料24覆蓋功率裝置14與導線架12。導電單元22的部分上表面22b露出封裝材料24。
在部分實施例中，導電單元22可包括銅。在部分實施例中，導電單元22可包括金屬連接片(clip)。在第1圖中，功率裝置14的基板26具有第一表面積A1。導電單元22的上表面22b露出封裝材料24的部分具有第二表面積A2。第二表面積A2大約大於或等於第一表面積A1的1.2倍。根據封裝結構10的爆炸圖(如第5圖所示)，更清楚地揭示導電單元22與功率裝置14之間的尺寸關係。
其他相關元件揭露於第3圖。封裝結構10更包括黏著層36’，設置於第一突出物16、第二突出物18與第三突出物20上。在部分實施例中，黏著層36’可包括焊錫(solder)。第一突出物16、第二突出物18與第三突出物20更包括藉由複數個金屬墊36連接至1812，如第1、4圖所示。在部分實施例中，金屬墊36可由銅、銀、金、錫、或其組合所構成。金屬墊36的寬度W大約小於或等於第一突出物16、第二突出物18與第三突出物20的直徑D，如第4圖所示。
在第3圖中，封裝結構10更包括圖案化鈍化層38，覆蓋主動層28以及一部分的第一電極30、第二電極32與第三電極34。封裝結構10更包括圖案化高分子層40，覆蓋圖案化鈍化層38以及一部分的第一電極30、第二電極32與第三電極34形成複數個開口42。封裝結構10更包括複數個金屬層44，設置於開口42的側壁與底部，並電性連接第一電極30、第二電極32與第三電極34。在部分實施例中，金屬層44作為凸塊下金屬層(under bump metal，UBM)，以利後續第一突出物16、第二突出物18與第三突出物20的電鍍製程。第一突出物16、第二突出物18與第三突出物20藉由金屬層44連接至第一電極30、第二電極32與第三電極34。
在本發明的一實施例中，利用覆晶技術藉由多個突出物(例如，銅柱)將功率元件設置於導電架上以連接源極與汲極。具有低電位的源極(第一突出物)與具有高電位的汲極(第二突出物)彼此以交錯方式排列。設置在不同電極上具有不同極性的突出物之間的間距大約大於或等於設置在同一電極上具有相同極性的突出物之間的間距的1.6倍。本發明元件的配置與尺寸具有以下優點：相鄰突出物之間獲得窄間距；由於取代傳統打線接合連接，降低了寄生電感的影響；藉由具有適當高度的突出物增加了功率元件與導線架之間的距離(至少60微米或以上)，提升崩潰電壓；以及封裝產品具有高可靠度。
在側向功率元件中，源極與汲極位在半導體基板的同一側，電流從高電位的汲極經主動層流至低電位的源極，不須流經半導體基板，可避免元件操作時半導體基板產生寄生電阻及電感。此外，導電單元(例如，金屬連接片)從半導體基板延伸至導線架，取代了傳統須採用兩導線從半導體基板兩端點延伸至導線架的打線接合(wire bonding)，可有效降低整體封裝尺寸。
再者，具有露出導電單元的封裝結構(亦即，具有至少一部分導電單元未被封裝材料覆蓋的封裝結構，例如，導電單元露出部分的表面積大約大於或等於功率裝置基板背表面積的1.2倍)可實現良好的雙向散熱，提升元件效能。
10:封裝結構 12:導線架 14:功率裝置 16:第一突出物 18:第二突出物 20:第三突出物 22:導電單元 22a:導電單元的下表面 22b:導電單元的上表面 23:接腳 24:封裝材料 26:基板 28:主動層 30:第一電極 32:第二電極 34:第三電極 36:金屬墊 36’:黏著層 38:圖案化鈍化層 40:圖案化高分子層 42:開口 44:金屬層 A1:第一表面積 A2:第二表面積 D:第一突出物、第二突出物與第三突出物的直徑 H:導線架與功率裝置的間距 S1:第一間距 S2:第一突出物與第二突出物的間距 W:金屬墊的寬度
第1圖係根據本發明的一實施例，一種封裝結構的剖面圖； 第2圖係根據本發明的一實施例，一種封裝結構的部分上視圖； 第3圖係根據本發明的一實施例，一種封裝結構的部分剖面圖； 第4圖係根據本發明的一實施例，一種封裝結構的部分剖面圖；以及 第5圖係根據本發明的一實施例，一種封裝結構的爆炸圖。
14:功率裝置 16:第一突出物 18:第二突出物 20:第三突出物 26:基板 28:主動層 30:第一電極 32:第二電極 34:第三電極 S1:第一間距 S2:第一突出物與第二突出物的間距

Claims (19)

  1. 一種封裝結構，包括： 一導線架； 一功率裝置，包括一基板、一主動層、複數個第一電極、複數個第二電極、以及一第三電極，該主動層設置於該基板上，該等第一電極、該等第二電極與該第三電極設置於該主動層上，其中該等第一電極的電位與該等第二電極的電位不同，且該等第一電極與該等第二電極彼此以交錯方式排列； 複數個第一突出物，設置於每一該等第一電極上； 複數個第二突出物，設置於每一該等第二電極上，其中該等第一突出物與該等第二突出物連接至該導線架； 一導電單元，具有一第一部分、一第二部分與一上表面，其中該導電單元的該第一部分連接至該功率裝置的該基板，以及該導電單元的該第二部分連接至該導線架；以及 一封裝材料，覆蓋該功率裝置與該導線架，其中一部分的該導電單元的該上表面露出該封裝材料。
  2. 如請求項1的封裝結構，其中該功率裝置為一側向功率元件。
  3. 如請求項1的封裝結構，其中該等第一電極包括源極，該等第二電極包括汲極，以及該第三電極包括一閘極。
  4. 如請求項1的封裝結構，其中該等第一突出物與該等第二突出物由銅、錫、金、或其組合所構成。
  5. 如請求項1的封裝結構，其中該等第一突出物與該等第二突出物具有一直徑，該直徑至少為65微米。
  6. 如請求項5的封裝結構，其中該等第一突出物具有一第一間距，該第一間距至少為40微米。
  7. 如請求項6的封裝結構，其中該等第二突出物的間距與該等第一突出物的該第一間距相同。
  8. 如請求項6的封裝結構，其中該第一間距小於或等於該等第一突出物與該等第二突出物的該直徑。
  9. 如請求項6的封裝結構，其中該等第一突出物與該等第二突出物具有一第二間距，該第二間距至少為65微米。
  10. 如請求項9的封裝結構，其中該第二間距大於或等於該第一間距的1.6倍。
  11. 如請求項1的封裝結構，其中該功率裝置的該基板具有一第一表面積，該導電單元的該上表面露出該封裝材料的該部分具有一第二表面積，且該第二表面積大於或等於該第一表面積的1.2倍。
  12. 如請求項5的封裝結構，更包括複數個金屬墊，設置於該導線架與該等第一突出物與該等第二突出物之間。
  13. 如請求項12的封裝結構，其中該等金屬墊由銅、銀、金、錫、或其組合所構成。
  14. 如請求項12的封裝結構，其中該等金屬墊具有一寬度，該寬度小於或等於該等第一突出物與該等第二突出物的該直徑。
  15. 如請求項1的封裝結構，其中該導線架與該功率裝置具有一第三間距，該第三間距至少為60微米。
  16. 如請求項1的封裝結構，更包括一圖案化鈍化層，覆蓋該主動層以及一部分的該等第一電極與該等第二電極。
  17. 如請求項16的封裝結構，更包括一圖案化高分子層，覆蓋該圖案化鈍化層以及一部分的該等第一電極與該等第二電極形成複數個開口。
  18. 如請求項17的封裝結構，更包括複數個金屬層，設置於該等開口的側壁與底部，並且電性連接該等第一電極及該等第二電極。
  19. 如請求項18的封裝結構，其中該等第一突出物與該等第二突出物藉由該等金屬層連接至該等第一電極與該等第二電極。
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