TWI758934B - Display device and method of forming the same - Google Patents

Abstract

In some embodiments, the present disclosure relates to a display device that includes a first reflector electrode and a second reflector electrode that is separated from the first reflector electrode. The display device further includes an isolation structure that overlies the first and second reflector electrodes. The isolation structure includes a first and second portion. The first portion overlies the first reflector electrode and has a first thickness. The second portion overlies the second reflector electrode, has a second thickness greater than the first thickness, and is separated from the first portion of the isolation structure. The display device also includes a first optical emitter structure and a second optical emitter structure that respectively overlie the first portion and the second portion of the isolation structure.

Description

Display device and method of forming the same

Embodiments of the present invention relate to a display device and a method for forming the same.

Many modern electronic devices, such as televisions and cellular devices, use image display devices to convert digital data into optical images. For this purpose, the image display device may include an array of pixel regions. Each pixel region can have an optical emitter structure and can be coupled to a semiconductor device. The semiconductor device can selectively apply an electrical signal (eg, a voltage) to the optical emitter structure. After the electrical signal is applied, the optical emitter structure can emit an optical signal (eg, light). The optical emitter structure may be, for example, an organic light emitting diode (OLED) or some other suitable light emitting device.

According to an embodiment of the present disclosure, a display device includes a first reflector electrode, a second reflector electrode, an isolation structure, a first optical emitter structure, and a second optical emitter structure. The second reflector electrode is spaced apart from the first reflector electrode. every The isolation structure overlies the first reflector electrode and the second reflector electrode, and the isolation structure includes a first portion overlying the first reflector electrode and having a first thickness and an overlying portion overlying the first reflector electrode and having a first thickness. the second portion on the second reflector electrode. The second portion has a second thickness greater than the first thickness and is spaced from the first portion of the isolation structure. A first optical emitter structure and a second optical emitter structure respectively overlie the first portion and the second portion of the isolation structure.

According to an embodiment of the present disclosure, a display device includes a first reflector electrode, a second reflector electrode, a first isolation layer, a second isolation layer, a first optical emitter structure, a second optical emitter structure, a first conductive layer structure and a second conductive structure. The first reflector electrode and the second reflector electrode are located on the interconnect structure. The first isolation layer includes a pair of segments spaced apart from each other and overlying the first reflector electrode and the second reflector electrode, respectively. A second isolation layer overlies the first isolation layer and the second reflector electrode, but does not overlie the first reflector electrode. The first optical emitter structure overlies the first isolation layer and the first reflector electrode, and the second optical emitter structure overlies the second isolation layer and the second reflector on the electrode. A first conductive structure and a second conductive structure extend from the first reflector electrode to the first optical emitter structure and from the second reflector electrode to the second optical emitter structure, respectively, wherein the The first conductive structure extends through the first isolation layer, and wherein the second conductive structure extends through the first isolation layer and the second isolation layer.

According to an embodiment of the present disclosure, a method of forming a display device includes: forming a first reflector electrode and a second reflector electrode on an interconnect structure, wherein the The first reflector electrode and the second reflector electrode are laterally spaced; a first isolation layer is deposited on the first reflector electrode and the second reflector electrode; a first shielding layer on the first reflector electrode but not overlying the second reflector electrode; depositing a second shielding layer on the first shielding layer and on the first shielding layer; A second shielding layer is formed on the second isolation layer, and the second shielding layer is directly overlying the second reflector electrode but not overlying the first reflector electrode; performing the first a removal process to remove portions of the first isolation layer and the second isolation layer not covered by the first masking layer or the second masking layer; and performing a second removal a manufacturing process to remove the first shielding layer and the second shielding layer.

100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300, 1400, 1500, 1600, 1700, 1800, 1900A, 1900B, 1900C, 2000, 2100: Cutaway view

101a: first pixel area

101b: Second pixel area

101c: The third pixel area

102a: first reflector electrode

102b: Second reflector electrode

102c: Third reflector electrode

104: The first blocking structure

106: Isolation Structure

106a: Part 1

106b: Part II

106c: Part Three

108a: first through hole structure

108b: second via structure

108c: third via structure

110a: First Optical Emitter Structure

110b: Second Optical Emitter Structure

110c: Third Optical Emitter Structure

112a: first transparent electrode

112b: second transparent electrode

112c: third transparent electrode

114: Second blocking structure

120: Control circuit system

122: Base

124: Semiconductor Devices

124a: source/drain region

124b: gate electrode

124c: gate dielectric layer

130: Inline Structure

132: Interconnected Dielectric Structure

134: Internal wiring

136: Internal communication hole

150: First Line

152: Second line

202: First Light Path

204: Second Light Path

302: First isolation layer

304: Second isolation layer

306: Third isolation layer

308: The first interface

310: Second interface

312: The third interface

314: Fourth interface

316: Fifth interface

318: Sixth Interface

402: Seventh interface

602: first dielectric layer

603: First barrier layer

604: Second Dielectric Layer

702: Cavity

802: Conductive Materials

1004: First Conformal Masking Layer

1006: first conformal oxide layer

1106: first oxide layer

1204: first masking layer

1204s: Outside Wall

1402: Second Conformal Masking Layer

1404: Second Conformal Oxide Layer

1502: Second masking layer

1504: Second oxide layer

1702: Third Conformal Masking Layer

1704: Third Conformal Oxide Layer

1802: The third masking layer

1804: Third oxide layer

1902: First removal process

2200: Methods

2202, 2204, 2206, 2208, 2210, 2212, 2214: Actions

t1: first thickness

t2: second thickness

t3: the third thickness

t4: Fourth thickness

t5: fifth thickness

w1: first width

w2: second width

w3: third width

Various aspects of the present disclosure are best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

1 illustrates a cross-sectional view of some embodiments of a display device having an isolation structure disposed over a reflector electrode structure, wherein the isolation structure includes a first portion and further includes a spaced apart from the first portion and having a different The second part of the thickness.

2 illustrates a cross-sectional view of some additional embodiments of the display device of FIG. 1, and an exemplary light path through a portion of the isolation structure.

3 and 4 illustrate cross-sectional views of some additional embodiments of the display device of FIG. 1, wherein the display device includes isolation structures having different layers of materials.

5-18, 19A-19C, 20, and 21 illustrate cross-sectional views of some embodiments of methods of forming a display device having isolation structures disposed over reflector electrode structures, wherein the isolation structures The first portion and the second portion are included spaced apart from each other to mitigate damage to the reflector electrode structure.

22 illustrates a flowchart of some embodiments of the method corresponding to FIGS. 5-18 , 19A-19C, 20 and 21 .

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which the first feature is formed in direct contact with the second feature. Embodiments in which additional features may be formed between a feature and a second feature such that the first feature and the second feature may not be in direct contact. Additionally, the present disclosure may reuse reference numbers and/or letters in various instances. Such repetition is for the purpose of brevity and clarity and is not itself indicative of the relationship between the various embodiments and/or configurations discussed.

Also, for ease of description, for example, "beneath", "below", "lower", Spatially relative terms such as "above", "upper" and the like are used to describe the relationship between one element or feature and another (other) element or feature shown in the figures. In addition to the orientation depicted in the figures, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

A display device includes an array of pixel regions, wherein each pixel region includes a portion of an isolation structure disposed between a reflector electrode and a transparent electrode. The via structure may extend through the isolation structure to electrically couple the reflector electrode to the transparent electrode. The optical emitter structure may be arranged over the transparent electrode. The isolation structure may comprise silicon dioxide, and the portion of the isolation structure may have a thickness corresponding to a certain color. For example, during operation of the display device, electrical signals (eg, voltages) may be applied to the transparent electrodes from circuitry coupled to the reflector electrodes, via structures, and transparent electrodes. The electrical signal can cause light to be generated at the interface between the optical emitter structure and the transparent electrode (eg, due to electron-hole recombination). Light may be reflected by the top surface of the isolation structure, and/or may travel through the isolation structure, reflected by the reflector electrodes, and travel back toward the top surface of the isolation structure. Due to constructive interference of a given wavelength of light at the top surface of the isolation structure and/or destructive interference of other wavelengths of light at the top surface of the isolation The top surface emits colored light depending on the thickness of the portion of the isolation structure.

To form the isolation structure, a first isolation layer may be formed, for example, over the first reflector electrode and the second reflector electrode. The first isolation layer can then be patterned to remove The second reflector electrode removes the first isolation layer. A second isolation layer can then be formed over the first isolation layer and the second reflector electrode. However, the patterning of the first isolation layer may cause damage to the top surface of the second reflector electrode (eg, appearance of pits, crystal defects, increased surface roughness, etc.) and thus affect the second isolation layer interface with the second reflector electrode. For example, an etching process can be used to remove the first isolation layer covering the second reflector electrode. The etching process may use dry etchants and cause damage to the top surface of the second reflector electrode by increasing the surface roughness. Since the second reflector electrode receives and reflects light at the top surface of the second reflector electrode, when the top surface is damaged, the reflected light may scatter, which may, for example, result in the emitted light being a different color and/or reduced The intensity of the light emitted. Therefore, the aforementioned patterning process may cause the display device to be unreliable.

Various embodiments of the present disclosure relate to a method of forming an isolation structure including a first portion, a second portion, and a third portion separated from each other to mitigate damage to an underlying reflector electrode structure of a display device. In some embodiments, the first reflector electrode and the second reflector electrode are formed over the interconnect structure. A first spacer layer is deposited over the first reflector electrode and the second reflector electrode. A first shielding layer is formed over the first reflector electrode such that the first shielding layer directly overlies the first reflector electrode and does not directly overlie the second reflector electrode. A second isolation layer is deposited over the first isolation layer and over the first masking layer. A second shielding layer is then formed over the second reflector electrode such that the second shielding layer directly overlies the second reflector electrode and not directly overlies the first reflector electrode or the first shielding layer.

A first removal process is performed to remove the difference between the first isolation layer and the second isolation layer The portion directly under the first shielding layer or the second shielding layer. The first masking layer and the second masking layer are hard masks, and thus during the first removal process, the first masking layer and the second masking layer protect the underlying first isolation layer, second isolation layer, first reflector The reflector electrode and the second reflector electrode are protected from damage caused by the first removal process. For example, in some embodiments, the first removal process utilizes plasma dry etching, and the first and second shielding layers block ions from passing through to the underlying first and second isolation layers and The underlying first reflector electrode and the second reflector electrode. In addition, a second removing process is performed to remove the first shielding layer and the second shielding layer. A second removal process may be performed by wet etching to selectively remove the first shielding layer and the second shielding layer, while the first reflector electrode and the second reflector electrode are separated by the first isolation layer and the second layer protection. Therefore, since the first reflector electrode and the second reflector electrode are respectively protected during the first removal process and the second removal process of forming the isolation structure, the first reflector electrode and the second reflector electrode are alleviated. damage, resulting in a reliable device.

1 illustrates a cross-sectional view 100 of some embodiments of a display device including an isolation structure having a first portion, a second portion, and a third portion separated from each other.

The display device of the cross-sectional view 100 includes a first pixel area 101a, a second pixel area 101b, and a third pixel area 101c. Each of the first pixel region 101a, the second pixel region 101b, and the third pixel region 101c is configured to emit light of a different color (eg, red, green) upon receiving an electrical signal (eg, a voltage) , blue), and the color of the light depends on the thickness and material of the isolation structure 106 . For example, in some implementations For example, the first pixel region 101a may include a first portion 106a of the isolation structure 106 having a first thickness t1; the second pixel region 101b may include a second portion 106b of the isolation structure 106 having a second thickness t2; The three-pixel region 101c may include a third portion 106c of the isolation structure 106 having a third thickness t3. In some embodiments, the first thickness t1 , the second thickness t2 and the third thickness t3 are different from each other. For example, in some embodiments, the first thickness t1 may be less than the second thickness t2 and the third thickness t3, and the second thickness t2 may be less than the third thickness t3.

In some embodiments, the first portion 106a, the second portion 106b, and the third portion 106c of the isolation structure 106 may each include one or more oxides, such as, for example, silicon dioxide, aluminum oxide, and the like. In other embodiments, the first portion 106a, the second portion 106b, and the third portion 106c of the isolation structure 106 may comprise a nitride (eg, silicon nitride) or some other material with optical properties such that it is visible from the surface of the material Colored light, and the colored light depends on the thickness of each part of the isolation structure 106 (the first part 106a, the second part 106b, the third part 106c). For example, the first thickness t1 may correspond to red light; the second thickness t2 may correspond to blue light; and the third thickness t3 may correspond to green light.

The first portion 106a of the isolation structure 106 may be disposed between the first reflector electrode 102a and the first transparent electrode 112a. The second portion 106b of the isolation structure 106 may be arranged between the second reflector electrode 102b and the second transparent electrode 112b. The third portion 106c of the isolation structure 106 may be arranged between the third reflector electrode 102c and the third transparent electrode 112c. The first optical emitter structure 110a, the second optical emitter structure 110b and the third optical emitter structure 110c may be respectively arranged on the first transparent on the electrode 112a, the second transparent electrode 112b and the third transparent electrode 112c. In some embodiments, the first via structure 108a, the second via structure 108b, and the third via structure 108 extend through the first portion 106a of the isolation structure 106, the second portion 106b of the isolation structure 106, and the isolation structure 106, respectively of the third part 106c. The via structures (first via structure 108a, second via structure 108b, third via structure, 108c) are isolated from the top surfaces of portions of isolation structure 106 (first portion 106a, second portion 106b, third portion 106c) extends to the bottom surface. Thus, the first via structure 108a can electrically couple the first reflector electrode 102a to the first transparent electrode 112a; the second via structure 108b can electrically couple the second reflector electrode 102b to the second transparent electrode 112b; The three-via structure 108c can electrically couple the third reflector electrode 102c to the third transparent electrode 112c.

In some embodiments, the first reflector electrode 102a , the second reflector electrode 102b , and the third reflector electrode 102c may be coupled to the control circuitry 120 . For example, in some embodiments, the first reflector electrode 102a, the second reflector electrode 102b, and the third reflector electrode 102c are disposed over the interconnect structure 130, the interconnect structure 130 including embedded in A network of interconnecting wires 134 and interconnecting vias 136 in the dielectric structure 132 are connected. In some embodiments, interconnect structure 130 is disposed over substrate 122 and coupled to semiconductor device 124 . In some embodiments, the semiconductor device 124 may be, for example, a metal oxide semiconductor field-effect transistor (MOSFET) including a source located within the substrate 122 /Drain region 124a and gate electrode 124b on the substrate 122 . The gate electrode 124b may pass through the gate dielectric layer 124c is spaced from the base 122. The control circuitry 120 is configured to selectively supply electrical signals (eg, voltages) to each of the first pixel region 101a, the second pixel region 101b, and the third pixel region 101c to transmit digital data from Colored light indicated. For example, if an electrical signal (eg, voltage) is supplied from the control circuitry 120 to the first reflector electrode 102a, the electrical signal (eg, voltage) may cause the first optical emitter structure 110a to generate light, and the Light may reflect from the top surface of the first portion 106a of the isolation structure 106 and/or travel through the first portion 106a of the isolation structure 106 , reflect from the first reflector electrode 102a and pass through the top surface of the first portion 106a of the isolation structure 106 shoot. Due to constructive and/or destructive interference, colored light can be seen depending on the first thickness t1 and the material of the first portion 106a of the isolation structure 106 .

In some embodiments, the first blocking structure 104 and/or the second blocking structure 114 separates the first pixel region 101a, the second pixel region 101b and the third pixel region 101c. In some embodiments, each of the first portion 106a , the second portion 106b , and the third portion 106c of the isolation structure 106 are completely separated from each other by the second barrier structure 114 .

For example, in some embodiments, the first line 150 may be disposed between the first portion 106a and the second portion 106b of the isolation structure 106 without intersecting the first portion 106a or the second portion 106b of the isolation structure 106 . The first line 150 may extend continuously in a first direction orthogonal to the upper surface of the first reflector electrode 102a, and may also be arranged between the first reflector electrode 102a and the second reflector electrode 102b, the first between the transparent electrode 112a and the second transparent electrode 112b and between the first optical emitter structure 110a and the second optical emitter structure 110b. in some implementations For example, the first line 150 may intersect the first barrier structure 104 and the second barrier structure 114 . Therefore, in some embodiments, the second barrier structure 114 directly overlies the first barrier structure 104 . Furthermore, a second line 152 extending parallel to the first line 150 and continuously in the first direction may be arranged between the second portion 106b of the isolation structure 106 and the third portion 106c of the isolation structure 106 without being connected to the isolation structure The second portion 106b or the third portion 106c of 106 intersects. In some embodiments, as a result of protecting the first reflector electrode 102a, the second reflector electrode 102b, and the third reflector electrode 102c during fabrication of the isolation structure 106, the first portion 106a, the second portion 106b of the isolation structure 106 and third portion 106c may be completely spaced apart from each other; in some embodiments, the spacing between first, second, and third portions 106a, 106b, and 106c of isolation structure 106 also relieves the first pixel region Optical interference between each of the second pixel region 101a, the second pixel region 101b, and the third pixel region 101c to provide a reliable display device.

2 illustrates a cross-sectional view 200 of some embodiments of a display device including isolation structures having first, second, and third portions spaced from each other, and an exemplary light path during operation of the display device.

The display device in cross-sectional view 200 includes a first reflector electrode 102a having a first width w1, a second reflector electrode 102b having a second width w2, and a third reflector electrode 102c having a third width w3. In some embodiments, the first width w1 , the second width w2 and the third width w3 may be substantially equal to each other, such as shown in FIG. 1 , while in other embodiments, as shown in FIG. 2 , the first width The width w1 , the second width w2 and the third width w3 may be different from each other. For example, in some embodiments Among them, the third width w3 may be smaller than the second width w2, and the second width w2 may be smaller than the first width w1. In some embodiments, the minimum width (eg, first width w1 ) corresponds to a pixel region (eg, a first pixel region) having a portion (eg, first portion 106a ) of isolation structure 106 having a minimum thickness (eg, first thickness t1 ) Element area 101a). Similarly, in some embodiments, the maximum width (eg, third width w3 ) corresponds to the portion (eg, third portion 106c ) having the greatest thickness (eg, third thickness t3 ) in the isolation structure (eg, isolation structure 106 ) pixel area (for example, the third pixel area 101c). However, in other embodiments, the reflector electrode (eg, the first reflector electrode) in each pixel region (eg, the first pixel region 101a, the second pixel region 101b, the third pixel region 101c) 102a, second reflector electrode 102b, third reflector electrode 102c) widths (eg, first width w1, second width w2, third width w3) and portions of isolation structures (eg, isolation structure 106) (eg, , the thicknesses (eg, the first thickness t1, the second thickness t2, the third thickness t3) of the first isolation structure 106a, the second isolation structure 106b, and the third isolation structure 106c) are not related.

The cross-sectional view 200 also illustrates an example first light path 202 in the first pixel region 101a and an example second light path 204 in the second pixel region 101b. In some embodiments, the first optical emitter structure 110a and the second optical emitter are due to electrical signals (eg, voltages) applied by the control circuitry 120 to the first reflector electrode 102a and the second reflector electrode 102b, respectively. Structure 110b produces light. For example, in cross-sectional view 200, first pixel region 101a and second pixel region 101b are "ON" (eg, generated at first optical emitter structure 110a and second optical emitter structure 110b) light), while the third pixel region 101c is "OFF" (eg, the third optical The emitter structure 110c produces no light). In first pixel region 101a, exemplary first light path 202 illustrates how light generated at first optical emitter structure 110a may be reflected by the top surface of first portion 106a of isolation structure 106 in some embodiments, and/or travels through the first portion 106a of the isolation structure 106 , is reflected by the first reflector electrode 102a and travels back up toward the top surface of the first portion 106a of the isolation structure 106 . Colored light having the first wavelength may be emitted/visible from the top surface of the first optical emitter structure 110a in the first pixel region 101a due to constructive interference of the first wavelength and/or destructive interference of the remaining wavelengths. The first wavelength is associated with the first thickness t1 and material of the first portion 106a of the isolation structure 106, and in some embodiments, the first wavelength is the only wavelength emitted/visible from the top surface of the first optical emitter structure 110a or dominant wavelength.

Similarly, in second pixel region 101b, exemplary second light path 204 illustrates how light generated at second optical emitter structure 110b may be isolated by second portion 106b of isolation structure 106 in some embodiments The top surface of the isolation structure 106 reflects and/or travels through the second portion 106b of the isolation structure 106 , is reflected by the second reflector electrode 102b and travels back up toward the top surface of the second portion 106b of the isolation structure 106 . Colored light having the second wavelength may be emitted/visible from the top surface of the second optical emitter structure 110b in the second pixel region 101b due to constructive interference of the second wavelength and/or destructive interference of the remaining wavelengths. The second wavelength is associated with the second thickness t2 and material of the second portion 106b of the isolation structure 106, and in some embodiments, the second wavelength is the only one emitted/visible from the top surface of the second optical emitter structure 110b wavelength or dominant wavelength. In some embodiments, due to the second The thickness t2 is different from the first thickness t1 of the first portion 106a of the isolation structure 106, so the second wavelength will be different from the first wavelength, and thus, the second pixel region 101b emits a different color light than the first pixel region 101a. Accordingly, the control circuitry 120 may use the digital data to selectively "turn on" one or more pixel regions (eg, the first pixel region 101a, the second pixel region 101b, the third pixel region 101c) to Generate optical images.

3 illustrates a cross-sectional view 300 of some embodiments of a display device including an isolation structure having a first portion, a second portion, and a third portion, wherein the second portion and the third portion include multiple layers.

The display device in cross-sectional view 300 includes: 1) a first portion 106a of the isolation structure 106 including a first isolation layer 302; 2) a second portion 106b of the isolation structure 106 including a second isolation layer disposed over the first isolation layer 302 and 3) the third portion 106c of the isolation structure 106 including the second isolation layer 304 disposed above the first isolation layer 302 and disposed below the third isolation layer 306. The first portion 106a , the second portion 106b and the third portion 106c of the isolation structure 106 are still separated from each other by the second barrier structure 114 . In some embodiments, the first isolation layer 302, the second isolation layer 304, and the third isolation layer 306 comprise different materials. For example, in some embodiments, the first isolation layer 302 may include aluminum oxide; the second isolation layer 304 may include silicon dioxide; and the third isolation layer 306 may include some other material with optical properties, such as nitride silicon. In other embodiments, each of the first isolation layer 302, the second isolation layer 304, and the third isolation layer 306 may comprise the same material, such as, for example, silicon dioxide. In such an embodiment, the isolation layers (the first isolation layer 302, the second isolation layer 304, the third isolation layer 306) may be indistinguishable from each other, and the isolation structure The first, second, and third portions 106a, 106b, and 106c of 106 may look like the first, second, and third portions 106a, 106b, and 106c of isolation structure 106 shown in cross-sectional view 100 of FIG.

In some embodiments, the first thickness t1 of the first portion 106a of the isolation structure 106 may be equal to the thickness of the first isolation layer 302 . In some embodiments, the first portion 106a of the isolation structure 106 contacts the first reflector electrode 102a at the first interface 308 and contacts the first transparent electrode 112a at the second interface 310 . The first thickness t1 of the first portion 106a of the isolation structure 106 may be measured from the first interface 308 to the second interface 310 in a first direction orthogonal to the top surface of the first reflector electrode 102a. In some embodiments, the second thickness t2 of the second portion 106b of the isolation structure 106 may be equal to the sum of the thickness of the first isolation layer 302 and the thickness of the second isolation layer 304 . In some embodiments, the second portion 106b of the isolation structure 106 contacts the second reflector electrode 102b at the third interface 312 and contacts the second transparent electrode 112b at the fourth interface 314 . The second thickness t2 of the second portion 106b of the isolation structure 106 may be measured from the third interface 312 to the fourth interface 314 in the first direction. In some embodiments, the third thickness t3 of the third portion 106c of the isolation structure 106 may be equal to the sum of the thickness of the first isolation layer 302 , the thickness of the second isolation layer 304 , and the thickness of the third isolation layer 306 . In some embodiments, the third portion 106c of the isolation structure 106 contacts the third reflector electrode 102c at the fifth interface 316 and the third transparent electrode 112c at the sixth interface 318 . The third thickness t3 of the third portion 106c of the isolation structure 106 may be measured from the fifth interface 316 to the sixth interface 318 in the first direction.

The cross-sectional view 300 of FIG. 3 further illustrates that, in some embodiments, the first The via structure 108a, the second via structure 108b, and the third via structure 108c may extend completely through the first portion 106a, the second portion 106b, and the third portion 106c of the isolation structure 106, respectively. In some embodiments, the via structures (first via structure 108a, second via structure 108b, third via structure 108c) include completely filling each via structure (first via structure 108a, second via structure 108c) The material of the space between the outer sidewalls of the structure 108b, the third third via structure 108c). In other embodiments (eg, FIG. 1 ), the transparent electrodes (first transparent electrode 112a, second transparent electrode 112b, transparent electrode 112c) fill the via structures (first via structure 108a, second via structure 108b, Some of the spaces between the outer sidewalls of the third via structure 108c). In this embodiment, since the reflector electrodes (the first reflector electrode 102a, the second reflector electrode 102b, the third reflector electrode 102c) and the transparent electrodes (the first transparent electrode 112a, the second transparent electrode 112b, the third The through-hole structures (the first through-hole structure 108a, the second through-hole structure 108b, the third through-hole structure 108c) between the three transparent electrodes 112c) are thinner, so the transparent electrodes (the first transparent electrode 112a, the second through-hole structure 108c) are thinner. 112b, the third transparent electrode 112c) and the reflector electrodes (the first reflector electrode 102a, the second reflector electrode 102b, the third reflector electrode 102c) can be electrically connected more efficiently.

4 illustrates a cross-sectional view 400 of an isolation structure having a first portion, a second portion, and a third portion, wherein the third portion of the isolation structure includes a second layer and a third layer comprising the same material.

Cross-sectional view 400 of FIG. 4 illustrates some embodiments of display devices in which portions of isolation structures (isolation structures 106) (first isolation structure 106a, second isolation structure 106b, third isolation structure 106c) may be larger than their respective overlying transparent electricity electrodes (first transparent electrode 112a, second transparent electrode 112b, third transparent electrode 112c) and/or optical emitter structures (first optical emitter structure 110a, second optical emitter structure 110b, third optical emitter structure 110c) wide.

In addition, the display device in the cross-sectional view 400 includes the first portion 106 a , the second portion 106 b and the third portion 106 c of the isolation structure 106 . In some embodiments, the third portion 106c of the isolation structure 106 may include the first isolation layer 302 , the second isolation layer 304 , and the third isolation layer 304 . In some embodiments, the first isolation layer 302 may include a first material, and the second isolation layer 304 and the third isolation layer 306 may include a second material that is different from the first material. For example, in some embodiments, the first material may include aluminum oxide and the second material may include silicon dioxide. In some embodiments, the first isolation layer 302 may be thinner than each of the second isolation layer 304 and the third isolation layer 306 . In such an embodiment, the first isolation layer 302 may comprise, for example, aluminum oxide, since, during deposition, it may be easier to control the thickness of aluminum oxide than, for example, silicon dioxide. Since the second isolation layer 304 and the third isolation layer 306 may include the same second material, the seventh interface 402 between the second isolation layer 304 and the third isolation layer 306 may be indistinguishable, as shown by the dotted line.

Figures 5-18, 19A-19C, 20, and 21 illustrate cross-sectional views 500 of some embodiments of methods of forming isolation structures over reflector electrode structures to prevent damage to the reflector electrode structures and produce reliable display devices To cross-sectional view 1800, cross-sectional view 1900A to cross-sectional view 1900C, cross-sectional view 2000, and cross-sectional view 2100. Although FIGS. 5-18, 19A-19C, 20, and 21 are described with respect to one method, it should be understood that FIGS. 5-18, 19A-19C, 20 And the structure disclosed in FIG. 21 is not limited to this method, but can exist as a structure independently of the method.

As shown in cross-sectional view 500 of FIG. 5 , in some embodiments, control circuitry 120 may be formed over substrate 122 . In some embodiments, control circuitry 120 may include interconnect structures 130 disposed over substrate 122 . The interconnect structure 130 may include interconnect wires 134 and interconnect holes 136 embedded in the interconnect dielectric structure 132 . In some embodiments, the interconnect wires 134 and the interconnect vias 136 may include copper, tungsten, or the like. The interconnect structure 130 may be coupled to the semiconductor device 124 integrated on the substrate 122 . In some embodiments, semiconductor device 124 may be or may include a metal oxide semiconductor field effect transistor (MOSFET), wherein the MOSFET includes source/drain regions 124a in substrate 122 . The semiconductor device 124 may also include a gate electrode 124b disposed over the gate dielectric layer 124c on the substrate 122 .

As shown in the cross-sectional view 600 of FIG. 6 , a first dielectric layer 602 , a first barrier layer 603 and a second dielectric layer 604 may be formed over the interconnect structure 130 . In some embodiments, the first dielectric layer 602, the first barrier layer 603, and the second dielectric layer 604 may comprise the same material. In other embodiments, at least the first barrier layer 603 may comprise a different material than the first dielectric layer 602 and/or the second dielectric layer 604 . The first barrier layer 603 may include a dielectric material, which may also serve as an etch stop layer to protect the interconnect structure 130 . For example, in some embodiments, the first barrier layer 603 may include nitride (eg, silicon nitride), carbide (eg, silicon carbide), or the like. Additionally, in some embodiments, the first and second dielectric layers 604 may include dielectric materials such as, for example, nitrides (eg, silicon nitride, silicon oxynitride), carbides (eg, such as silicon carbide), oxides (eg, silicon oxide), borosilicate glass (BSG), undoped silicate glass (USG), phosphosilicate glass ( phosphoric silicatc glass (PSG), borophosphosilicate glass (BPSG), low dielectric constant (low-k) oxides (eg, carbon-doped oxides, SiCOH), and the like. In some embodiments, the first dielectric layer and/or the second dielectric layer 604 may comprise the same material as the interconnect dielectric structure 132 . In some embodiments, the first dielectric layer 602 , the first barrier layer 603 and/or the second dielectric layer 604 may each use a deposition process (eg, physical vapor deposition (PVD), chemical vapor deposition Deposition (chemical vapor deposition, CVD), plasma enhanced chemical vapor deposition (plasma enhanced chemical vapor deposition (PE-CVD), atomic layer deposition (atomic layer deposition, ALD), sputtering, etc.).

As shown in the cross-sectional view 700 of FIG. 7, portions of the first dielectric layer 602, the second dielectric layer 604, and the first barrier layer (the first barrier layer 603 of FIG. 6) are removed to define the A cavity 702 separated by a barrier structure 104 . Each cavity 702 may expose a top inner communication hole 136 of the inner communication holes 136 . Cavity 702 may be formed using photolithography and removal (eg, etching) processes. In some embodiments, each cavity 702 may have equal widths, wherein the first width w1 is equal to the second width w2 and the third width w3. In other embodiments, at least one of the first width w1 , the second width w2 or the third width w3 is different.

As shown in cross-sectional view 800 of FIG. 8 , conductive material 802 may be deposited over interconnect structure 130 such that conductive material 802 fills the cavity (cavity 702 of FIG. 7 ) middle. In some embodiments, the conductive material 802 includes a metal that is both conductive and light-reflective. For example, in some embodiments, conductive material 802 may comprise aluminum or aluminum copper. The conductive material may be deposited over the interconnect dielectric structure 132 using a deposition process (eg, physical vapor deposition (PVD), chemical vapor deposition (CVD), PE-CVD, atomic layer deposition (ALD), sputtering, etc.) 802. In some embodiments, conductive material 802 overfills the cavity (cavity 702 of FIG. 7 ) such that conductive material 802 has a top surface over second dielectric layer 604 .

As shown in cross-sectional view 900 of FIG. 9, a planarization process (eg, chemical mechanical planarization (CMP)) is performed to remove conductive material (conductive material 802 of FIG. 8) on second dielectric layer 604 the upper part, thereby forming the first reflector electrode 102a, the second reflector electrode 102b and the third reflector electrode 102c. The first reflector electrode 102a may have a first width w1, the second reflector electrode 102b may have a second width w2, and the third reflector electrode 102c may have a third width w3. The first reflector electrode 102a, the second reflector electrode 102b, and the third reflector electrode 102c may have upper surfaces that are substantially coplanar with each other. Furthermore, the first reflector electrode 102a , the second reflector electrode 102b and the third reflector electrode 102c may have upper surfaces that are substantially coplanar with the second dielectric layer 604 . In other embodiments, a planarization process may remove, for example, the second dielectric layer 604 and thus the first reflector electrode 102a, the second reflector electrode 102b, and the third reflector electrode 102c may have the same characteristics as the first barrier structure 104 Substantially coplanar upper surfaces. In some embodiments, the first reflector electrode 102a , the second reflector electrode 102b , and the third reflector electrode 102c may each be coupled to a different one of the plurality of semiconductor devices 124 . In addition, the first Each of the emitter electrode 102a , the second reflector electrode 102b , and the third reflector electrode 102c may be laterally spaced from each other and electrically isolated from each other by the first blocking structure 104 .

In some embodiments, after the planarization process, the first reflector electrode 102a may have a first average surface roughness, the second reflector electrode 102b may have a second average surface roughness, and the third reflector electrode 102c may have a second average surface roughness Has a third average surface roughness. In some embodiments, since each reflector electrode (first reflector electrode 102a, second reflector electrode 102b, third reflector electrode 102c) comprises the same material and uses the same process method (eg, depositing Figure 8 The conductive material 802 and then the planarization process) are formed at the same time, so the first average surface roughness, the second average surface roughness and the third average surface roughness can be substantially equal to each other. Since the reflector electrodes (first reflector electrode 102a, second reflector electrode 102b, third reflector electrode 102c) have the optical function of reflecting light, low average surface roughness is preferred to reduce light scattering upon reflection. In some embodiments, to measure average surface roughness, a roughness measurement tool (eg, a profilometer, atomic force microscopy (AFM), etc.) calculates a mean line along the surface and The deviation between the height of a peak or valley on the surface and the bisector is measured. After measuring a number of deviations at many peaks and valleys across the surface, the average surface roughness is calculated by averaging the many deviations, where the deviation is an absolute value. In other embodiments, surface roughness is quantified by measuring total thickness variation (TTV). The total thickness variation of the layer is the difference between the minimum thickness of the layer and the maximum thickness difference between large thicknesses. The total thickness variation is measured over the entire length of the layer.

As shown in the cross-sectional view 1000 of FIG. 10, a first isolation layer 302 may be formed over the first reflector electrode 102a, the second reflector electrode 102b, and the third reflector electrode 102c. In some embodiments, the first isolation layer 302 may comprise a material having optical properties such that colored light is visible from the surface of the material, and wherein the colored light is dependent on the thickness of the first isolation layer 302 . In some embodiments, the first isolation layer 302 may include, for example, an oxide (eg, aluminum oxide or silicon dioxide). The first isolation layer 302 may have a first thickness t1, and in some embodiments, the first thickness t1 may be in a range, for example, between approximately 200 angstroms and approximately 600 angstroms. In other embodiments, the first thickness t1 may be in a range between approximately 49 angstroms and approximately 51 angstroms, for example. In such other embodiments, since the first isolation layer 302 may be thin (eg, less than 100 angstroms), the first isolation layer 302 may comprise aluminum oxide deposited by atomic layer deposition (ALD) such that The first thickness t1 can be precisely controlled. In some embodiments, the first isolation layer 302 may be formed using a deposition process other than ALD, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), PE-CVD, sputtering. The first isolation layer 302 may directly contact the first reflector electrode 102a, the second reflector electrode 102b and the third reflector electrode 102c.

Additionally, a first conformal masking layer 1004 may be deposited over the first isolation layer 302 . The first conformal shielding layer 1004 may include, for example, titanium, titanium nitride, tantalum, tantalum nitride, silicon nitride, or the like. Accordingly, the first conformal masking layer 1004 may be deposited using a deposition process (eg, physical vapor deposition (PVD), chemical vapor deposition (CVD), PE-CVD, atomic layer deposition (ALD), sputtering, etc.).

In some embodiments, a first conformal oxide layer 1006 may be formed over the first conformal masking layer 1004 . As shown in FIGS. 11 and 12 , the first conformal oxide layer 1006 can be used to more precisely pattern the first conformal masking layer 1004 . However, it should be appreciated that in some embodiments, the first conformal oxide layer 1006 may be omitted. In some embodiments, the first conformal oxide layer 1006 may include an oxide material such as, for example, silicon dioxide, silicon oxynitride, aluminum oxide, and the like. In some embodiments, the first conformal oxide layer 1006 may be formed by using a deposition process (eg, physical vapor deposition (PVD), chemical vapor deposition (CVD), PE-CVD, atomic layer deposition (ALD), sputtering shot, etc.) to form.

As shown in cross-sectional view 1100 of FIG. 11 , a first conformal oxide layer (first conformal oxide layer 1006 of FIG. 10 ) may be selectively patterned to form over first conformal masking layer 1004 A first oxide layer 1106 . The first oxide layer 1106 is formed to directly overlie the first reflector electrode 102a, but not the second reflector electrode 102b or the third reflector electrode 102c. Furthermore, in some embodiments, the first oxide layer 1106 completely overlies the first reflector electrode 102a, and thus, the first oxide layer 1106 can have a first oxide layer approximately equal to or greater than the first reflector electrode 102a The width of width w1.

In some embodiments, the first oxide layer 1106 may be formed by, for example, a photolithography/etch process or some other suitable process. In some embodiments, a dry etching process can be used to form the first oxide layer 1106, and the first conformal masking layer 1004 can block the passage of ions during the dry etching process, thereby protecting the underlying first isolation layer 302 and the first isolation layer 302. a reflector electrode 102a, a second reflector electrode 102b and a second reflector electrode 102b The triple reflector electrode 102c is protected from damage due to dry etching.

As shown in cross-sectional view 1200 of FIG. 12 , portions of the first conformal masking layer (first conformal masking layer 1004 ) that are not covered by first oxide layer 1106 may be removed to form first masking layer 1204 . Thus, in some embodiments, the first oxide layer 1106 acts as a mask to form the first masking layer 1204 . In some embodiments, portions of the first conformal masking layer (first conformal masking layer 1004) are removed using a wet etch process. The wet etch process may use a wet etchant including, for example, hydrogen peroxide. The wet etchant used in the wet etching process does not remove or affect the first isolation layer 302, the second reflector electrode 102b and the third reflector electrode 102c. Therefore, during the formation of the first oxide layer 1106 and the first shielding layer 1204, the first isolation layer 302, the second reflector electrode 102b, and the third reflector electrode 102c may remain substantially unchanged. If dry etching is used, ions from the dry etching can pass through the first isolation layer 302 and impinge on the second reflector electrode 102b and the third reflector electrode 102c. This may result in damage (eg, compositional defects, structural defects, etc.) to the first isolation layer 302, the second reflector electrode 102b, and the third reflector electrode 102c. Such damage may in turn lead to light scattering and thus negatively impact the reliability of the display device. In some embodiments, the first shielding layer 1204 may have curved outer sidewalls 1204s due to the lateral effect of the wet etching process.

As shown in the cross-sectional view 1300 of FIG. 13 , a second isolation layer 304 may be formed over the first isolation layer 302 and the first shielding layer 1204 . In some embodiments, the second isolation layer 304 may comprise the same or a different material than the first isolation layer 302 . In some embodiments, the second isolation layer 304 may include, for example, an oxide (eg, aluminum oxide or silica).

The second isolation layer 304 may have a fourth thickness t4, and in some embodiments, the fourth thickness t4 may be in a range, for example, between approximately 200 angstroms and approximately 800 angstroms. In some other embodiments, the fourth thickness t4 may be in a range between approximately 800 angstroms and approximately 1000 angstroms, for example. In some embodiments, the fourth thickness t4 is less than, greater than, or approximately equal to the first thickness t1 of the first isolation layer 302 . For example, in the cross-sectional view 1300, the fourth thickness t4 is greater than the first thickness t1. The second isolation layer 304 may be formed using a deposition process (eg, physical vapor deposition (PVD), chemical vapor deposition (CVD), PE-CVD, atomic layer deposition (ALD), sputtering, etc.). The second isolation layer 304 may directly contact the first isolation layer 302 . In some embodiments, if the first isolation layer 302 and the second isolation layer 304 comprise the same material, the interface between the first isolation layer 302 and the second isolation layer 304 may be indistinguishable.

As shown in the cross-sectional view 1400 of FIG. 14 , a second conformal masking layer 1402 may be formed over the second isolation layer 304 . In some embodiments, the second conformal masking layer 1402 may comprise the same material as the first conformal masking layer (the first conformal masking layer 1004 of FIG. 10 ), and may use the same material as the first conformal masking layer ( FIG. 10 ). 10) of the first conformal masking layer 1004) is deposited by the same deposition process. Additionally, in some embodiments, a second conformal oxide layer 1404 may be deposited over the second conformal masking layer 1402 . In some embodiments, the second conformal oxide layer 1404 may comprise the same material as the first conformal oxide layer (first conformal oxide layer 1006 of FIG. 10 ), and may use the same material as the first conformal oxide layer The same deposition process is used for the material layer (the first conformal oxide layer 1006 of FIG. 10 ).

As shown in cross-sectional view 1500 of FIG. 15, a second conformal oxide layer (second conformal oxide layer 1404 of FIG. 14) and a second conformal masking layer (second conformal masking layer 1402 of FIG. 14) may be ) is patterned so that the second shielding layer 1502 and the second oxide layer 1504 are directly overlying the second reflector electrode 102b instead of directly overlying the first reflector electrode 102a or the third reflector electrode 102c . The patterning of the second oxide layer 1504 and the second shielding layer 1502 can be performed using the same or similar steps presented in FIGS. 11 and 12 with respect to forming the first oxide layer 1106 disposed over the first shielding layer 1204 conduct. Furthermore, in some embodiments, the second oxide layer 1504 and the second shielding layer 1502 completely overlie the second reflector electrode 102b, and thus, the second oxide layer 1504 and the second shielding layer 1502 may each have A width approximately equal to or greater than the second width w2 of the second reflector electrode 102b. Furthermore, similar to the first isolation layer 302 during the formation of the first shielding layer 1204, in some embodiments the second isolation layer 304 is patterned because the second shielding layer 1502 prevents the passage of ions and is patterned using a wet etch process. It remains substantially unchanged during the formation of the second shielding layer 1502 .

As shown in the cross-sectional view 1600 of FIG. 16 , a third isolation layer 306 may be formed over the second isolation layer 304 and the second shielding layer 1502 . In some embodiments, the third isolation layer 306 may comprise the same or a different material than the first isolation layer 302 and/or the second isolation layer 304 . In some embodiments, the third isolation layer 306 may include, for example, an oxide (eg, aluminum oxide or silicon dioxide).

The third isolation layer 306 may have a fifth thickness t5, and in some embodiments, the fifth thickness t5 may be in a range, for example, between approximately 200 angstroms and approximately 1100 angstroms. In some other embodiments, the fifth thickness t5 may be in a range between approximately 1100 angstroms and approximately 1300 angstroms, for example. In some embodiments, the fifth thickness t5 is less than, greater than, or approximately equal to the fourth thickness t4 of the second isolation layer 304 . For example, in the cross-sectional view 1600, the fifth thickness t5 is approximately equal to the fourth thickness t4. The third isolation layer 306 may be formed using a deposition process (eg, physical vapor deposition (PVD), chemical vapor deposition (CVD), PE-CVD, atomic layer deposition (ALD), sputtering, etc.). The third isolation layer 306 may directly contact the second isolation layer 304 . In some embodiments, if the second isolation layer 304 and the third isolation layer 306 comprise the same material, the interface between the second isolation layer 304 and the third isolation layer 306 may be indistinguishable.

As shown in the cross-sectional view 1700 of FIG. 17 , a third conformal masking layer 1702 may be formed over the third isolation layer 306 . In some embodiments, the third conformal masking layer 1702 may comprise the same material as the first conformal masking layer (the first conformal masking layer 1004 of FIG. 10 ), and may use the same material as the first conformal masking layer ( FIG. 10 ). 10) of the first conformal masking layer 1004) is deposited by the same deposition process. Additionally, in some embodiments, a third conformal oxide layer 1704 may be deposited over the third conformal masking layer 1702 . In some embodiments, the third conformal oxide layer 1704 may comprise the same material as the first conformal oxide layer (first conformal oxide layer 1006 of FIG. 10 ), and may use the same material as the first conformal oxide layer The same deposition process is used for the material layer (the first conformal oxide layer 1006 of FIG. 10 ).

As shown in cross-sectional view 1800 of FIG. 18, a third conformal oxide layer (third conformal oxide layer 1704 of FIG. 17) and a third conformal masking layer (third conformal masking layer 1702 of FIG. 17) may be ) is patterned so that the third shielding layer 1802 and the third The oxide layer 1804 is directly overlying the third reflector electrode 102c and not directly overlying the second reflector electrode 102b or the third reflector electrode 102c. The patterning of the third oxide layer 1804 and the third shielding layer 1802 can be performed using the same or similar steps presented in FIGS. 11 and 12 with respect to forming the first oxide layer 1106 disposed over the first shielding layer 1204 conduct. Furthermore, in some embodiments, the third oxide layer 1804 and the third shielding layer 1802 completely overlie the third reflector electrode 102c, and thus, the third oxide layer 1804 and the third shielding layer 1802 may each have A width approximately equal to or greater than the third width w3 of the third reflector electrode 102c. Furthermore, similar to the first isolation layer 302 during the formation of the first shielding layer 1204, in some embodiments the third isolation layer 306 is because the third shielding layer 1802 prevents the passage of ions and is patterned using a wet etch process. It remains substantially unchanged during the formation of the third shielding layer 1802 .

As shown in cross-sectional views 1900A-1900C of FIGS. 19A-19C , a first removal process 1902 is performed to remove the first isolation layer 302 , the second isolation layer 304 , and the third isolation layer 306 that are not masked by the first The part covered by the layer 1204 , the second shielding layer 1502 and the third shielding layer 1802 . Cross-sectional view 1900A, cross-sectional view 1900B, and cross-sectional view 1900C of FIGS. 19A, 19B, and 19C illustrate the first removal process 1902 at a first time, a second time, and a third time, respectively, where the second time is after the first time , and the third time is after the second time.

During the first time, as shown in the cross-sectional view 1900A of FIG. 19A, the third isolation layer 306 that is not covered by the third masking layer 1802 is removed. In some embodiments, the first removal process 1902 uses a vertical etch. Therefore, in some embodiments, The first removal process 1902 is an etching process using a dry etchant. This dry etchant does not remove the first masking layer 1204, the second masking layer 1502, or the third masking layer 1802. In some embodiments, the first oxide layer 1106 , the second oxide layer 1504 and the third oxide layer 1804 comprise the same material as the first isolation layer 302 , the second isolation layer 304 and/or the third isolation layer 306 . In some embodiments, the first removal process 1902 may partially remove the first oxide layer 1106, the second oxide layer 1504, and the third oxide layer 1804, such that after the first removal process 1902, the first The oxide layer 1106 , the second oxide layer 1504 , and the third oxide layer 1804 may have a higher average surface roughness than before the first removal process 1902 . In other embodiments (not shown), the first removal process 1902 may completely remove the first oxide layer 1106 , the second oxide layer 1504 and the third oxide layer 1804 . However, the first shielding layer 1204, the second shielding layer 1502, and the third shielding layer 1802 cover and protect the underlying first isolation layer 302, second isolation layer 304, and/or third isolation layer 306 from during dry etching ionic influence.

During the second time, as shown in the cross-sectional view 1900B of FIG. 19B , the first removal process 1902 begins to remove the portions of the second isolation layer 304 that are not covered by the second masking layer 1502 and the third masking layer 1802 . In some embodiments, the same dry etchant is used during the first removal process 1902 . In other embodiments, such as if first isolation layer 302, second isolation layer 304, and/or third isolation layer 306 comprise different materials, different dry etchants may be used to effectively remove uncovered or Each of the first isolation layer 302 , the second isolation layer 304 , and the third isolation layer 306 that are not directly under the first shielding layer 1204 , the second shielding layer 1502 , or the third shielding layer 1802 . For example, in some embodiments, for the oxide-based first isolation layer 302, the second isolation layer 304 and/or the third isolation layer 306, a dry etchant based on carbon fluoride can be used, while in some other embodiments, for the first isolation layer 302, the second isolation layer of the nitride system 304 and/or the third isolation layer 306, a dry etchant based on carbon hydrogen fluoride can be used. It should be understood that other dry etchants are also within the scope of the present disclosure.

During a third time, as shown in cross-sectional view 1900C of FIG. 19C , the first removal process 1902 ends and the first isolation layer 302 , the second isolation layer 304 , and the third isolation layer 306 that are not directly on the first shield are removed The portion below layer 1204 , the second shielding layer 1502 or the third shielding layer 1802 . The first removal process 1902 may be stopped at the second dielectric layer 604 or at the first barrier structure 104 . Since the first shielding layer 1204, the second shielding layer 1502 and the third shielding layer 1802 completely cover the first reflector electrode 102a, the second reflector electrode 102b and the third reflector electrode 102c, respectively, the first reflector The electrode 102a, the second reflector electrode 102b, and the third reflector electrode 102c are not damaged by the first removal process 1902, and thus maintain the first average surface roughness, the second average surface roughness, and the third average surface roughness, respectively Spend. Therefore, the patterning of the first isolation layer 302, the second isolation layer 304 and the third isolation layer 306 does not damage the first reflector electrode 102a, the second reflector electrode 102b and the third reflector electrode 102c, and the first reflector The optical properties of the reflector electrode 102a, the second reflector electrode 102b, and the third reflector electrode 102c are maintained.

As shown in the cross-sectional view 2000 of FIG. 20, a second removal process may be performed to remove the first masking layer, the second masking layer, and the third masking layer (the first masking layer 1204, the second masking layer 1502, the third shielding layer 1802). Furthermore, in some real In an embodiment, the second removal process also removes the first oxide layer (the first oxide layer 1106 of FIG. 19C ), the second oxide layer (the second oxide layer 1504 of FIG. 19C ), and the third oxide layer (third oxide layer 1804 of FIG. 19C). In some embodiments, the second removal process may include, for example, a dry etching process to remove the first oxide layer (the first oxide layer 1106 of FIG. 19C ), the second oxide layer (the second oxide of FIG. 19C ) layer 1504) and the third oxide layer (the third oxide layer 1804 in FIG. 19C), followed by a wet etching process to remove the first masking layer, the second masking layer and the third masking layer (the first masking layer in FIG. 19C). shielding layer 1204, second shielding layer 1502, third shielding layer 1802). In which, for example, the first oxide layer (the first oxide layer 1106 of FIG. 19C ), the second oxide layer (the second oxide layer 1504 of FIG. 19C ), and the third oxide layer (the third oxide layer of FIG. 19C ) are omitted. oxide layer 1804) or wherein the first oxide layer (first oxide layer 1106 of FIG. 19C) is removed during the first removal process (first removal process 1902 of FIGS. 19A, 19B, 19C) In other embodiments of the dioxide layer (the second oxide layer 1504 of FIG. 19C ) and the third oxide layer (the third oxide layer 1804 of FIG. 19C ), the second removal process may only include removal of The wet etching process of the first shielding layer, the second shielding layer and the third shielding layer (the first shielding layer 1204, the second shielding layer 1502, and the third shielding layer 1802 in FIG. 19C ).

Wet etching is used instead of dry etching to prevent damage to the first isolation layer 302, the second isolation layer 304, and the third isolation layer 306, as well as the first reflector electrode 102a, the second reflector electrode 102b, and the third reflector electrode 102c damage. If a dry etchant is used, ions from dry etching can pass through the first isolation layer 302, the second isolation layer 304 and the third isolation layer 306 to reach the first reflector electrode 102a, respectively The upper surface, the upper surface of the second reflector electrode 102b, and the upper surface of the third reflector electrode 102c. This will damage the crystal structures of the first spacer layer 302, the second spacer layer 304, and the third spacer layer 306, and will increase the upper surfaces of the first reflector electrode 102a, the second reflector electrode 102b, and the third reflector electrode 102c roughness. Crystal damage and/or increased surface damage, in turn, can increase light scattering and reduce the reliability of the display device.

The first isolation layer 302 , the second isolation layer 304 , and the third isolation layer 306 form the isolation structure 106 coupled to the control circuitry 120 . The first portion 106a of the isolation structure 106 includes the first isolation layer 302 . The first portion 106a of the isolation structure 106 has a first thickness t1. The second portion 106b of the isolation structure 106 includes portions of the first isolation layer 302 and the second isolation layer 304 directly overlying the second reflector electrode 102b, respectively. The first isolation layer 302 of the second portion 106b of the isolation structure directly contacts the second reflector electrode 102b. The second portion 106b of the isolation structure 106 has a second thickness t2, in some embodiments, the second thickness t2 is, for example, in a range between approximately 300 angstroms and approximately 1300 angstroms. The second thickness t2 is greater than the first thickness t1 such that the upper surface of the first portion 106a of the isolation structure 106 is lower than the upper surface of the second portion 106b of the isolation structure 106 . The second thickness t2 is equal to the sum of the first thickness t1 and the fourth thickness t4. The third portion 106c of the isolation structure 106 is directly overlying the third reflector electrode 102c, and includes respective portions of the first isolation layer 302, the second isolation layer 304, and the third isolation layer 306. The first isolation layer 302 of the third portion 106c of the isolation structure directly contacts the third reflector electrode 102c. The third portion 106c of the isolation structure 106 has a third thickness t3, which in some embodiments is in a range, eg, between approximately 400 angstroms and approximately 1500 angstroms. The third thickness t3 is equal to the first thickness t1, the fourth thickness t4 and the The sum of the five thicknesses t5. The third thickness t3 may be greater than the second thickness t2 such that the upper surface of the second portion 106b of the isolation structure 106 is lower than the upper surface of the third portion 106c of the isolation structure 106 . The first portion 106a, the second portion 106b, and the third portion 106c of the isolation structure 106 are completely laterally spaced from each other to enable optical isolation.

As shown in cross-sectional view 2100 of FIG. 21 , a first portion 106a, a second portion 106b, and a third portion extending through the interconnect structure are formed over the first portion 106a, the second portion 106b, and the third portion 106c, respectively, of the interconnect structure. The first via structure 108a, the second via structure 108b and the third via structure 108c of the portion 106c are in contact with the first reflector electrode 102a, the second reflector electrode 102b and the third reflector electrode 102c, respectively. In some embodiments, the via structures (first via structure 108a, second via structure 108b, third via structure 108c) may comprise tantalum, titanium, or some other conductive material.

In addition, in some embodiments, a first transparent electrode 112a, a second transparent electrode 112b, and a third transparent electrode 112c may be formed over the first portion 106a, the second portion 106b, and the third portion 106c of the isolation structure 106, respectively. The first transparent electrode 112a may directly contact the first portion 106a of the isolation structure 106 . The second transparent electrode 112b may directly contact the second portion 106b of the isolation structure 106 . The third transparent electrode 112c may directly contact the third portion 106c of the isolation structure 106 . In some embodiments, the transparent electrodes (first transparent electrode 112a, second transparent electrode 112b, third transparent electrode 112c) comprise conductive materials that are also optically transparent, such as, for example, indium tin oxide (ITO) ), fluorine tin oxide (FTO), etc. In some embodiments, the transparent electrodes (the first transparent electrode 112a, the Each of the two transparent electrodes 112b, the third transparent electrode 112c) may have a thickness ranging, for example, between approximately 500 angstroms and approximately 3000 angstroms.

In some embodiments, the first optical emitter structure 110a, the second optical emitter structure 110b and the third optical emitter may be formed on the first transparent electrode 112a, the second transparent electrode 112b and the third transparent electrode 112c, respectively Structure 110c. In some embodiments, the optical emitter structures (first optical emitter structure 110a, second optical emitter structure 110b, third optical emitter structure 110c) may be or may include organic light emitting diodes (OLEDs) or some Other suitable light generating devices. In some embodiments, each of the optical emitter structures (first optical emitter structure 110a, second optical emitter structure 110b, third optical emitter structure 110c) may have between, eg, approximately 500 angstroms and approximately thickness in the range between 3000 angstroms.

In some embodiments, the second barrier structure 114 is formed to connect the transparent electrodes (the first transparent electrode 112a, the second transparent electrode 112b, the third transparent electrode 112c) with the optical emitter structures (the first optical emitter structure 110a, the third transparent electrode 112c) The two optical emitter structures 110b and the third optical emitter structure 110c) are separated to define the first pixel region 101a, the second pixel region 101b and the third pixel region 101c. In addition, the second blocking structure 114 may completely separate the first portion 106a , the second portion 106b and the third portion 106c of the isolation structure 106 . It should be understood that the display device may include an array of pixel regions, and may include more than the first pixel region 101a, the second pixel region 101b, and the third pixel region 101c. Some of the second barrier structures 114 may directly overlie the first barrier structures 104 , and the second barrier structures 114 may include elements for connecting the pixel regions (the first pixel region 101 a , the second pixel region 101 a , the second pixel region 101 a , the second pixel region 101 a The pixel area 101b and the third pixel area 101c) are mutually Dielectric materials for electrical and optical isolation. For example, the second blocking structure 114 may include nitride (eg, silicon nitride, silicon oxynitride), oxide (eg, silicon oxide), and the like. For example, in some other embodiments, the second barrier structure 114 may comprise a multilayer film stack of silicon nitride and silicon oxide. Furthermore, in some embodiments, the second barrier structure 114 may comprise the same material as the isolation structure 106 , the first barrier structure 104 , and/or the interconnect dielectric structure 132 . In other embodiments, the second barrier structure 114 may comprise a different material than the isolation structure 106 , the first barrier structure 104 , and/or the interconnect dielectric structure 132 .

It should be understood that through-hole structures (the first through-hole structure 108a, the second through-hole structure 108b, the third through-hole structure 108c), the transparent electrodes (the first transparent electrode 112a, the second transparent electrode 112b, the Each of the three transparent electrodes 112c), the optical emitter structures (the first optical emitter structure 110a, the second optical emitter structure 110b, the third optical emitter structure 110c), and the second blocking structure 114, the various Steps include deposition processes (eg, physical vapor deposition (PVD), chemical vapor deposition (CVD), PE-CVD, atomic layer deposition (ALD), sputtering, etc.), removal processes (eg, wet etching, dry etching, chemical mechanical planarization (CMP), etc.) and/or patterning processes (eg, lithography/etching).

Therefore, the display device includes a control circuit system 120 to selectively operate the first pixel area 101a, the second pixel area 101b and the third pixel area 101c. Since the first reflector electrode 102a, the second reflector electrode 102b, and the third reflector electrode 102c are protected by the first masking layer 1204, the second masking layer 1502, and the third masking layer 1802, respectively, from the first removal process ( 19A, 19B, 19C first removal system process 1902), so the control circuitry 120 can selectively operate each of the pixel regions (the first pixel region 101a, the second pixel region 101b, and the third pixel region 101c) in accordance with the isolation thickness (first thickness t1, second thickness t2, third thickness t3) and/or material of each portion (first portion 106a, second portion 106b, third portion 106c) of the structure (isolation structure 106) to reliably emit colored light.

22 illustrates a flowchart of some embodiments of a method 2200 corresponding to FIGS. 5-18, 19A-19C, 20, and 21 .

Although method 2200 is illustrated and described below as a series of acts or events, it should be understood that the illustrated order of these acts or events should not be interpreted in a limiting sense. For example, some actions may be performed in a different order and/or concurrently with other actions or events in addition to those shown and/or described herein. Additionally, not all acts illustrated are required to implement one or more aspects or one or more embodiments described herein. Furthermore, one or more of the actions depicted herein may be performed in one or more separate actions and/or phases.

At act 2202, a first reflector electrode and a second reflector electrode are formed over the interconnect structure. 7-9 illustrate cross-sectional views 700-900 of some embodiments corresponding to act 2202.

At act 2204, a first isolation layer is deposited over the first reflector electrode and the second reflector electrode. FIG. 10 illustrates a cross-sectional view 1000 of some embodiments corresponding to act 2204 .

At act 2206, a first shadow layer is formed over the first reflector electrode such that the first shadow layer directly overlies the first reflector electrode, but not overlying on the second reflector electrode. 10-12 illustrate cross-sectional views 1000-1200 of some embodiments corresponding to act 2206 .

At act 2208, a second isolation layer is deposited over the first isolation layer and over the first masking layer. FIG. 13 illustrates a cross-sectional view 1300 of some embodiments corresponding to act 2208 .

At act 2210, a second shielding layer is formed over the second isolation layer such that the second shielding layer directly overlies the second reflector electrode, but not the first reflector electrode. FIGS. 14 and 15 illustrate cross-sectional views 1400 and 1500 , respectively, of some embodiments corresponding to act 2210 .

At act 2212, a first removal process is performed to remove portions of the first isolation layer and portions of the second isolation layer that are not directly under the first masking layer or the second masking layer. 19A, 19B, and 19C illustrate cross-sectional views 1900A, 1900B, and 1900C, respectively, of some embodiments corresponding to act 2212.

At act 2214, a second removal process is performed to remove the first masking layer and the second masking layer. FIG. 20 illustrates a cross-sectional view 2000 of some embodiments corresponding to act 2214 .

Accordingly, the present disclosure relates to a method of forming an isolation structure that prevents damage to the upper surface of an underlying reflector electrode structure to improve the reliability of a display device.

Accordingly, in some embodiments, the present disclosure relates to a display device comprising: a first reflector electrode; a second reflector electrode spaced from the first reflector electrode; an isolation structure overlying the first reflector electrode and the On the second reflector electrode, the isolation structure includes: a first portion overlying the first reflector electrode and having a first thickness, and a second portion overlying the second reflector electrode , having a second thickness greater than the first thickness and spaced apart from the first portion of the isolation structure; and a first optical emitter structure and a second optical emitter structure overlying the isolation structure, respectively on the first part and the second part. In an embodiment, the display device further includes: a first transparent electrode and a second transparent electrode. A first transparent electrode is arranged between the first portion of the isolation structure and the first optical emitter structure. A second transparent electrode is disposed between the second portion of the isolation structure and the second optical emitter structure, wherein the second transparent electrode is electrically isolated from the first transparent electrode. In an embodiment, the first portion of the isolation structure contacts the first reflector electrode at a first interface, wherein the first portion of the isolation structure contacts the first transparent electrode at a second interface , wherein the first thickness of the first portion of the isolation structure is measured from the first interface to the second interface, wherein the second portion of the isolation structure contacts at a third interface the second reflector electrode, wherein the second portion of the isolation structure contacts the second transparent electrode at a fourth interface, and wherein the second thickness of the second portion of the isolation structure is measured from the third interface to the fourth interface. In an embodiment, a first barrier structure is arranged between the first reflector electrode and the second reflector electrode, wherein a second barrier structure is arranged between the first portion of the isolation structure and the second between the parts, and wherein the second blocking structure directly overlies the first blocking structure. In an embodiment, the second barrier structure includes and the isolation junction Construct different materials. In an embodiment, the first portion of the isolation structure directly contacts the first reflector electrode, and wherein the second portion of the isolation structure directly contacts the second reflector electrode.

In other embodiments, the present disclosure relates to a display device comprising: a first reflector electrode and a second reflector electrode on the interconnection structure; a first isolation layer including spaced apart and on A pair of segments overlying the first reflector electrode and the second reflector electrode; a second isolation layer overlying the first isolation layer and the second reflector electrode, but not on Overlying the first reflector electrode; a first optical emitter structure and a second optical emitter structure, the first optical emitter structure overlying the first isolation layer and the first reflector electrode , the second optical emitter structure is overlying the second isolation layer and the second reflector electrode; and the first conductive structure and the second conductive structure respectively extend from the first reflector electrode to the first optical emitter structure and from the second reflector electrode to the second optical emitter structure, wherein the first conductive structure extends through the first isolation layer, and wherein the A second conductive structure extends through the first isolation layer and the second isolation layer. In an embodiment, a barrier structure separates the first conductive structure from the second conductive structure, and wherein the barrier structure separates the first optical emitter structure from the second optical emitter structure . In an embodiment, the second isolation layer is a different material than the first isolation layer. In an embodiment, the first reflector electrode has a first average surface roughness, and wherein the second reflector electrode has a second average surface roughness approximately equal to the first average surface roughness. In an embodiment, the first isolation layer is larger than the second isolation layer thin layer. In an embodiment, the second isolation layer is the same material as the first isolation layer. In an embodiment, a line extends continuously between the first reflector electrode and the second reflector electrode and between the pair of segments of the first spacer layer, wherein the line is not connected to the first reflector electrode and the second reflector electrode or the first spacer and the second spacer intersect, and wherein the line is orthogonal to the upper surface of the first reflector electrode extends in the first direction.

In still other embodiments, the present disclosure relates to a method of forming a display device, the method comprising: forming a first reflector electrode and a second reflector electrode over an interconnect structure, wherein the first reflector electrode laterally spaced from the second reflector electrode; depositing a first isolation layer over the first reflector electrode and the second reflector electrode; forming a direct overlying layer on the first reflector electrode a first shielding layer on the first shielding layer; a second shielding layer is deposited on the first shielding layer and on the first shielding layer; a second shielding layer is formed on the second shielding layer, and the first shielding layer is formed Two shielding layers are directly overlying the second reflector electrode; a first removal process is performed to remove the first isolation layer and the second isolation layer not directly located on the first shielding layer or a plurality of portions under the second shielding layer; and performing a second removal process to remove the first shielding layer and the second shielding layer. In an embodiment, the first removal process includes dry etching, and wherein the second removal process includes wet etching. In an embodiment, the first isolation layer and the second isolation layer are the same material. In an embodiment, the forming the first shielding layer comprises: depositing a first conformal shielding layer over the first isolation layer; depositing a first conformal oxide over the first conformal shielding layer layer; the first conformal using a dry etchant patterning an oxide layer to form a first oxide layer directly overlying the first reflector electrode; and masking the first conformal masking layer from the first oxide layer using a wet etchant patterning to form the first shielding layer. In an embodiment, after the first removal process, the first oxide layer has a higher average surface roughness than before the first removal process. In an embodiment, after the second removal process, a first segment of the first isolation layer overlies the first reflector electrode, and a second segment of the first isolation layer overlies On the second reflector electrode, wherein the first segment of the first spacer layer is laterally spaced apart from the second segment of the first spacer layer. In an embodiment, the method further comprises: forming a first transparent electrode over the first segment of the first isolation layer; forming a first transparent electrode over the second segment of the first isolation layer two transparent electrodes; a first optical emitter structure is formed over the first transparent electrode; and a second optical emitter structure is formed over the second transparent electrode.

The foregoing summarizes the features of several embodiments in order that those skilled in the art may better understand the various aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or implementing the embodiments described herein Same advantages. Those skilled in the art should also realize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the present invention .

100: Cutaway view

101a: first pixel area

101b: Second pixel area

101c: The third pixel area

102a: first reflector electrode

102b: Second reflector electrode

102c: Third reflector electrode

104: The first blocking structure

106: Isolation Structure

106a: Part 1

106b: Part II

106c: Part Three

108a: first through hole structure

108b: second via structure

108c: third via structure

110a: First Optical Emitter Structure

110b: Second Optical Emitter Structure

110c: Third Optical Emitter Structure

112a: first transparent electrode

112b: second transparent electrode

112c: third transparent electrode

114: Second blocking structure

120: Control circuit system

122: Base

124: Semiconductor Devices

124a: source/drain region

124b: gate electrode

124c: gate dielectric layer

130: Inline Structure

132: Interconnected Dielectric Structure

134: Internal wiring

136: Internal communication hole

150: First Line

152: Second line

t1: first thickness

t2: second thickness

t3: the third thickness

Claims (10)

A display device comprising: a first reflector electrode; a second reflector electrode separated from the first reflector electrode; a first blocking structure arranged between the first reflector electrode and the second reflector between electrodes, and the first reflector electrode and the second reflector electrode have an upper surface that is substantially coplanar with the upper surface of the first blocking structure; an isolation structure overlies the first reflector On the reflector electrode and the second reflector electrode, the isolation structure includes: a first portion overlying the first reflector electrode and having a first thickness, and a second portion overlying the second reflector electrode a reflector electrode with a second thickness greater than the first thickness and spaced apart from the first portion of the isolation structure; and a first optical emitter structure and a second optical emitter structure, respectively overlying on the first portion and the second portion of the isolation structure. The display device of claim 1, further comprising a second blocking structure, wherein the second blocking structure is disposed between the first portion and the second portion of the isolation structure, and wherein the second blocking structure The blocking structure directly overlies the first blocking structure. The display device of claim 2, wherein the second blocking structure comprises a different material than the isolation structure. A display device, comprising: a first reflector electrode and a second reflector electrode, located on an interconnect structure; a first blocking structure, arranged between the first reflector electrode and the second reflector electrode, and the first reflector electrode and the second reflector electrode have upper surfaces that are substantially coplanar with the upper surface of the first blocking structure; the first isolation layer includes a pair of segments, the pair of segments spaced apart from each other and respectively overlying the first reflector electrode and the second reflector electrode; a second isolation layer overlying the first isolation layer and the second reflector electrode, but not overlying the first reflector electrode; a first optical emitter structure and a second optical emitter structure, the first optical emitter structure overlying the first isolation layer and the first reflector On the reflector electrode, the second optical emitter structure is overlying the second isolation layer and the second reflector electrode; and the first conductive structure and the second conductive structure, respectively, from the first reflector an electrode extends to the first optical emitter structure and from the second reflector electrode to the second optical emitter structure, wherein the first conductive structure extends through the first isolation layer, and wherein The second conductive structure extends through the first isolation layer and the second isolation layer. The display device of claim 4, further comprising a second blocking structure, wherein the second blocking structure directly overlies the first blocking structure, and connects the first optical emitter structure with the first blocking structure. The two optical emitter structures are spaced apart. The display device of claim 4, wherein the first reflector electrode has a first average surface roughness, and wherein the second reflector electrode has a second average surface roughness approximately equal to the first average surface roughness Surface roughness. A method of forming a display device, comprising: forming a first reflector electrode and a second reflector electrode over an interconnect structure, wherein the first reflector electrode and the second reflector electrode are laterally spaced apart, depositing a first isolation layer over the first reflector electrode and the second reflector electrode; forming directly overlying the first reflector electrode but not overlying the second reflector electrode A second shielding layer is deposited on the first shielding layer and on the first shielding layer; a second shielding layer is formed on the second shielding layer, and the second shielding layer is formed on the second shielding layer. The shielding layer is directly overlying the second reflector electrode but not overlying the first reflector electrode; a first removal process is performed to remove the first isolation layer and the second parts of the isolation layer not covered by the first shielding layer or the second shielding layer; and performing a second removal process to remove the first shielding layer and the second shielding layer. The method of claim 7, wherein the first removal process comprises dry etching, and wherein the second removal process comprises wet etching. The method of claim 7, wherein the forming the first masking layer comprises: depositing a first conformal masking layer over the first isolation layer; depositing over the first conformal masking layer a first conformal oxide layer; patterning the first conformal oxide layer using a dry etchant to form a first oxide layer directly overlying the first reflector electrode; and using a wet etchant An etchant patterns the first conformal masking layer according to the first oxide layer to form the first masking layer. The method of claim 7, wherein after the second removal process, the first segment of the first isolation layer overlies the first reflector electrode, and the first segment of the first isolation layer A second segment overlies the second reflector electrode, wherein the first segment of the first isolation layer is laterally spaced apart from the second segment of the first isolation layer.

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