TWI754393B - Electronic device - Google Patents

Abstract

An electronic device includes a substrate, a plurality of transistors and a plurality of drain contact holes. The transistors are disposed on the substrate. Each transistor has a semiconductor, a source and a drain. The drain is electrically connected to the semiconductor through the drain contact holes. A number of the drain contact holes is less than a number of the drains.

Description

electronic device

The present disclosure relates to an electronic device, and more particularly, to an electronic device that can provide better display quality.

Display panels have been widely used in electronic devices such as mobile phones, televisions, monitors, tablet computers, automotive displays, wearable devices, and desktop computers. With the vigorous development of electronic products, the requirements for the display quality of electronic products are getting higher and higher, so that the electronic devices used for display are constantly moving towards light, thin, short, small, frameless and larger or higher resolution display effects Improve.

The present disclosure provides an electronic device with better reliability or better display quality.

The electronic device of the present disclosure includes a substrate, a plurality of transistors, and a plurality of drain contact holes. A plurality of transistors are arranged on the substrate. Each transistor has a semiconductor, a source and a drain. The drain is electrically connected to the semiconductor through a plurality of drain contact holes. The number of the plurality of drain contact holes is smaller than the number of the drain electrodes.

In order to make the above-mentioned features and advantages of the present disclosure more obvious and easy to understand, the following embodiments are given and described in detail in conjunction with the accompanying drawings as follows.

The present disclosure can be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in order to facilitate readers' understanding and to simplify the drawings, the drawings in the present disclosure only depict a part of an electronic device. And specific elements in the drawings are not drawn according to actual scale. In addition, the number and size of each element in the figures are for illustration only, and are not intended to limit the scope of the present disclosure.

In the following description and claims, the words "comprising" and "including" are open-ended words, so they should be interpreted as meaning "including but not limited to...".

It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or directly connected to the other element or layer Hereto another element or layer, or there is an intervening element or layer in between (indirect case). In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present.

Although the terms first, second, third . . . may be used to describe various constituent elements, the constituent elements are not limited by the terms. This term is only used to distinguish a single constituent element from other constituent elements in the specification. The same terms may not be used in the claims, but replaced by first, second, third, . . . in the order in which the elements are recited in the claims. Therefore, in the following description, the first constituent element may be the second constituent element in the claims.

In the text, the terms "about", "approximately", "substantially" and "substantially" usually mean within 10%, or within 5%, or within 3%, or within 2% of a given value or range. within 1%, or within 0.5%. The quantity given here is an approximate quantity, that is, "about", "approximately", "approximately", "approximately", "approximately", "approximately", "approximately", "approximately", "approximately", "approximately", "substantially" and "substantially" may still be implied without the specific description of "about", "approximately", "substantially", "substantially" The meaning of "substantially" and "substantially". Furthermore, the terms "range is from the first value to the second value", "range is between the first value and the second value" means that the range includes the first value, the second value and other values in between.

In some embodiments of the present disclosure, terms related to bonding and connection, such as "connection", "interconnection", etc., unless otherwise defined, may mean that two structures are in direct contact, or may also mean that two structures are not in direct contact, There are other structures located between these two structures. And the terms of joining and connecting can also include the case where both structures are movable, or both structures are fixed. Furthermore, the term "coupled" includes any direct and indirect means of electrical connection.

In the present disclosure, the measurement method of length and width can be measured by using an optical microscope, and the thickness can be measured by a cross-sectional image in an electron microscope, but it is not limited thereto. In addition, any two values or directions used for comparison may have certain errors.

The electronic device of the present disclosure may include, but is not limited to, a display device, an antenna device, a sensing device, a touch display, a curved display, or a free shape display . The electronic device may be a bendable or flexible electronic device. The electronic device may, for example, include light emitting diodes (LEDs), liquid crystals, fluorescence, phosphors, quantum dots (QDs), other suitable display media, or The aforementioned combinations, but not limited thereto. The light-emitting diodes may include, for example, organic light-emitting diodes (OLEDs), inorganic light-emitting diodes (LEDs), sub-millimeter light-emitting diodes (mini LEDs), micro-LEDs Polar body (micro LED) or quantum dot (quantum dot, QD) light emitting diode (QLED, QDLED), or other suitable materials or any combination of the above, but not limited thereto. The display device may include, for example, but not limited to, a tiled display device. The antenna device may be, for example, a liquid crystal antenna, but not limited thereto. The antenna device may include, for example, but not limited to, an antenna splicing device. It should be noted that, the electronic device can be any arrangement and combination of the foregoing, but not limited to this. In addition, the shape of the electronic device may be rectangular, circular, polygonal, a shape with curved edges, or other suitable shapes. The electronic device may have peripheral systems such as a driving system, a control system, a light source system, a shelf system, etc. to support a display device, an antenna device or a splicing device. Hereinafter, the present disclosure will be described with reference to an electronic device, but the present disclosure is not limited thereto.

It should be noted that, in the following embodiments, features in several different embodiments may be replaced, recombined, and mixed to complete other embodiments without departing from the spirit of the present disclosure. As long as the features of the various embodiments do not violate the spirit of the invention or conflict with each other, they can be mixed and matched arbitrarily.

Reference will now be made in detail to the exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and description to refer to the same or like parts.

FIG. 1A is a schematic top view of an electronic device according to an embodiment of the disclosure. FIG. 1B is a schematic cross-sectional view of the electronic device of FIG. 1A along the section line A-A'. For the clarity of the drawings and the convenience of description, FIG. 1A omits illustration of some elements in the electronic device.

1A and 1B at the same time, the electronic device 100 of this embodiment includes a substrate 110 , a plurality of transistors 120 , 121 , 122 , 123 , 124 , and 125 ( FIG. 1A schematically shows six transistors, but not This is limited) and a plurality of drain contact holes 130 (one drain contact hole is schematically shown in FIG. 1A , but not limited to this). In this embodiment, the substrate 110 may include a rigid substrate, a flexible substrate or a combination of the foregoing. For example, the material of the substrate 110 may include glass, quartz, sapphire (sapphire), ceramics, polycarbonate (PC), polyimide (PI), polyethylene terephthalate (polyethylene terephthalate) terephthalate, PET), other suitable substrate materials, or a combination of the foregoing, but not limited thereto.

A plurality of transistors 120 , 121 , 122 , 123 , 124 and 125 are disposed on the substrate 110 . The transistor 120 , the transistor 122 and the transistor 124 are arranged in sequence along the direction X (for example, the extending direction of the scan line SL) and are adjacent to each other, and the transistor 121 , the transistor 123 and the transistor 125 are sequentially arranged along the direction X is arranged and adjacent to each other, the transistors 120 and 121 are sequentially arranged along the direction Y (for example, the extension direction of the data line DL) and are adjacent to each other, and the transistors 122 and 123 are sequentially arranged along the direction Y is arranged and adjacent to each other, and the transistors 124 and 125 are sequentially arranged along the direction Y and adjacent to each other (the adjacent transistors means that the two transistors are the most along the direction X or along the direction No other transistors in Y). In addition, in the top-view schematic diagram of the electronic device 100 in this embodiment (as shown in FIG. 1A ), the electronic device 100 further includes a plurality of sub-pixels P0 , P1 , P2 , P3 , P4 , and P5 . The transistor 120 is set corresponding to the sub-pixel P0, the transistor 121 is set corresponding to the sub-pixel P1, the transistor 122 is set corresponding to the sub-pixel P2, the transistor 123 is set corresponding to the sub-pixel P3, and the transistor 124 is set corresponding to the sub-pixel P4 is set, and the transistor 125 is set corresponding to the sub-pixel P5. For the convenience of description, the following description will take the transistor 120 and the transistor 121 as an example.

In this embodiment, each transistor 120 (or 121) has a semiconductor SE (or SE1), a source SD (or SD1), a drain SD' (or SD1'), a gate GE (or GE1), and a portion the gate insulating layer GI. The portion of the scan line SL overlapping the semiconductor SE may be defined as a gate electrode GE. In the schematic top view of the electronic device 100 of the present embodiment (as shown in FIG. 1A ), the semiconductor SE of the transistor 120 and the semiconductor SE1 of the adjacent transistor 121 in the direction Y are in the same layer, and one end of the semiconductor SE is connected to One end of the semiconductor SE1 is connected together and partially overlaps with the data line DL, the other end of the semiconductor SE has a side SE', the side SE' is located between two adjacent data lines DL, and the extension direction of the side SE' Substantially parallel to the direction X, and the other end of the semiconductor SE1 has a side SE1', the side SE1' is also located between two adjacent data lines DL, and the extension direction of the side SE1' is substantially parallel to the direction X, wherein The side SE' and the side SE1' are separated from each other in the direction Y. Specifically, the side SE' and the side SE1' have a distance D1 in the direction Y, whereby the semiconductor of the present disclosure can form a "C"-like outline. Please refer to the schematic cross-sectional view of the electronic device 100 of the present embodiment (as shown in FIG. 1B ). When the side SE' of the semiconductor SE and the side SE1' of the semiconductor SE1 are separated from each other, a part of the buffer layer is exposed. 140. In this embodiment, the materials of the semiconductors SE and SE1 may include amorphous silicon, low temperature polysilicon (LTPS), metal oxides (eg, indium gallium zinc oxide IGZO), other suitable materials, or a combination thereof, But not limited to this. In other embodiments, different transistors may include different semiconductor materials, but not limited thereto.

Please continue to refer to the schematic cross-sectional view of the electronic device 100 in this embodiment (as shown in FIG. 1B ). In this embodiment, the gate insulating layer GI is disposed on the semiconductor SE (or SE1 ) and has an opening GIa. The width W1 of the bottom of the opening GIa may be greater than the distance D1 between the other end SE' of the semiconductor SE and the other end SE1' of the semiconductor SE1, so that the opening GIa may expose part of the semiconductor SE (or SE1) and part of the the buffer layer 140. In this embodiment, the width W1 is, for example, the maximum width of the opening GIa measured along the direction Y, and the distance D1 is, for example, the distance between the other end SE' of the semiconductor SE and the other end SE1' of the semiconductor SE1 along the direction Y The maximum distance to measure.

In this embodiment, the gate GE of the transistor 120 and the gate GE1 of the transistor 121 are respectively disposed on the gate insulating layer GI. The source SD and the drain SD' of the transistor 120 are respectively disposed on the gate GE, and the source SD1 and the drain SD1' of the transistor 121 are also respectively disposed on the gate GE1. In this embodiment, the materials of the source electrodes SD1, SD1 and/or the drain electrodes SD', SD1' may include transparent conductive materials or non-transparent conductive materials, such as indium tin oxide, indium zinc oxide, indium oxide, zinc oxide , tin oxide, metal materials (eg, aluminum, molybdenum, copper, silver, etc.), other suitable materials, or combinations thereof, but not limited thereto.

In the schematic top view of the electronic device 100 in this embodiment (as shown in FIG. 1A ), the electronic device 100 further includes a scan line SL and a data line DL. The scan lines SL and the data lines DL are disposed on the substrate 110 . The scan lines SL generally extend along the direction X, the data lines DL generally extend along the direction Y, and the normal direction of the substrate 110 is the direction Z, wherein the direction X, the direction Y, and the direction Z are different from each other, and the direction X, the direction Y and direction Z are perpendicular to each other. Since the source SD (or SD1) of the transistor 120 (or 121) can be electrically connected to the data line DL, and the gate GE (or GE1) of the transistor 120 (or 121) can be electrically connected to the scan line SL, Therefore, the transistor 120 (or 121 ) can be electrically connected to the data line DL and the scan line SL. In addition, in the above schematic diagram of this embodiment, a part of the data line DL extends into the drain contact hole 130 , and the width of the data line DL extending into the drain contact hole 130 is W2 , and the other part of the data line DL extends into the drain contact hole 130 . A portion of the width W3 disposed outside the drain contact hole 130 is, for example, less than or equal to the width W2, but not limited thereto. In some embodiments, the width W3 may be greater than the width W2 by a factor of 2. In some embodiments, width W3 may be greater than width W2 by a factor of 1.7. In some embodiments, the width W3 may be greater than the width W2 by a factor of 1.3. In this embodiment, the width W2 is, for example, the maximum width of the data line DL in the drain contact hole 130 measured along the direction X from one side of the data line DL to the other side, and the width W3 is, for example, in the drain contact hole 130. The maximum width of the data line DL outside the pole contact hole 130 is measured along the direction X from one side of the data line DL to the other side.

1A and FIG. 1B, in this embodiment, the electronic device 100 further includes a buffer layer 140, a shielding layer 141, insulating layers 142, 142', an insulating layer 143, a dielectric layer 150, a transfer pad 160, 160', an insulating layer 170, a pixel electrode (not shown), a common electrode (not shown), and an interlayer insulating layer (not shown) between the pixel electrode and the common electrode. The buffer layer 140, the insulating layers 142, 142', the insulating layer 143, the dielectric layer 150, and the insulating layer 170 may be single-layer or multi-layer structures, and may include organic materials, inorganic materials, or a combination of the foregoing, but not This is limited. In this embodiment, the material of the shielding layer 141 may be, for example, a metal material or other light shielding materials. In some embodiments, the electronic device may not be provided with a shielding layer (not shown).

In this embodiment, the shielding layer 141 is disposed on the substrate 110 , the buffer layer 140 is disposed on the shielding layer 141 , and the shielding layer 141 and the buffer layer 140 are disposed between the transistors 120 , 121 and the substrate 110 . The insulating layer 142 (or 142') is disposed between the gate electrode GE (or GE1) and the gate insulating layer GI, and the insulating layer 142 (or 142') is disposed corresponding to the gate electrode GE (or GE1).

In this embodiment, the dielectric layer 150 is disposed between the drain electrodes SD', SD1' and the gate insulating layer GI to cover the gate electrodes GE, GE1 and the gate insulating layer GI. The dielectric layer 150 has openings 151 . The opening 151 communicates with the opening GIa to form the drain contact hole 130 and expose part of the semiconductors SE, SE1 and part of the buffer layer 140 . Therefore, in the present embodiment, in the extending direction of the data line DL (ie, the direction Y), the transistor 120 and the transistor 121 (or the transistor 122 and the transistor 123, or the transistor 124 and the transistor 125) are in phase with each other Adjacent, and the drain contact hole 130 of the electronic device 100 is disposed between two adjacent transistors 120 , 121 (or transistors 122 , 123 , or transistors 124 , 125 ).

In this embodiment, the source electrode SD (or SD1) and the drain electrode SD' (or SD1') may be disposed on the dielectric layer 150, respectively. The source electrode SD of the transistor 120 and the source electrode SD1 of the transistor 121 can also be disposed in the drain contact hole 130 , so that the source electrode SD and the source electrode SD1 can be respectively contacted and electrically connected to the drain contact hole 130 . Semiconductor SE and Semiconductor SE1. In addition, the drain SD' of the transistor 120 and the drain SD1' of the transistor 121 can also be disposed in the drain contact hole 130, so that the drain SD' and the drain SD1' can be respectively contacted and electrically connected to the drain The semiconductor SE and the semiconductor SE1 in the pole contact hole 130 . That is, the source SD of the transistor 120 and the source SD1 of the transistor 121 can be electrically connected to the semiconductor SE and the semiconductor SE1 through the drain contact hole 130 respectively, and the drain SD' of the transistor 120 and the transistor 121 The drain SD1 ′ can also be electrically connected to the semiconductor SE and the semiconductor SE1 through the drain contact hole 130 , respectively. That is, the source electrode SD and the drain electrode SD1' of the transistor 120 may share the same drain contact hole 130 with the source electrode SD1 and the drain electrode SD1' of the transistor 121 adjacent in the direction Y.

In this embodiment, the drain contact hole of the electronic device is defined as a contact hole as long as the drain of the transistor can be contacted and electrically connected to the semiconductor. Therefore, even though there are other electrodes (eg, source electrodes) in the contact hole that can contact and be electrically connected to the semiconductor through the contact hole, the contact hole is still defined as a drain contact hole.

In addition, similar to the case of the transistor 120 and the transistor 121, the source SD2 of the transistor 122 and the source SD3 of the transistor 123 can also be electrically connected to the semiconductor SE2 and the semiconductor SE3 through the drain contact hole 130, respectively. The transistor 122 The drain SD2' of the transistor 123 and the drain SD3' of the transistor 123 can also be electrically connected to the semiconductor SE2 and the semiconductor SE3 through the drain contact hole 130, respectively, and the source SD4 of the transistor 124 and the source SD5 of the transistor 125 can also be They are electrically connected to the semiconductor SE4 and the semiconductor SE5 through the drain contact hole 130 respectively, and the drain SD4 ′ of the transistor 124 and the drain SD5 ′ of the transistor 125 can also be electrically connected to the semiconductor SE4 through the drain contact hole 130 respectively. with Semiconductor SE5. That is, the source SD and the drain SD' of the transistor 120 may also share the same drain contact hole 130 with the source SD2 and the drain SD2' of the transistor 122 adjacent in the direction X. Thereby, the source SD and drain SD' of the transistor 120 in the sub-pixel P0, the source SD1 and the drain SD1' of the transistor 121 in the sub-pixel P1, and the source of the transistor 122 in the sub-pixel P2 The electrode SD2 and the drain SD2', the source SD3 and the drain SD3' of the transistor 123 in the sub-pixel P3, the source SD4 and the drain SD4' of the transistor 124 in the sub-pixel P4, and the sub-pixel P5. Both the source SD5 and the drain SD5 ′ of the transistor 125 share the same drain contact hole 130 and are electrically connected to the corresponding semiconductors SE, SE1 , SE2 , SE3 , SE4 and SE5 .

Therefore, in this embodiment, the drains SD', SD1', SD1', SD2 ′, SD3 ′, SD4 ′, SD5 ′ and the source electrodes SD, SD1 , SD2 , SD3 , SD4 , SD5 may share one drain contact hole 130 among a plurality of drain contact holes (not shown). Therefore, the number of the drain contact holes 130 can be made smaller than the number of the drains SD', SD1', SD2', SD3', SD4', SD5' (or the number of the sources SD, SD1, SD2, SD3, SD4, SD5) number), to avoid electronic devices (such as high-resolution display devices, but not limited to this) due to the excessive number of contact holes, which may cause the topography in the contact holes to be steep, which may cause the subsequent formation of the stack. The risk of cracking is improved, thereby improving the layout of metal lines and thin film transistor cells in the display panel.

In this embodiment, the insulating layer 143 is disposed on the transistors 120 and 121 to cover the source electrodes SD, SD1 , the drain electrodes SD', SD1' and the dielectric layer 150 . The insulating layer 143 is disposed between the transfer pads 160, 160' and the drain electrodes SD', SD1'. The insulating layer 143 may also be disposed in the drain contact hole 130 to cover the drain electrodes SD', SD1' and the buffer layer 140 at the portion exposed by the opening GIa of the gate insulating layer GI. In addition, the insulating layer 143 has a first opening 1431 and a second opening 1432 to expose part of the drain electrode SD' and part of the drain electrode SD1', respectively.

In this embodiment, the transfer pad 160 and the transfer pad 160' are disposed corresponding to the drain electrode SD' and the drain electrode SD1', respectively. Specifically, the transfer pads 160 and 160' are disposed on the insulating layer 143 and in the drain contact hole 130. The transfer pad 160 can also be disposed in the first opening 1431 of the insulating layer 143 , so that the connecting pad 160 can be electrically connected to the drain SD' through the first opening 1431 of the insulating layer 143 . The transfer pad 160' can also be disposed in the second opening 1432 of the insulating layer 143, so that the connecting pad 160' can be electrically connected to the drain electrode SD1' through the second opening 1432 of the insulating layer 143. In the drain contact hole 130, the transfer pad 160 and the transfer pad 160' are separated from each other to expose a part of the insulating layer 143. In this embodiment, the material of the transfer pads 160 and 160' may also include a metal material or a transparent conductive material. The metal material may include, but is not limited to, molybdenum, aluminum, titanium, copper, other suitable metals, or alloys or combinations of the above materials. The transparent conductive material may include, but not limited to, indium tin oxide or indium zinc oxide.

In this embodiment, the insulating layer 170 is disposed on the transfer pads 160 and 160' and in the drain contact hole 130. In the drain contact hole 130, the insulating layer 170 may cover the via pads 160, 160' and the insulating layer 143 of the part exposed by the via pads 160, 160'. The insulating layer 170 has a third opening 171 and a fourth opening 172 to expose part of the transfer pad 160 and part of the transfer pad 160', respectively. In addition, in the top view of the electronic device 100 (as shown in FIG. 1A ), the third opening 171 of the insulating layer 170 and the drain contact hole 130 are separated from each other by a distance D2 , and the fourth opening 172 of the insulating layer 170 Also separated from the drain contact hole 130 by a distance D3. In detail, in the upper view of this embodiment (as shown in FIG. 1A ), the distance D2 is, for example, the edge between the side 171 a of the third opening 171 and the side 130 a of the drain contact hole 130 . The maximum distance measured along the direction Y, the distance D3 is, for example, the maximum distance measured along the direction Y between one side 172b of the fourth opening 172 and the other side 130b of the drain contact hole 130 , wherein the extension directions of the side 171a and the side 172b are actually parallel to the direction X (ie, the extension direction of the parallel scan line SL), and the side 171a and the side 172b are closest to each other.

In addition, in this embodiment, the orthographic projection of the third opening 171 (or the fourth opening 172 ) of the insulating layer 170 on the normal direction of the substrate 110 (ie, the direction Z) does not overlap the drain contact hole 130 on the Orthographic projection on the normal direction of the substrate 110 . Specifically, the third opening 171 of the insulating layer 170 has a sidewall 171 a adjacent to the drain contact hole 130 , the fourth opening 172 of the insulating layer 170 has a sidewall 172 b adjacent to the drain contact hole 130 , and the drain contact hole 130 There is a side wall 130 a adjacent to the third opening 171 and a side wall 130 b adjacent to the fourth opening 172 . The orthographic projection of the sidewall 171a of the third opening 171 on the normal direction of the substrate 110 (ie, the direction Z) does not overlap the orthographic projection of the sidewall 130a of the drain contact hole 130 on the normal direction of the substrate 110, and The orthographic projection of the sidewall 172b of the fourth opening 172 on the normal direction of the substrate 110 does not overlap the orthographic projection of the sidewall 130b of the drain contact hole 130 on the normal direction of the substrate 110 .

In this embodiment, since the third opening 171 (or the fourth opening 172 ) of the insulating layer 170 does not overlap the drain contact hole 130 and the third opening 171 (or the fourth opening 172 ) of the insulating layer 170 The drain contact hole 130 is separated from each other and has a distance D2 (or a distance D3), and the orthographic projection of the sidewall 171a of the third opening 171 (or the sidewall 172b of the fourth opening 172 ) in the direction Z does not overlap with the drain The orthographic projection of the sidewall 130a (or the sidewall 130b) of the contact hole 130 on the direction Z, thus providing a relatively flat topography to avoid the subsequent interlayer insulation disposed on the insulating layer 170 and between the pixel electrode and the common electrode The layers (not shown) are cracked, thereby avoiding the risk of short circuits due to the cracking of the interlayer insulating layer and the contact between the pixel electrode and the common electrode.

Although in the top view of the electronic device 100 of the present embodiment, the third opening 171 (or the fourth opening 172 ) of the insulating layer 170 and the drain contact hole 130 are separated from each other, but not limited thereto. In some embodiments, the third opening 171 (or the fourth opening 172 ) of the insulating layer 170 may also partially overlap with the drain contact hole 130 (as shown in FIG. 5A and FIG. 5B ), as long as the third opening is made The orthographic projection of the sidewall 171a of the hole 171 (or the sidewall 172b of the fourth opening 172 ) in the direction Z may not overlap the orthographic projection of the sidewall 130a (or the sidewall 130b ) of the drain contact hole 130 in the direction Z.

Although in the top view of the electronic device 100 in this embodiment, the source SD and the drain SD' of the transistor 120 may share the same drain with the source SD1 and the drain SD1' of the transistor 121 adjacent in the direction Y contact hole 130, and the source electrode SD and drain electrode SD' of the transistor 120 can also share the same drain contact hole 130 with the source electrode SD2 and drain electrode SD2' of the transistor 122 adjacent in the direction X, but this The disclosure does not limit the coverage of the drain contact holes, as long as the number of the drain contact holes in the electronic device can be smaller than the number of the drain holes. That is to say, in some embodiments, the coverage of the drain contact hole may only allow the source and drain electrodes of two adjacent transistors in the direction Y to be shared, as shown in FIG. 3 and FIG. 4 . In some embodiments, the coverage of the drain contact hole may only be shared by the drains of two adjacent transistors in the direction Y, as shown in FIG. 2 .

In addition, in the electronic device 100 of this embodiment, in the direction Y, the pixel electrodes (not shown) in any two adjacent sub-pixels P0, P1 (or sub-pixels P2, P3, or sub-pixels P4, P5) For example, it is configured in a back-to-back manner. The so-called back-to-back configuration in the present disclosure refers to the configuration mode in which the source and drain electrodes of the transistors of two adjacent sub-pixels are shared in the direction Y, but Not limited to this.

In short, in the electronic device 100 of the disclosed embodiment, the drain contact hole 130 is disposed on two adjacent transistors 120 and 121 (or the transistors 122 and 123 , or the transistors 124 and 125 ) Between the two adjacent transistors 120, 121 (or transistors 122, 123, or transistors 124, 125) drain SD', SD1' (or drain SD2', SD3', or drain SD', SD1' (or drain SD2', SD3', or drain The electrodes SD4', SD5') are electrically connected to their corresponding semiconductors SE, SE1 (or the semiconductors SE2, SE3, or the semiconductors SE4, SE5) through the same drain contact hole 130, thus increasing the number of the drain contact holes 130 Can be smaller than the number of drains SD', SD1', SD2', SD3', SD4', SD5'. In this way, it can be avoided that the electronic device 100 (such as a high-resolution display device, but not limited thereto) has a steep topography in the contact hole due to the excessive number of contact holes, which may cause the subsequent formation of the stack. There is a risk of rupture. In addition, since the orthographic projection of the sidewall 171a (or sidewall 171a ) of the third opening 171 (or the fourth opening 172 ) adjacent to the drain contact hole 130 on the normal direction (direction Z) of the substrate 110 does not overlap with the drain The contact hole 130 is adjacent to the orthographic projection of the sidewall 130a (or the sidewall 130b ) of the third opening 171 (or the fourth opening 172 ) on the normal direction of the substrate 110 , thereby providing a relatively flat topography to avoid subsequent placement on the insulating The interlayer insulating layer on the layer 170 and located between the pixel electrode and the common electrode is ruptured, thereby avoiding the risk of short circuit caused by contact between the pixel electrode and the common electrode due to the rupture of the interlayer insulating layer. In this way, the electronic device 100 of the embodiment of the present disclosure can have better reliability or better display quality.

Other examples are listed below for illustration. It must be noted here that the following embodiments use the element numbers and part of the contents of the previous embodiments, wherein the same numbers are used to represent the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, and repeated descriptions in the following embodiments will not be repeated.

FIG. 2 is a schematic top view of an electronic device according to another embodiment of the disclosure. For the sake of clarity and convenience in the description of the drawings, FIG. 2 omits to illustrate some elements in the electronic device, such as scan lines, transition pads, first openings, second openings, third openings and fourth openings. Open holes, but not limited to this. Please refer to FIG. 1A and FIG. 2 at the same time. The electronic device 100 a of this embodiment is substantially similar to the electronic device 100 of FIG. 1A , so the same and similar components in the two embodiments will not be repeated here. The electronic device 100a of this embodiment is different from the electronic device 100 mainly in that the electronic device 100a of this embodiment includes drain contact holes 131, 132, 133 and source contact holes 181, 182, 183, and the drain contact hole 131 , the drain contact hole 132 and the drain contact hole 133 are separated from each other and not connected.

2, in the top view of the electronic device 100a of this embodiment, the source SD1 of the transistor 120 and the source SD1 of the adjacent transistor 121 in the direction Y share the source contact hole 181, The drain SD' of the transistor 120 shares the drain contact hole 131 with the drain SD1' of the transistor 121 adjacent in the direction Y, and the source contact hole 181 and the drain contact hole 131 are separated from each other. The source SD2 of the transistor 122 shares the source contact hole 182 with the source SD3 of the transistor 123 adjacent in the direction Y, and the drain SD2' of the transistor 122 and the drain SD3 of the adjacent transistor 123 in the direction Y ' The drain contact hole 132 is shared, and the source contact hole 182 and the drain contact hole 132 are separated from each other. The source SD4 of the transistor 124 shares the source contact hole 183 with the source SD5 of the transistor 125 adjacent in the direction Y, and the drain SD4 ′ of the transistor 124 and the drain SD5 of the adjacent transistor 125 in the direction Y ' The drain contact hole 133 is shared, and the source contact hole 183 and the drain contact hole 133 are separated from each other.

In this embodiment, due to the drains of at least two transistors 120, 121 (or transistors 122, 123, or transistors 124, 125) of the plurality of transistors 120, 121, 122, 123, 124, 125 SD', SD1' (or drain SD2', SD3', or drain SD4', SD5') may share one drain contact hole 131 (or drain contact hole) among the plurality of drain contact holes 131, 132, 133 hole 132, or drain contact hole 133), thus allowing the drain SD', SD1' (or drain SD2', SD3', or drain SD4', SD5') to pass through the drain contact hole 131 (or drain The contact hole 132, or the drain contact hole 133) is electrically connected to the semiconductors SE, SE1 (or the semiconductors SE2, SE3, or the semiconductors SE4, SE5). Wherein, the number of the plurality of drain contact holes 131, 132, 133 may be smaller than the number of the drain electrodes SD', SD1', SD2', SD3', SD4', SD5'. The number of source contact holes 181 , 182 and 183 may also be smaller than the number of source electrodes SD, SD1 , SD2 , SD3 , SD4 and SD5 .

FIG. 3 is a schematic top view of an electronic device according to another embodiment of the disclosure. For the sake of clarity and convenience in the description of the drawings, FIG. 3 omits to illustrate some elements in the electronic device, such as scan lines, transition pads, first openings, second openings, third openings and fourth openings. Open holes, but not limited to this. Please refer to FIG. 1A and FIG. 3 at the same time, the electronic device 100b of this embodiment is substantially similar to the electronic device 100 of FIG. 1A , so the same and similar components in the two embodiments will not be repeated here. The electronic device 100b of this embodiment is different from the electronic device 100 mainly in that the electronic device 100b of this embodiment includes drain contact holes 131b, 132b, 133b, and the drain contact hole 131b, the drain contact hole 132b and the drain The contact holes 133b are separated from each other and are not connected.

3 , in the top view of the electronic device 100b of this embodiment, the source SD and drain SD' of the transistor 120 may be connected to the source SD1 and the drain SD' of the transistor 121 adjacent in the direction Y The drains SD1' share the drain contact hole 131b. The source electrode SD2 and the drain electrode SD2' of the transistor 122 may share the drain contact hole 132b with the source electrode SD3 and the drain electrode SD3' of the transistor 123 adjacent in the direction Y. The source SD4 and the drain SD4' of the transistor 124 may share the drain contact hole 133b with the source SD5 and the drain SD5' of the transistor 125 adjacent in the direction Y.

In this embodiment, due to the drains of at least two transistors 120, 121 (or transistors 122, 123, or transistors 124, 125) of the plurality of transistors 120, 121, 122, 123, 124, 125 SD', SD1' (or drain SD2', SD3', or drain SD4', SD5') and source SD, SD1 (or source SD2, SD3, or source SD4, SD5) can share multiple drains One of the drain contact holes 131b (or the drain contact hole 132b, or the drain contact hole 133b) among the electrode contact holes 131b, 132b, 133b, thereby allowing the drains SD', SD1' (or the drains SD2', SD3' , or the drain SD4', SD5') can be electrically connected to the semiconductor SE, SE1 (or the semiconductor SE2, SE3, or the semiconductor SE4) through the drain contact hole 131b (or the drain contact hole 132b, or the drain contact hole 133b) , SE5). The number of the plurality of drain contact holes 131b, 132b, 133b may be smaller than the number of the drains SD', SD1', SD2', SD3', SD4', SD5', and the plurality of drain contact holes 131b, 132b, The number of 133b may also be smaller than the number of source electrodes SD, SD1, SD2, SD3, SD4, and SD5.

In addition, in the top view of the electronic device 100b of this embodiment, although the outlines of the drain contact holes 131b, 132b, and 133b are quadrilaterals, the present disclosure does not limit the outlines of the drain contact holes. That is to say, in some embodiments, the contour of the drain contact hole can also be, for example, a C-shaped (as shown in FIG. 4 ) or other suitable contours, as long as the source of the two adjacent transistors in the direction Y is The electrode and the drain may share the same drain contact hole to be electrically connected to the corresponding semiconductor.

FIG. 4 is a schematic top view of an electronic device according to another embodiment of the disclosure. 3 and FIG. 4 at the same time, the electronic device 100c of this embodiment is substantially similar to the electronic device 100b of FIG. 3, so the same and similar components in the two embodiments will not be repeated here. The electronic device 100c of this embodiment is different from the electronic device 100b mainly in that, in the top view of the electronic device 100c of this embodiment, the outlines of the drain contact holes 131c, 132c, and 133c are C-shaped.

FIG. 5A is a schematic top view of an electronic device according to another embodiment of the disclosure. FIG. 5B is a schematic cross-sectional view of the electronic device of FIG. 5A along the section line B-B'. 1A-1B and FIGS. 5A-5B at the same time, the electronic device 100d of this embodiment is substantially similar to the electronic device 100 of FIGS. 1A-1B , so the same and similar components in the two embodiments will not be repeated here. The electronic device 100 d of the present embodiment is different from the electronic device 100 mainly in that, in the top view of the electronic device 100 d of the present embodiment, the third opening 171 d (or the fourth opening 172 d ) of the insulating layer 170 d is in the substrate 110 . The orthographic projection on the normal direction (ie, the direction Z) of 170 d partially overlaps the orthographic projection of the drain contact hole 130 on the normal direction of the substrate 110 , and the fourth opening 172 d of the insulating layer 170 d is in the normal direction of the substrate 110 . The orthographic portion of the upper portion overlaps the orthographic projection of the drain contact hole 130 on the normal direction of the substrate 110 .

5A and 5B, in this embodiment, the third opening 171d of the insulating layer 170d has a sidewall 171a' adjacent to the drain contact hole 130, and the fourth opening 172d of the insulating layer 170d has a neighboring The sidewall 172b' of the drain contact hole 130 has a sidewall 130a adjacent to the third opening 171d and a sidewall 130b adjacent to the fourth opening 172d. The orthographic projection of the sidewall 171a' of the third opening 171d on the normal direction of the substrate 110 (ie, the direction Z) does not overlap with the orthographic projection of the sidewall 130a of the drain contact hole 130 on the normal direction of the substrate 110, And the orthographic projection of the sidewall 172b ′ of the fourth opening 172d on the normal direction of the substrate 110 does not overlap with the orthographic projection of the sidewall 130b of the drain contact hole 130 on the normal direction of the substrate 110 . There is a distance D4 between the sidewall 171a' of the third opening 171d and the sidewall 130a of the drain contact hole 130, and a distance D5 between the sidewall 172b' of the fourth opening 172d and the sidewall 130b of the drain contact hole 130. In this embodiment, the distance D4 is, for example, the maximum distance measured along the direction Y between the sidewall 171a' of the third opening 171d and the sidewall 130a of the drain contact hole 130, and the distance D5 is, for example, the fourth opening The maximum distance measured along the direction Y between the sidewall 172b' of 172d and the sidewall 130b of the drain contact hole 130.

In this embodiment, since and the orthographic projection of the sidewall 171a' of the third opening 171d (or the sidewall 172b' of the fourth opening 172d) in the direction Z does not overlap with the sidewall 130a (or the sidewall of the drain contact hole 130) 130b) is an orthographic projection on the direction Z, so that a relatively flat topography can be provided to avoid the subsequent cracking of the interlayer insulating layer (not shown) disposed on the insulating layer 170d and located between the pixel electrode and the common electrode, and then The risk of short circuit caused by contact between the pixel electrode and the common electrode due to the rupture of the interlayer insulating layer can be avoided. Conversely, when the orthographic projection of the sidewall of the third opening adjacent to the drain contact hole (or the sidewall of the fourth opening of the drain contact hole) in the direction Z overlaps the sidewall (or adjacent to the drain contact hole) adjacent to the third opening When the orthographic projection (not shown) of the fourth opening sidewall) on the direction Z, an invert taper may appear, which may cause the subsequent arrangement on the insulating layer and between the pixel electrode and the common electrode. The interlayer insulating layer (not shown) therebetween is broken, thereby contacting the pixel electrode with the common electrode and causing a short circuit.

FIG. 6 is a schematic top view of an electronic device according to another embodiment of the disclosure. For the sake of clarity and convenience in the description of the drawings, FIG. 6 omits to illustrate some elements in the electronic device, for example, to omit to illustrate the scan lines, the transfer pads, the first opening, the second opening, the third opening and the fourth opening. Open holes, but not limited to this. 1A and FIG. 6 at the same time, the electronic device 100e of this embodiment is substantially similar to the electronic device 100 of FIG. 1A , so the same and similar components in the two embodiments will not be repeated here. The electronic device 100e of this embodiment is different from the electronic device 100 mainly in that the electronic device 100e of this embodiment includes drain contact holes 134 and 135, and the drain contact hole 134 and the drain contact hole 135 are separated from each other and Not connected.

Specifically, referring to FIG. 6 , in the top view of the electronic device 100e of this embodiment, among the transistors 120 , 122 and 124 that are adjacently arranged in the direction X, the source SD of the transistor 120 is The same drain contact hole 134 is shared with the drain SD', the source SD2 and the drain SD2' of the transistor 122, and the source SD4 and the drain SD4' of the transistor 124. Next, among the transistors 121 , 123 and 125 that are adjacently arranged in the direction X, the source SD1 and the drain SD1 ′ of the transistor 121 , the source SD3 and the drain SD3 ′ of the transistor 123 , and The source SD5 and the drain SD5 ′ of the transistor 125 share the same drain contact hole 135 .

To sum up, in the electronic device of the embodiment of the present disclosure, by arranging the drain contact hole between two adjacent transistors, the drains of the two adjacent transistors can pass through the same The drain contact holes are electrically connected to their corresponding semiconductors, so that the number of drain contact holes may be smaller than the number of drains. In this way, it can be avoided that the electronic device (such as a high-resolution display device, but not limited thereto) has a steep topography in the contact hole due to the excessive number of contact holes, which may cause the subsequent formation of the stack to have a steep topography. The risk of cracking is improved, thereby improving the layout of metal lines and thin film transistor cells in the display panel. In addition, since the orthographic projection of the sidewall of the third opening (or the fourth opening) adjacent to the drain contact hole on the normal direction (direction Z) of the substrate does not overlap with the adjacent third opening (or the fourth opening) of the drain contact hole The orthographic projection of the sidewalls of the four openings) on the normal direction of the substrate, thus providing a relatively flat topography to avoid cracking of the interlayer insulating layer subsequently disposed on the insulating layer and between the pixel electrode and the common electrode, thereby avoiding There is a risk of short circuit due to the breakage of the interlayer insulating layer and the contact between the pixel electrode and the common electrode. In this way, the electronic device of the embodiment of the present disclosure can have better reliability or better display quality.

Although the present disclosure has been disclosed above with examples, it is not intended to limit the present disclosure. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present disclosure. The scope of protection of the present disclosure shall be determined by the scope of the appended patent application.

100, 100a, 100b, 100c, 100d, 100e: electronic devices 110: Substrate 120, 121, 122, 123, 124, 125: Transistor 130, 131, 131b, 131c, 132, 132b, 132c, 133, 133b, 133c, 134, 135: drain contact holes 130a, 130b, 171a, 171a', 172b, 172b': side walls 140: Buffer layer 141: Masking layer 142, 142', 143, 170, 170d: insulating layer 1431: The first opening 1432: Second opening 150: Dielectric layer 151. GIa: Opening 160, 160': Adapter pad 171, 171d: The third opening 172, 172d: Fourth opening 181, 182, 183: source contact holes D1, D2, D3, D4, D5: Distance DL: data line GE, GE1: gate GI: gate insulating layer P0, P1, P2, P3, P4, P5: Subpixels SD, SD1, SD2, SD3, SD4, SD5: Source SD', SD1', SD2', SD3', SD4', SD5': Drain SE, SE1, SE2, SE3, SE4, SE5: semiconductor layers SE', SE1': side SL: scan line W1, W2, W3: Width X, Y, Z: direction

FIG. 1A is a schematic top view of an electronic device according to an embodiment of the disclosure. FIG. 1B is a schematic cross-sectional view of the electronic device of FIG. 1A along the section line A-A'. FIG. 2 is a schematic top view of an electronic device according to another embodiment of the disclosure. FIG. 3 is a schematic top view of an electronic device according to another embodiment of the disclosure. FIG. 4 is a schematic top view of an electronic device according to another embodiment of the disclosure. FIG. 5A is a schematic top view of an electronic device according to another embodiment of the disclosure. FIG. 5B is a schematic cross-sectional view of the electronic device of FIG. 5A along the section line B-B'. FIG. 6 is a schematic top view of an electronic device according to another embodiment of the disclosure.

100: Electronics

110: Substrate

120, 121, 122, 123, 124, 125: Transistor

130: Drain contact hole

130a, 130b, 171a, 172b: side walls

1431: The first opening

1432: Second opening

160: Transfer pad

171: The third opening

172: Fourth opening

D1, D2, D3: Distance

DL: data line

GE: gate

P0, P1, P2, P3, P4, P5: Subpixels

SD, SD1, SD2, SD3, SD4, SD5: Source

SD', SD1', SD2', SD3', SD4', SD5': Drain

SE, SE1, SE2, SE3, SE4, SE5: semiconductor layers

SE', SE1': side

SL: scan line

W2, W3: width

X, Y, Z: direction

Claims (9)

An electronic device comprising: a substrate; a plurality of transistors disposed on the substrate, and each of the plurality of transistors has a semiconductor, a source electrode and a drain electrode; a plurality of drain contact holes, wherein the drain electrode The plurality of drain contact holes are electrically connected to the semiconductor; and a data line is disposed on the substrate and is electrically connected to the plurality of transistors, wherein the data line is connected to the plurality of transistors. The width inside the drain contact hole is W2, the width of the data line outside the plurality of drain contact holes is W3, and W3 is less than or equal to W2, wherein the number of the plurality of drain contact holes is smaller than the number of the drain contact holes number of drains. The electronic device of claim 1, wherein the drains of at least two transistors of the plurality of transistors share one drain contact hole of the plurality of drain contact holes. The electronic device of claim 1, wherein the drain and the source of at least two of the plurality of transistors share one of the plurality of drain contact holes . The electronic device of claim 3, wherein the source electrode is electrically connected to the semiconductor through the plurality of drain contact holes, and the number of the plurality of drain contact holes is smaller than the number of the source electrodes . The electronic device of claim 1, wherein in an extending direction of the data line, two transistors of the plurality of transistors are adjacent to each other, and the plurality of transistors are adjacent to each other. One of the drain contact holes is disposed between the two adjacent transistors. The electronic device according to claim 5, wherein the drains of the two adjacent transistors share the same drain contact hole. The electronic device according to claim 5, wherein the drain electrodes and the source electrodes of the two adjacent transistors share the same drain contact hole. The electronic device of claim 1, further comprising: a transfer pad disposed on the plurality of transistors and electrically connected to the plurality of transistors; and an insulating layer disposed on the transfer pad and in the plurality of drain contact holes, there are third openings and fourth openings, the third openings and the fourth openings respectively expose a part of the transfer pad, wherein the The sidewall of the third opening adjacent to the drain contact hole does not overlap the sidewall of the drain contact hole adjacent to the third opening, and the sidewall of the fourth opening adjacent to the drain contact hole does not overlap The drain contact hole is adjacent to the sidewall of the fourth opening. The electronic device according to claim 1, wherein two transistors in the plurality of transistors are adjacent to each other in the extending direction of the scan line, and the drains of the adjacent two transistors The same drain contact hole is shared with the source electrode.

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