200928534 j 九、發明說明： ·> 【發明所屬之技術領域】 本發明係關於一種薄膜電晶體基板及其製造方法。 【先前技術】 目前，液晶顯示器逐漸取代傳統陰極射線管（Ca化 Ray Tube，CRT)顯示器，而且，由於液晶顯示器呈有輕、 薄、體積小等特點，使其非常適合應用於桌上型電腦f筆 記型電腦、個人數位助理（Pers〇nal Dighal Assistant> 〇 PD A)、便攜式電話、電視及多種辦公自動化與視聽設備 中。液晶面板是其主要元件，其一般包括一薄膜電晶體基 板、一彩色濾光片基板及一夾於該薄膜電晶體基板與該彩 色濾光片基板之間之液晶層。 請參閱圖1’係一種先前技術之薄膜電晶體基板之部份 剖面示意圖。在該薄膜電晶體基板1〇上定義一資料端子區 110、一顯示區120及一閘極端子區13〇。該顯示區12〇位於 該薄膜電晶體基板10之中央區域，該資料端子區丨1〇及該閘 〇極端子區130分別位於該顯示區120外圍之相鄰二邊緣處。 3亥薄膜電晶體基板1 〇包括一基底1 0 1、一閘極丨〗i、一電容 電極112、一資料端子（source pad)U3及一閘極端子（別“ Pad)114、一閘極絕緣層102、一非晶矽圖案1〇3、一掺雜非 日日梦圖案104、一源極115、一没極116、一純化層1〇5、一 第一連接孔a、一第二連接孔b、二第三連接孔c丨、、一 第四連接孔d、一像素電極1〇8、一第一透明導電層1〇9，一 第二透明導電層106及一第三透明導電層1〇7。 200928534 ，>料鳊子113、5亥閘極端子114係肖外部驅動電路(圖 未不）相連接之端子部，二者分別形成於該資料端子區⑽ -及閘極端子區13〇對應之基底1〇1上。該閘極1U及該電容電 極112間隔形成於該顯示區12G之基底1()1上。該閘極絕緣層 102覆盡該閘極111、該電容電極112、該資料端子113、該 閘極端子m及該基底⑻。該非w圖案1()3形成於與該閉 極m對應之閘極絕緣層102之表面。該換雜非晶石夕圖宰1〇4 覆蓋非晶石夕圖案103表面’並於該閘極⑴對應處形成一開 © 口e。該源極115與該沒極116相對設置於㈣口 〇二側之推 雜非晶矽圖案104表面並與該閘極絕緣層1〇2部份交疊。該 純化層105覆蓋具有該閘極絕緣層1〇2、該源極出及=汲極 =6之基底1〇1上。該第一連接孔&及該第二連接孔1^分別貫 穿該源極115、該汲極116對應處之該鈍化層1〇5，從而曝露 出部份源極115與部份汲極116。該第三連接孔cl、c2及該 第四連接孔d貫穿該鈍化層105及閘極絕緣層1〇2，從而曝露 出部份資料端子11 3及部份閘極端子114。 ❹ 該第一透明導電層109覆蓋該資料端子區11〇與該顯示 區120對應之鈍化層1〇5’並填充該第一連接孔a及該第三連 接孔cl，從而使該源極115籍由該第一連接孔a及該第三連 接孔cl與該資料端子113電連接。該像素電極1〇8形成於該 顯示區120對應之部份鈍化層1〇5上，並藉由該第二連接孔匕 與該汲極116相連接。該電容電極丨12及該像素電極1〇8與夾 於其間之該閘極絕緣層102及該鈍化層1 〇5形成一存儲電 容。該第二透明導電層106覆蓋該資料端子區11〇對應之鈍 200928534 * 化層10 5 ’並填充該第三連拉^丨9 a r μ, j：接孔c2與該資料端子ii3相連 ί;:: 端子"1 2 3 4之金屬材質以防止其氧化及 .^属’亦用於貫現外部資料_晶 子⑴之電連接。該第三透明導電 )開 130對應之鈍化層1〇5，並填 復盍》』極^子£ 11/ΙΛ ^ 異充5亥第四連接孔d與該閘極端子 114相連接’其用於保護該閘極端子114 ^_子 JL S 芬、由、p _v m 金'屬材質以防_lh ，、乳化及H亦用於實現外部掃描 該閘極端子114之電連接。 乃U3禾不）與 Ο該薄膜電晶體基板10係籍由五道 要步驟包括於第-道光罩形成該間極m、該電容ΐ: ==子113及該資料端子114。於第二道光罩= 忒非曰曰矽圖案103及該摻雜非晶矽圖案1〇4。於第三 :細原極115及該没極116。於第四道光罩形成該二 成本低之薄膜電晶體 9 1 觸孔b、該第三接觸孔ci、c2及該第四接 2 觸孔d。於第五道光罩形成該像素電極108、該第 電層⑽、該第二透明導電層⑽及該第三透明導電層1〇7。 “惟，由於各道光罩所形成結構圖案各不相同，因此該 3 溥膜電晶體基板10之五道光罩製程需要利用五個 = 4 之光罩，而光罩設計複雜且成本較高，則 體某 5 板10之製造成本較高。 兒日日體基 【發明内容】 有鑑於此，提供-種製程簡單、成本低 基板實為必要。 嗎^曰體 有鑑於此’提供一種製程簡單、 200928534 基板之製造方法實為必要。 Ί .干區—種晶體基板，包括：―絕緣基底，其包括一顯 資；端子子區及—資料端子區。該閘極端子區及該 於該絕緣基底上之—閘之相邊緣處。設置 極及該像素電極間隔設置於閘極線，該閘 線盥該閙朽m m缘基底之顯示區，該閘極 線…亥閘極相連接。一閘極 及其二側之絕緣基底上以及令間朽又置於5亥問極 〇上。一丰莫栌爲闻# 及。亥閘極線及其二側之絕緣基底 荦表面。沔朽、、’其位於該閘極對應之閘極絕緣層圖 電連接。-問極端子=7又® ’該沒極與該像素電極 6 知子该閘極端子位於該閘極端 間極線對應之閘極絕緣層㈣&子£之邊 極線相連接。一導電保，亚、'由-連接孔與該間 及該閉極端子。 ” s '、’其覆盍該源極、該汲極 ❹緣A底種二：電曰曰體基板製造方法，其步驟包括:提供一絕 形二二上:成像素電極;在該絕緣基底上 該閘極與該:極::;接 成-閘極絕緣層圖案，於該：Μ0 “及该閘極表面形 -連接孔對;:閘極絕緣層中形成 極及該間極線上沉積一第：金屬二二導體二、該像素電 黃-刻製程處理該第二金屬層:該:;體== 200928534 Ί ❹ ==應m緣層上形成—閘極端子，該閘極 朗極線接觸，於該半導體層上形成-溝 ^辛二，溝槽部份交疊之—源極及—㈣，且該汲極與該 =:極部份交疊；於該閘極絕緣層、該源極、該汲極、 圖案、該像素電極、該閘極端子及該資料端子上 :里二：：導電保護層，利用該第四光罩進行黃光 =透明導電保護層，進而於該源極、該汲極及該問極端 千上形成一透明導電保護層圖案。 相較於先前技術，前述薄膜電晶體基板製造方法形 ，保護層圖案與形成源極、汲極、半導體層、閘極端子 ^資料端子係使用同一光罩，較先前技術節省一道光罩， 從而降低了該薄膜電晶體基板之製造成本。 【實施方式】 、請參閱圖2，係本發明薄膜電晶體基板一較佳實施方 式之部份平面示意圖。該薄膜電晶體基板2〇包括一顯示區 210及一立而子區22〇,該端子區22〇位於該顯示區Η。之外 圍。该顯示區210包括複數相互平行之閘極線211、複數 貝料線212及複數公共線213。該複數閘極線211與該複 數資料線212垂直絕緣相交，從而界定複數像素單元214。 每一像素單元214包括一薄膜電晶體215、一儲存電 容216及一像素電極217。該薄膜電晶體215設置於該閘 極線211與該資料線212相交處，其包括一閘極2151、一 源極2152及一汲極2153。該閘極2151與該閘極線211相 連接’該源極2152與該資料線212相連接，該汲極2153 11 200928534 j 與該像素電極217招連桩。 ，線2U之間且與該像素^極=:線3位於相鄰二閘極 •儲存電容216。 、 〇 部份交疊，交疊處形成該 該端子區22G包括複數間極 子區222。該間極端子區 知子& 221與複數貧料端 接孔-該閘極端子端子加及-連 2Π相接觸。一閘極驅 ^由该連接孔Μ與該閘極線 馬£動Λ嬈错由外部掃描動 示）調整後再經由該閘極端子22η心射田驅動日日片（圖未 ❹該資料端子區222包括二傳輸至 助與該資料、線212目;;料端子2221，該資料端子 Γ圖去、 接且經由一外部資料驅動晶片 (圖未後之晝面顯示訊號經由 至該資料蝮21 ?，π品^ 而τ丨得翰 I線2攸而控制該像素單元2!4之晝面顯示。 IV Α圖3 ’係該薄臈電晶體基板心別沿^ fe0a|tA^?n% ^ 向之』面放大示意圖。該薄膜200928534 j IX. Description of the Invention: · Technical Field of the Invention The present invention relates to a thin film transistor substrate and a method of manufacturing the same. [Prior Art] At present, liquid crystal displays are gradually replacing the traditional cathode ray tube (CRT Ray Tube, CRT) display, and because of the light, thin, small size of the liquid crystal display, it is very suitable for use in desktop computers. f Notebook, personal digital assistant (Pers〇nal Dighal Assistant> 〇PD A), portable phone, TV and a variety of office automation and audio-visual equipment. The liquid crystal panel is a main component thereof, and generally includes a thin film transistor substrate, a color filter substrate, and a liquid crystal layer sandwiched between the thin film transistor substrate and the color filter substrate. Please refer to FIG. 1' for a partial cross-sectional view of a prior art thin film transistor substrate. A data terminal region 110, a display region 120 and a gate terminal region 13A are defined on the thin film transistor substrate 1A. The display area 12 is located at a central area of the thin film transistor substrate 10. The data terminal area 丨1〇 and the gate terminal area 130 are respectively located at adjacent two edges of the periphery of the display area 120. The 3H thin film transistor substrate 1 includes a substrate 110, a gate 丨i, a capacitor electrode 112, a source pad U3, and a gate terminal (other "pad" 114, a gate The insulating layer 102, an amorphous germanium pattern 1〇3, a doped non-day dream pattern 104, a source 115, a dipole 116, a purification layer 1〇5, a first connection hole a, and a second a connecting hole b, two third connecting holes c, a fourth connecting hole d, a pixel electrode 1〇8, a first transparent conductive layer 1〇9, a second transparent conductive layer 106 and a third transparent conductive Layer 1〇7. 200928534,> Terminals 113, 5, the gate terminal, 114, the external drive circuit (not shown) are connected to the terminal portion, which are respectively formed in the data terminal area (10) - and the gate terminal The sub-region 13A corresponds to the substrate 1〇1. The gate electrode 1U and the capacitor electrode 112 are formed on the substrate 1()1 of the display region 12G. The gate insulating layer 102 covers the gate 111. The capacitor electrode 112, the data terminal 113, the gate terminal m, and the substrate (8). The non-w pattern 1()3 is formed on the surface of the gate insulating layer 102 corresponding to the gate electrode m. The amorphous austenite shovel 1 〇 4 covers the surface of the amorphous slab pattern 103 and forms an open port e at the corresponding position of the gate (1). The source 115 is opposite to the immersion 116 (4). The surface of the two sides of the doped amorphous germanium pattern 104 overlaps with the gate insulating layer 1〇2. The purification layer 105 is covered with the gate insulating layer 1〇2, the source is out and the=bungee= The first connection hole & and the second connection hole 1^ respectively penetrate the source 115 and the passivation layer 1〇5 corresponding to the drain electrode 116, thereby exposing a part of the source a pole 115 and a portion of the drain 116. The third connection holes cl, c2 and the fourth connection hole d extend through the passivation layer 105 and the gate insulating layer 1〇2, thereby exposing a portion of the data terminals 11 and a gate terminal 114. The first transparent conductive layer 109 covers the data terminal region 11〇 and the passivation layer 1〇5′ corresponding to the display region 120 and fills the first connection hole a and the third connection hole cl, thereby The source electrode 115 is electrically connected to the data terminal 113 by the first connection hole a and the third connection hole c1. The pixel electrode 1〇8 is formed in the display area 120. a portion of the passivation layer 1 〇 5 is connected to the drain electrode 116 through the second connection hole 。. The capacitor electrode 丨 12 and the pixel electrode 1 〇 8 and the gate insulating layer 102 sandwiched therebetween The passivation layer 1 〇 5 forms a storage capacitor. The second transparent conductive layer 106 covers the blunt 200928534 layer 10 5 ′ corresponding to the data terminal region 11 并 and fills the third connection 丨 9 ar μ, j: The connection hole c2 is connected to the data terminal ii3 ί;:: the metal material of the terminal "1 2 3 4 is prevented from being oxidized and the genus is also used for the electrical connection of the external data _ crystal (1). The third transparent conductive opening 130 corresponds to the passivation layer 1 〇 5, and is filled with 盍 』 』 极 £ £ £ 11 11 11 £ £ £ 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四 第四In order to protect the gate terminal 114 ^ _ JL S fen, from, p _ ν m gold 'genuine material to prevent _lh, emulsification and H is also used to achieve external scanning of the electrical connection of the gate terminal 114. The film transistor substrate 10 is formed by a five-step process including forming the interpole m, the capacitor ΐ: == sub-113 and the data terminal 114. The second mask = the non-twist pattern 103 and the doped amorphous germanium pattern 1〇4. In the third: the fine pole 115 and the poleless 116. The second low-cost thin film transistor 9 1 contact hole b, the third contact hole ci, c2 and the fourth contact hole d are formed in the fourth mask. The pixel electrode 108, the first electrical layer (10), the second transparent conductive layer (10) and the third transparent conductive layer 1〇7 are formed in the fifth mask. "However, because the structure patterns formed by the reticle are different, the five mask processes of the three bismuth film substrate 10 need to utilize a mask of five = 4, and the reticle design is complicated and the cost is high. The manufacturing cost of a certain 5 board 10 is relatively high. The daily basis of the body [invention] In view of this, it is necessary to provide a simple process and a low cost substrate. The present invention provides a simple process. 200928534 The manufacturing method of the substrate is really necessary. 干 Dry area - a kind of crystal substrate, including: "insulation substrate, which includes a display capital; a terminal sub-area and a data terminal area. The gate terminal region and the insulating substrate The gate electrode and the pixel electrode are spaced apart from each other at a gate line, and the gate line is a display area of the base of the rim, and the gate line is connected to the gate. On the insulating substrate on the two sides and on the two sides of the immersion, it is placed on the 5th floor. The first step is the surface of the insulating gate and the two sides of the insulating base. It is located at the gate corresponding to the gate insulating layer Connection. - Ask the terminal = 7 again ® 'The pole is connected to the pixel electrode 6 知子 The gate terminal is located at the gate of the gate electrode corresponding to the gate insulation layer (4) & Bao, ya, 'from-connection hole and the same and the closed terminal. s ', 'which covers the source, the ❹ ❹ A A bottom 2: the method of manufacturing the electrode substrate, the steps The method includes: providing a shape of a diode electrode: on the insulating substrate, the gate and the: pole::; is connected to a gate insulating layer pattern, wherein: Μ0 "and the gate surface shape - a pair of connection holes; a gate formed in the gate insulating layer and a first electrode deposited on the interpolar line: the pixel is electrically yellow-etched to process the second metal layer: the body == 200928534 Ί ❹ == The gate electrode is formed on the m-edge layer, the gate is in contact with the gate, and the trench is formed on the semiconductor layer, the trench is partially overlapped, the source and the (four), and the gate The pole overlaps with the =: pole portion; on the gate insulating layer, the source, the drain, the pattern, the pixel electrode, the gate terminal, and the data terminal: a conductive protective layer, wherein the fourth photomask is used to perform a yellow light=transparent conductive protective layer, and a transparent conductive protective layer pattern is formed on the source, the drain and the extreme electrode. Compared with the prior art, the foregoing In the method of manufacturing a thin film transistor substrate, the protective layer pattern uses the same mask as the source, the drain, the semiconductor layer, and the gate terminal, thereby saving a mask compared to the prior art, thereby reducing the thin film transistor substrate. [Embodiment] FIG. 2 is a partial plan view showing a preferred embodiment of a thin film transistor substrate of the present invention. The thin film transistor substrate 2 includes a display area 210 and a vertical sub-area. 22〇, the terminal area 22〇 is located at the periphery of the display area Η. The display area 210 includes a plurality of gate lines 211, a plurality of feed lines 212, and a plurality of common lines 213 which are parallel to each other. The complex gate line 211 is vertically insulated from the complex data line 212 to define a plurality of pixel units 214. Each pixel unit 214 includes a thin film transistor 215, a storage capacitor 216, and a pixel electrode 217. The thin film transistor 215 is disposed at the intersection of the gate line 211 and the data line 212, and includes a gate 2151, a source 2152 and a drain 2153. The gate 2151 is connected to the gate line 211. The source 2152 is connected to the data line 212, and the drain 2153 11 200928534 j is connected to the pixel electrode 217. Between the lines 2U and with the pixel ^== line 3 is located adjacent to the second gate • storage capacitor 216. And 部份 partially overlapping, the overlap forming portion of the terminal region 22G includes a plurality of interpole regions 222. The terminal region of the terminal, the zizi & 221, is in contact with the plurality of poor terminal terminals - the gate terminal terminal plus the two terminals. A gate drive ^ is connected by the connection hole Μ and the gate line is rotated by an external scan), and then the day-end film is driven by the gate terminal 22n. The area 222 includes two transmissions to the data and the line 212; the material terminal 2221, the data terminal is connected to the interface, and the chip is driven via an external data (the picture is displayed after the image is not shown). ?, π品^ and τ丨得翰I line 2攸 and control the display of the pixel unit 2!4. IV Α Figure 3' is the thin 臈 transistor substrate heart ^fe0a|tA^?n% ^ to the surface of the enlarged view. The film
Si: I步包括 '絕緣基底2〇1、-間極絕緣層 ❾Ξ f Π Ϊ曰圖案2 G 3 '位於該非晶石夕圖案2 0 3二側 該門:二1曰曰石夕圖案204及—透明導電保護層圖案205。 相 =及該像素電極217間隔設置於該顯示區綱 對應之該絕緣基底201上。該閘極絕 罢 =2⑸及該絕緣基底201。該非晶衝 二=1，閘極絕緣層圖案2〇2表面，該摻雜非晶 ^ 5又置於s亥非晶矽圖案203表面並具有一溝槽 =3玄源極2152及汲極2153分別設置在該溝槽£二側之嗜 摻雜非晶石夕圖案204表面上，且該汲極2153與該像素錄 12 200928534 217電連接。 該資料端子2221位於該資料端子區222之閘極絕緣層 圖案202表面，並與該資料線212相連接。該閘極線 延伸至該閘極端子區221對應之該絕緣基底2〇1上，經由 該連接孔2A與該閘極端子2211電連接。該透明導電保護 層圖案205完全覆蓋於該源極2152、該汲極2153、嗜資升= :子2221及該閘極端子2211，以防止該層_漏及被 0亦該薄膜電晶體基板2G之邊緣區域（圖未示） 2 $夕卜圍功能電路’如—種用於修補閘極線之修 =:路：修補線與該問極具有一結點’當該間極線與該開 斷^ ’訊遽可藉由該修補線經由該結點傳輸至該問 ’⑽補線與該閘極藉由—介電 結點處之修補線與該閉極亦可採用一連接孔實現H 即如同該閘極端早„ 7# a 貝兄电連接 功能電路，^ 閘極線2U之連接方式。其餘 力此二路：如檢測電路之結點亦可為此結構。 之fil方：圖4至圖12’圖4係該薄膜電晶體基板20 別製造方圖5至圖12係該薄膜電晶體基板 各主要步驟之結構示意圖。 板20之製造方法之具體步驟如下：電日曰體基 步驟幻〇 ’形成一像素電極217: 請參閱圖5，拉糾 可以係玻璃、石英或者H彖基底201，該絕緣基底201 上沉積一透明導電/，陶Λ專絕緣材質。在該絕緣基底201 等冤層该透明導電層之材質可以為氧化銦 200928534 錫（Indium Tin 0xide，IT0)或氧化銦鋅（Indium zinc 〇xide， ’ ίΖ〇)。再在該透明導電層上沉積一第一光阻層（圖未示）/ •光罩（圖未示）對該第—光阻層曝光，再顯影曝光 後之第-光阻層，然後以該剩餘第一光阻層為遮罩性刻該 透明導電層’進而在該顯示區21〇，形成如圖6所示之該 像素電極21 7，並移除剩餘光阻材質。 步驟S21，形成閘極2151及閘極線2ιι: 請一併參閱圖6,在該絕緣基底2〇1及該像素電極217 〇上沉積一第一金屬層（圖未示） )第金屬層之材質可為 •糸金屬、钥、路、叙或銅。在該第—金屬層上沉積一第 一先阻層（圖未示），利用一第二光罩（圖未 層進行曝光，再顯影曝光後之第_光阻# /弟一先阻 一 兀*1乂心罘一九阻層，亚以該剩餘第Si: I step includes 'insulating substrate 2 〇 1, - interpolar insulating layer ❾Ξ f Π Ϊ曰 pattern 2 G 3 ' is located on the amorphous eve pattern 2 0 3 two sides of the door: two 1 曰曰 夕 夕 pattern 204 and a transparent conductive protective layer pattern 205. Phase = and the pixel electrode 217 are spaced apart from the insulating substrate 201 corresponding to the display area. The gate is absolutely = 2 (5) and the insulating substrate 201. The amorphous punch 2 = 1, the gate insulating layer pattern 2 〇 2 surface, the doped amorphous ^ 5 is placed on the surface of the s-amorphous germanium pattern 203 and has a trench = 3 source 2152 and drain 2153 They are respectively disposed on the surface of the doped amorphous slab pattern 204 on the two sides of the trench, and the drain 2153 is electrically connected to the pixel record 12 200928534 217. The data terminal 2221 is located on the surface of the gate insulating layer pattern 202 of the data terminal region 222 and is connected to the data line 212. The gate line extends to the insulating substrate 2〇1 corresponding to the gate terminal region 221, and is electrically connected to the gate terminal 2211 via the connection hole 2A. The transparent conductive protective layer pattern 205 completely covers the source electrode 2152, the drain electrode 2153, the sufficiency swell =: the sub-2221, and the gate terminal 2211 to prevent the layer_drain and the film from being on the thin film transistor substrate 2G. The edge area (not shown) 2 $ 夕 围 functional circuit 'such as - used to repair the gate line repair =: road: repair line and the question pole has a node 'When the line and the opening The signal can be transmitted through the node to the '(10) line and the gate by the repair line and the gate line at the dielectric junction and the closed pole can also be realized by a connection hole. That is, as the gate is extremely early „ 7# a Bell brother electrical connection function circuit, ^ gate line 2U connection mode. The rest of the force of the two: such as the detection circuit node can also be this structure. fil side: Figure 4 FIG. 12 is a schematic structural view showing the main steps of the thin film transistor substrate. The specific steps of the method for manufacturing the board 20 are as follows: The illusion 'forms a pixel electrode 217: Please refer to FIG. 5, the lacquer can be glass, quartz or H 彖 substrate 201 A transparent conductive/ceramic insulating material is deposited on the insulating substrate 201. The insulating conductive substrate 201 may be made of indium oxide 200928534 tin (Indium Tin 0xide, IT0) or indium zinc oxide. Indium zinc 〇xide, ' Ζ〇 。.. Deposit a first photoresist layer on the transparent conductive layer (not shown) / • Photomask (not shown) exposes the first photoresist layer, and then develops exposure Then, the first photoresist layer is then patterned with the remaining first photoresist layer as a masking layer and then formed in the display region 21 to form the pixel electrode 21 7 as shown in FIG. In addition to the remaining photoresist material, step S21, forming a gate 2151 and a gate line 2: please refer to FIG. 6 to deposit a first metal layer on the insulating substrate 2〇1 and the pixel electrode 217〇 (not shown) )) The material of the metal layer may be 糸 metal, key, road, rib or copper. A first etch layer (not shown) is deposited on the first metal layer, and a second mask is used. The layer is exposed, and then the first photo-resistance after the development of the exposure # /弟一一一一兀*1乂心罘一九阻层In the remaining sub-section
一光阻層為遮罩蚀刻該第一全J P 21。及該閘極端子區221中：成屬:圖， τ A成如圖6所示之該閘極2 j 5 1 及該閘極線211，並移除剩餘光阻材質。 © ^ ^驟奶，形成問極絕緣層施、非晶石夕層加a、摻 雜非日日矽層204a及第三光阻圖案： 月併乡閱圖7 ’在該絕緣基底201、該閘極2} 5工、 該閘極線211及該像辛雷炻？17 μ ^ ·丨 豕常電極217上，利用化學氣相沉積 爱Dep〇siti〇n，CVD)形成氮化石夕⑽X)之方 =述結構之間極絕緣層2〇〜再侧 二曰 非晶矽層2〇3a;並進行-道摻雜工藝， 上ra進行摻雜’進而於該非晶秒層2心之 上表面形成-摻雜非日日日石夕層2G4a。再在該摻 200928534 • 204a上沉積一第三光阻層206，則該閘極絕緣層202a、該 ' 非晶矽層203a及該摻雜非晶矽204a層疊設置。提供一第 二光罩207對準該第三光阻層206 ’以紫外光線照射該第 三光阻層206。該第三光罩207為狹縫光罩（SUtMask)，其 包括遮光區207a、狹縫區2〇7b及透光區207c，其中該遮 光區207a對應於該閘極2151，該透光區207c對應於該像 素電極217及該閘極端子區221，該狹縫區2〇7b對應於該 資料端子區222及其餘剩餘位置。再對該第三光阻層2〇6 ❹進行顯影’因該遮光區2〇7a、該狹缝區2〇7b及該透光區 2〇7c之透光能力依次減弱，從而使該第三光阻層2〇6在曝 光顯影後形成如圖8所示之預定圖案，即相應於該狹縫區 2〇7b，剩餘第三光阻層2〇讣較相應於該遮光區汕以之 餘第二光阻層206a之展庚壤，安4·庙认斗* 哲一， 厚度潯對應於泫透光區207c處並 第三光阻層206覆蓋。 …、 及連形成閘極絕緣層圖案2G2、非晶硬圖案203 ❿ ，一併參閱® 9 ’以剩餘第三光 非it層純及該_層-: 三光阻層:^咖二行::刻：”：：會對該剩餘第 光阻層206b全部性刻掉厚^較薄之該剩餘第三 應之該摻雜非晶♦層20㈣露^餘第三光阻層鳩相對 層二，為遮㈣刻該摻雜非晶-非日日夕層203a及該間極絕緣層咖，使未被 15 200928534 ，該剩餘第三光阻層206a覆蓋之該摻雜非晶矽層2〇4a及該 非晶矽層203a全部蚀刻掉，形成如圖1〇所示之非晶矽圖 •案203、摻雜非晶矽層2〇4a及閘極絕緣層圖案2〇2，其中， 該問極絕緣層圖案逝覆蓋除該像素電極217、該閘極端 :區⑵之閘極線211外之絕緣基底2〇1上，該非晶石夕圖 .、203、摻雜非晶矽層2〇钧層疊設置在該閘極ΜΗ對應 層圖案202上。同時於該閑極線2ιι上方形： 〇光阻層編。’亚使雜素電極217外露。移除該剩餘第三 ^驟S24，形成源極2152、汲極2153、換雜非晶石夕圖 -、、閘極端子2211及資料端子2221· 桎閱圖u’在該剩餘摻雜非晶…^該間 二、，、=層圖案2〇2、該像素電極217 未示)。該第二金屬層之材質可為 ❹ 第四光阻>ml 1合金。再在該第二金屬層上沉積一 先阻層（圖未示）。以一第四光罩 阻層曝光，並顯影曝光後之第 再以光 光阻層為遮罩㈣該第：金# 曰再;^剩餘第四 對應之非晶石夕圖案203上形心在該問極215! 204及—溝槽e，在續溝样1圖所不之摻雜非晶石夕圖案 表面分別形成該源極^及及^換雜非晶石夕圖案撕 ⑵形成閘極端子2211及在該資153;在該閘極端子區 子2功。該閘極端子2211“^=區奶形成資料端 211相接觸。移除剩餘光阻材f /連接孔2A與該閘極線 200928534 / 二驟S25形成透明導電保護層圖案205: 〇月併參閱圖12，在該閘極絕緣層202、爷泝;)¾ 7q 該汲極⑽、該非晶石夕圖案2〇3、該料2、 極端子_及該資料端子222 一透明 (圖未示）。該透明暮s 稹远月導電保蠖層 鋅。在嗲透 、保護層之材質.為氧化銦錫或氧化銦 在》亥透明導電保護層上沉積 以前述第四道光罩對 尤阻層(圖未不）。 卜或其他方式照射該第五 ： 〇;行顯影’形成第五光阻層圖索(圖“= 層圖案205，，、类保護層’形成透明導電保護 2152、該汲極_、該閘極端子2211及該；；極 移除剩餘光阻材質，進而^固。及該貝⑽子222卜 板20。 、 形成如圖2所不之薄膜電晶體基 方法先前技術，由於前述薄膜電晶體基板之f造 〇 a s 205 ^ —— 係使用同光t，圖Λ204、閑極端子2211及資料端子2221 β ^ 軚先則技術節省一道光罩，從而降低了 口只潯骐電日日體基板20之製造成本。 - 資料：晶板2〇之該資料端子2221與該 因此，1金面觀連’』無需經由一透明導電層連接’ 再:、：：顯示訊號傳送之損耗減小，準確性較高。 資料線21::二：電晶體基板20之該資料端子2221與該 貧料線扣之間無需經由連接孔連接，因此，可避免在製 17 200928534 .造過程中形成連接孔而產生的龜裂不良。 本發明薄膜電晶體基板20亦可具有多種變更設計。如 該資料端子㉟222之資料端子2221亦可不與該資料線212 直接相連，而是與該閘極線211 一併形成於該絕緣基底2〇1 線2U則與該源極2151及該没極仙一併形 =接心料料2221經由—連接孔2A與該㈣線212電 綜上所述，本發明確已符合發明之要件，担山 〇專射請。惟，以上該者僅為 依法&出 發明之範圍並不以上述實施方式式’本 之人士援依本發明之精神所作二先、心本案技藝 蓋於以下申請專利範圍内。4放。飾或變化，皆應涵 200928534 【圖式簡單說明】 圖1係先前技術之㈣電晶體基板之剖面示意圖。 圖2係本發明之薄骐電晶體基板之部份平面示意圖。 圖3㈣2所示薄膜電晶體基板沿IVA-IVAHjvbi C-IVC方向之剖面放大示意圖。A photoresist layer etches the first full J P 21 for the mask. And in the gate terminal region 221: a genus: a graph, τ A is the gate 2 j 5 1 and the gate line 211 as shown in FIG. 6, and the remaining photoresist material is removed. © ^ ^ milking, forming a pole insulating layer, amorphous layer, a, doping non-day layer 204a and a third photoresist pattern: month and township Figure 7 'in the insulating substrate 201, the Gate 2} 5 workers, the gate line 211 and the image like Xin Lei? 17 μ ^ · 丨豕 on the electrode 217, using chemical vapor deposition love Dep〇siti〇n, CVD) to form a nitride 夕 (10) X) square = between the structure of the insulating layer 2 〇 ~ re-side two amorphous The germanium layer 2〇3a; and the doping process is performed, and the doping is performed on the upper side of the amorphous second layer 2 to form a doped non-day day layer 2G4a. Further, a third photoresist layer 206 is deposited on the doped 200928534 • 204a, and the gate insulating layer 202a, the 'anomorphous germanium layer 203a and the doped amorphous germanium 204a are stacked. A second photomask 207 is provided to align the third photoresist layer 206' with the ultraviolet light to illuminate the third photoresist layer 206. The third photomask 207 is a slit mask (SUtMask), which includes a light shielding area 207a, a slit area 2〇7b, and a light transmission area 207c, wherein the light shielding area 207a corresponds to the gate 2151, and the light transmission area 207c Corresponding to the pixel electrode 217 and the gate terminal region 221, the slit region 2〇7b corresponds to the data terminal region 222 and the remaining remaining positions. And developing the third photoresist layer 2〇6 '', because the light-shielding ability of the light-shielding region 2〇7a, the slit region 2〇7b, and the light-transmitting region 2〇7c is sequentially weakened, thereby making the third The photoresist layer 2〇6 forms a predetermined pattern as shown in FIG. 8 after exposure and development, that is, corresponding to the slit region 2〇7b, and the remaining third photoresist layer 2〇讣 corresponds to the shading region. The second photoresist layer 206a is covered with a glass layer, and the thickness 浔 corresponds to the 泫 light-transmissive region 207c and is covered by the third photoresist layer 206. ..., and even form a gate insulating layer pattern 2G2, an amorphous hard pattern 203 ❿, see also ® 9 'to the remaining third light non-it layer pure and the _ layer -: three photoresist layer: ^ coffee two lines:: Engraving: ":: the remaining photoresist layer 206b will be completely thinned out. The remaining third portion of the doped amorphous layer 20 (4) is exposed to the third photoresist layer 鸠 opposite layer 2, The doped amorphous-non-Japanese layer 203a and the inter-electrode insulating layer are etched (4), so that the doped amorphous germanium layer 2〇4a and the remaining third photoresist layer 206a are not covered by 15 200928534 and The amorphous germanium layer 203a is completely etched away to form an amorphous germanium pattern 203, a doped amorphous germanium layer 2〇4a, and a gate insulating layer pattern 2〇2 as shown in FIG. The layer pattern is covered by the pixel electrode 217, the gate electrode: the gate substrate 211 outside the gate line 211, the amorphous substrate 、, 203, doped amorphous layer 2 〇钧 stacked On the gate electrode corresponding layer pattern 202. At the same time on the idle line 2 ιι square: 〇 photoresist layer. 'Asian impurity electrode 217 exposed. Remove the remaining third step S24, shape The source 2152, the drain 2153, the amorphous austenite--, the gate terminal 2211, and the data terminal 2221· 桎 u u u in the remaining doped amorphous ... ^ between the two, ,, = layer pattern 2〇2, the pixel electrode 217 is not shown. The material of the second metal layer may be ❹4th photoresist>ml1 alloy. A pre-resist layer is deposited on the second metal layer (not shown). Exposing with a fourth mask resist layer and developing the exposed light photoresist layer as a mask (4) the first: gold #曰再; ^ remaining fourth corresponding amorphous stone pattern 203 on the center In the question electrode 215! 204 and the groove e, the surface of the doped amorphous stone pattern is formed on the surface of the doped amorphous stone pattern of the continuous groove sample 1 to form the gate. The terminal 2211 and the element 153; in the gate terminal area 2 work. The gate terminal 2211 "^ = area milk forming data end 211 is in contact. Removing the remaining photoresist material f / connection hole 2A and the gate line 200928534 / two step S25 to form a transparent conductive protective layer pattern 205: 〇月 and refer to FIG. 12, in the gate insulating layer 202, the master trace;) 3⁄4 7q The drain (10), the amorphous austenite pattern 2〇3, the material 2, the terminal _ and the data terminal 222 are transparent (not shown). The transparent 暮 稹 稹 far month conductive protective layer of zinc. In the material of the transparent and protective layer, indium tin oxide or indium oxide is deposited on the transparent conductive protective layer of the above-mentioned fourth light-shielding layer (not shown). Bu or other means of illuminating the fifth: 〇; line development 'forming a fifth photoresist layer map (Fig. " = layer pattern 205,, class-like protective layer 'forming transparent conductive protection 2152, the drain _, the gate terminal Sub 2211 and the ;; remove the remaining photoresist material, and then the solid and the shell (10) sub-222 board 20, forming a thin film transistor-based method as shown in FIG. 2, due to the aforementioned thin film transistor substrate The f 〇 as 205 ^ —— uses the same light t, the figure 204, the idle terminal 2211 and the data terminal 2221 β ^ 軚 first technology saves a mask, thereby reducing the mouth of the solar cell substrate 20 Manufacturing cost. - Data: The data terminal 2221 of the crystal plate 2 is connected to the gold plate. Therefore, there is no need to connect via a transparent conductive layer. ':::: The loss of display signal transmission is reduced, accuracy The data line 21::2: the data terminal 2221 of the transistor substrate 20 and the lean line buckle need not be connected through the connection hole, so that the formation of the connection hole during the manufacture of the system can be avoided. Poor cracking. The thin film transistor base of the present invention The data terminal 2221 of the data terminal 35222 may not be directly connected to the data line 212, but may be formed together with the gate line 211 on the insulating substrate 2〇1 line 2U. The source 2151 and the singularity = the core material 2221 are electrically connected via the connection hole 2A and the (four) line 212. The present invention has indeed met the requirements of the invention, and the mountain is dedicated to the shot. The person is only legally & the scope of the invention is not in the above-mentioned embodiment. The person in charge of the invention is based on the spirit of the invention. The skill of the present invention is covered by the following patent application. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic cross-sectional view of a (4) transistor substrate of the prior art. Figure 2 is a partial plan view of a thin germanium transistor substrate of the present invention. Figure 3 (4) 2 shows a thin film transistor substrate along IVA-IVAHjvbi is a schematic enlarged view of the C-IVC direction.
圖4係薄膜電晶體基板製造方法之流程圖。 圖5=係圖4所示之薄膜電晶體基板之製造方法之各 主要步驟之結構示意圖。4 is a flow chart of a method of manufacturing a thin film transistor substrate. Fig. 5 is a structural schematic view showing the main steps of the method for producing a thin film transistor substrate shown in Fig. 4.
【主要元件符號說明】 薄膜電晶體基板 閘極線 公共線 薄膜電晶體 源極 儲存電容 端子區 資料端子區 閘極端子 絕緣基底 非晶碎圖案 透明導電保護層圖案 非晶秒層 弟—光阻層 連接孔 遮光區 剩餘第三光阻層 20顯示區 211資料線 213像素單元 215閘極 2152沒極 216像素電極 220閘極端子區 222資料端子 2211溝槽 201閘極絕緣層圖案 203摻雜非晶石夕圖案 2 0 5閘極絕緣層 2〇3a摻雜非晶矽層 206第三光罩 曰 2A狹縫區 207a透光區 210 212 214 2151 2153 217 221 2221 e 202 204 202a 204a 207 207b 207c 206a、206b 19[Major component symbol description] Thin film transistor substrate gate line common line thin film transistor source storage capacitor terminal area data terminal area gate terminal insulation substrate amorphous pattern transparent conductive protection layer pattern amorphous second layer brother - photoresist layer Connection hole opaque area remaining third photoresist layer 20 display area 211 data line 213 pixel unit 215 gate 2152 no pole 216 pixel electrode 220 gate terminal region 222 data terminal 2211 trench 201 gate insulating layer pattern 203 doped amorphous Shi Xi pattern 2 0 5 gate insulating layer 2〇3a doped amorphous germanium layer 206 third mask 曰 2A slit region 207a light transmitting region 210 212 214 2151 2153 217 221 2221 e 202 204 202a 204a 207 207b 207c 206a 206b 19