CN106098706B - A kind of array substrate and preparation method thereof, display device - Google Patents
A kind of array substrate and preparation method thereof, display device Download PDFInfo
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- CN106098706B CN106098706B CN201610585770.6A CN201610585770A CN106098706B CN 106098706 B CN106098706 B CN 106098706B CN 201610585770 A CN201610585770 A CN 201610585770A CN 106098706 B CN106098706 B CN 106098706B
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- 239000000758 substrate Substances 0.000 title claims abstract description 87
- 238000002360 preparation method Methods 0.000 title abstract description 5
- 238000000034 method Methods 0.000 claims abstract description 76
- 229910052751 metal Inorganic materials 0.000 claims abstract description 17
- 239000002184 metal Substances 0.000 claims abstract description 17
- 239000010409 thin film Substances 0.000 claims abstract description 10
- 239000010949 copper Substances 0.000 claims description 23
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 21
- 229910052802 copper Inorganic materials 0.000 claims description 21
- 238000004519 manufacturing process Methods 0.000 claims description 20
- 238000000059 patterning Methods 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 6
- 230000004888 barrier function Effects 0.000 claims description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 29
- 238000010586 diagram Methods 0.000 description 9
- 239000004973 liquid crystal related substance Substances 0.000 description 7
- 239000011521 glass Substances 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 229910052750 molybdenum Inorganic materials 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 239000012528 membrane Substances 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000007687 exposure technique Methods 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
In array substrate provided by the invention and preparation method thereof, display device, wherein the array substrate, including thin film transistor (TFT) and public electrode；The thin film transistor (TFT) includes the grid, active layer, source electrode and drain electrode formed on substrate；The grid includes the first conductive layer and the second conductive layer；First conductive layer and the public electrode same layer；Second conductive layer is metal.Array substrate forms the second conductive layer with the setting of public electrode same layer, forms the first conductive layer on the second conductive layer, the first conductive layer and the second conductive layer together constitute grid when forming public electrode.In the array substrate, the first conductive layer is formed while forming public electrode, it does not need specially to make buffer layer between the second conductive layer and substrate to increase the adhesiveness of the second conductive layer and substrate, the structure for simplifying array substrate eliminates the process flow that buffer layer is made between the second conductive layer and substrate.
Description
Technical field
The invention belongs to field of display technology, and in particular to a kind of array substrate and preparation method thereof, display device.
Background technique
Liquid crystal display device is low in energy consumption, radiationless because having many advantages, such as, has occupied plane display field predominantly
Position.Liquid crystal display panel generally includes the array substrate and color membrane substrates being oppositely arranged, and filling in existing liquid crystal display device
Liquid crystal layer between array substrate and color membrane substrates, wherein array substrate is equipped with multiple thin film transistor (TFT)s and multiple pictures
The drain electrode of plain electrode, pixel electrode and thin film transistor (TFT) connects, and common electrical corresponding with pixel electrode is equipped on color membrane substrates
Pole.When being that pixel electrode charges by thin film transistor (TFT), electric field is formed between pixel electrode and public electrode, thus controllable
Liquid crystal molecule deflection in the corresponding liquid crystal region of pixel electrode, and then realize crystal display.
In the fabrication process of the array substrate, metallic aluminium (Al) or metal molybdenum (Mo) can be used as the material of grid and source-drain electrode
Material.But for powerful display device, the high resistivity of Al or Mo will affect the propagation of electric signal in display device,
And metal (Cu) has lower resistivity compared to Al or Mo, can become the alternative materials of Al or Mo.
However, the poor adhesion between Cu and glass, needs in the manufacturing process of existing array substrate in glass base
One layer of buffer layer good with glass adhesion is first deposited on plate, then etched technique forms grid on the buffer layer by Ni metal deposition
Pole or source-drain electrode.The manufacturing process of this array substrate that grid or source-drain electrode are formed using Ni metal, is needed by buffer layer
Ni metal is adhered on glass or insulating layer, array base-plate structure is complicated, and the process flow of array substrate production is cumbersome.
Summary of the invention
The technical problem to be solved by the present invention is to how simplify the technique of the structure of array substrate and array substrate production
Process.
For the technical problem, the present invention provides a kind of array substrates, including thin film transistor (TFT) and public electrode；
The thin film transistor (TFT) includes the grid, active layer, source-drain electrode formed on substrate；
The grid includes the first conductive layer and the second conductive layer；
First conductive layer and the public electrode same layer；
Second conductive layer is metal.
Preferably, further includes:
The first insulating layer is provided on the grid；
Active layer is provided on first insulating layer；
Etching barrier layer and second insulating layer figure are provided on the active layer；
Pixel electrode is provided in the second insulating layer；
The source-drain electrode is overlapped on the pixel electrode.
Preferably, the source and drain extremely copper.
Preferably, first conductive layer is formed with the public electrode using identical material, and second conductive layer is
Copper.
Second aspect, the present invention also provides a kind of production methods of array substrate, comprising:
After the first conductive layer and the second conductive layer is formed on the substrate, grid and common electrical are formed by a patterning processes
Pole；
Wherein, the public electrode is formed using first conductive layer, and second conductive layer is metal.
Preferably, described to pass through that patterning processes form grid and public electrode includes:
To half gray level mask patterned process of first conductive layer and the second conductive layer:
Second conductive layer in public electrode region Partial exposure patterned process removal public electrode region is formed public
Electrode pattern；
Region except area of grid and public electrode is exposed completely, forms gate patterns.
Preferably, further includes:
The first insulating layer and active layer are formed on the grid；
Second insulating layer and third conductive layer are formed on the active layer, by a patterning processes, form connection institute
State the via hole of active layer；
The 4th conductive layer for connecting the active layer is formed on the third conductive layer, passes through a patterning processes, shape
At source-drain electrode and pixel electrode.
Preferably, described to pass through a patterning processes, it forms source-drain electrode and pixel electrode includes:
To half gray level mask patterned process of the 4th conductive layer:
Region in addition to pixel electrode area and source drain region is exposed completely, patterned process removal the 4th is conductive
Layer and third conductive layer form pixel electrode figure；
To the 4th conduction of region Partial exposure patterned process removal in pixel electrode area not including source drain region
Layer forms source-drain electrode.
Preferably, second conductive layer is copper.
Preferably, the 4th conductive layer is copper.
Preferably, first conductive layer and/or third conductive layer are IZO or ITO.
The third aspect, the present invention also provides a kind of display devices, including above-mentioned array substrate.
In array substrate provided by the invention and preparation method thereof, display device, in the public electrode for forming array substrate
When, the first conductive layer with the setting of public electrode same layer is formed, forms the second conductive layer, the first conductive layer on the first conductive layer
Grid is together constituted with the second conductive layer.The first conductive layer being formed simultaneously in the array substrate with public electrode and second
Conductive layer together constitutes grid, and the contact surface of substrate and the first conductive layer, the first conductive layer and the second conductive layer has preferably
Adhesiveness, while the first conductive layer prevent the second conductive layer made of metal to substrate spread, therefore, there is no need in order to
Increase the adhesiveness of the second conductive layer and substrate and specially make buffer layer, simplify the structure of array substrate, eliminates production
The process flow of buffer layer.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is this hair
Bright some embodiments for those of ordinary skill in the art without creative efforts, can be with root
Other attached drawings are obtained according to these attached drawings.
Fig. 1 is array base-plate structure schematic diagram provided in an embodiment of the present invention；
Fig. 2 is the formation signal of the first conductive layer and the second conductive layer in array substrate provided in an embodiment of the present invention
Figure；
Fig. 3 is the grid of array substrate provided in an embodiment of the present invention and the manufacture craft schematic diagram of public electrode；
Fig. 4 is the first insulating layer of array substrate provided in an embodiment of the present invention and the manufacture craft schematic diagram of active layer；
Fig. 5 is the via hole manufacture craft schematic diagram of array substrate provided in an embodiment of the present invention；
Fig. 6 is the first time exposure development technique in the source-drain electrode forming process of array substrate provided in an embodiment of the present invention
Schematic diagram；
Fig. 7 is showing for the first time etching technics in the source-drain electrode forming process of array substrate provided in an embodiment of the present invention
It is intended to；
Fig. 8 is the signal of the photoresist ashing in the source-drain electrode forming process of array substrate provided in an embodiment of the present invention
Figure；
Appended drawing reference: 101- public electrode, 102- grid, the first insulating layer of 103-, 104- active layer, 105- etch stopper
Layer, 106- second insulating layer, 107- pixel electrode, 108- source-drain electrode, 109- substrate, the first conductive layer of 201-, 202- second are led
Electric layer, 501- third conductive layer, 502- via hole, the 4th conductive layer of 601-, 602- photoresist layer.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
Every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
Fig. 1 is array base-plate structure schematic diagram provided in an embodiment of the present invention.Referring to Fig. 1, which includes film
Transistor and public electrode；
Thin film transistor (TFT) includes the grid 102, active layer 104, source-drain electrode 108 formed on substrate 109；
Grid 102 includes the first conductive layer and the second conductive layer；
First conductive layer and 101 same layer of public electrode；
Second conductive layer is metal.
First conductive layer and 101 same layer of public electrode are formed, can be while forming public electrode 101, by primary
Patterned process forms the first conductive layer.Second conductive layer is on the first conductive layer, since public electrode 101 is metal oxidation
Object, the first conductive layer are also metal oxide, and the second conductive layer is metal, are had between the first conductive layer and the second conductive layer
Adhesiveness, thereby it is ensured that the stability of array base-plate structure.
In array substrate provided in this embodiment, when forming public electrode 101, formation is set with 101 same layer of public electrode
The first conductive layer set, forms the second conductive layer on the first conductive layer, and the first conductive layer and the second conductive layer together constitute
Grid.In the array substrate, the first conductive layer and the second conductive layer being formed simultaneously with public electrode 101 together constitute grid
The contact surface of pole, substrate 109 and the first conductive layer, the first conductive layer and the second conductive layer has preferable adhesiveness, while
One conductive layer prevents the second conductive layer made of metal to spread to substrate 109, therefore, does not need specially in the second conduction
Buffer layer is made between layer and substrate 109 to increase the adhesiveness between the second conductive layer and substrate 109, simplifies array substrate
Structure, eliminate production buffer layer process flow.
Further, the array substrate further include:
The first insulating layer 103 is provided on grid；
Active layer 104 is provided on first insulating layer 103；
The figure of etching barrier layer 105 and second insulating layer 106 is provided on active layer 104；
Pixel electrode 107 is provided in second insulating layer 106；
Source-drain electrode 108 is overlapped on pixel electrode 107.
It will be appreciated that the first insulating layer 103 formed on grid covers the second conductive layer and public electrode 101.
In the present embodiment, pixel electrode 107 is formed in the second insulating layer 106 of 105 same layer of etching barrier layer, in pixel
Source-drain electrode 108 is formed on electrode 107.Pixel electrode layer 107 is metal oxide, and source-drain electrode 108 is metal, pixel electrode layer
The adhesiveness having had between 107 and source-drain electrode 108, meanwhile, pixel electrode 107 prevents source-drain electrode 108 made of metal
Diffusion to second insulating layer 106 therefore, there is no need to by making buffer layer between source-drain electrode 108 and second insulating layer 106
To increase the adhesiveness between source-drain electrode 108 and second insulating layer 106.Compared to existing needs in source-drain electrode 108 and second
Buffer layer is made between insulating layer 106 to increase the adhesiveness between source-drain electrode 108 and second insulating layer 106, the present embodiment mentions
The array base-plate structure of confession is simpler, and eliminates the technique that buffer layer is made between source-drain electrode 108 and second insulating layer 106
Process.
Further, source-drain electrode 108 is copper.
Compared to other metal materials, copper have lower resistivity, be suitable for powerful device.But due to copper with
The poor adhesion of glass needs to form buffer layer before forming copper electrode.Array substrate provided in this embodiment, using copper as
Two conductive layers form the second conductive layer on the first conductive layer formed with 101 same layer of public electrode, eliminate to guarantee
Adhesiveness between two conductive layers and substrate 109 and the technical process that buffer layer is made between the second conductive layer and substrate 109.
In addition, being needed before the source-drain electrode that formation in the prior art is made of copper due to the poor adhesion of copper and insulating layer
Buffer layer is initially formed between source-drain electrode and insulating layer.And in the present embodiment using copper as when source-drain electrode 108, directly in pixel
Source-drain electrode 108 is formed on electrode 107, is eliminated and is made buffer layer between second insulating layer 106 and source-drain electrode 108 to guarantee the
The technique of adhesiveness between two insulating layers 106 and source-drain electrode 108；In addition pixel electrode 107 prevents the source and drain being made of copper
Diffusion of the pole 108 to second insulating layer 106.
Further, since the first conductive layer material identical as 101 use of public electrode is formed, the second conductive layer is
Copper.First conductive layer can be formed with public electrode 101 by a patterned process, and process flow is simple.
Fig. 2 is the formation schematic diagram of the first conductive layer and the second conductive layer in array substrate provided in this embodiment, Fig. 3
It is the grid of array substrate provided in this embodiment and the manufacture craft schematic diagram of public electrode.Referring to figs. 2 and 3, the array
The production method of substrate, comprising:
After forming the first conductive layer 201 and the second conductive layer 202 in substrate 109, grid are formed by a patterning processes
Pole 102 and public electrode 101；
Wherein, for public electrode 101 using the formation of the first conductive layer 201, the second conductive layer 202 is metal.
Specifically, grid 102 is formed by a patterning processes and public electrode 101 includes:
To 202 half gray level mask patterned process of the first conductive layer 201 and the second conductive layer:
To second conductive layer 202 in 101 region Partial exposure patterned process of public electrode removal, 101 region of public electrode
Form 101 figure of public electrode；
Region except 102 region of grid and public electrode 101 is exposed completely, forms 102 figure of grid.
Specifically, as shown in Fig. 2, sequentially forming the first conductive layer 201 and the second conductive layer 202 on substrate 109；
Photoresist layer is formed on the second conductive layer 202.
Half gray level mask exposure-processed is carried out to the photoresist layer on the second conductive layer 202, by development, retains the firstth area
The photoresist in domain (the corresponding region of grid 102 in Fig. 3), part retains second area, and (public electrode 101 in Fig. 3 is corresponding
Region) photoresist, remove third region (grid 102 and public electrode in Fig. 3 except first area and second area
Region between 101) photoresist；
Etch away corresponding first conductive layer in third region and the second conductive layer；
The photoresist for removing second area, etches away corresponding second conductive layer 202 of second area, by second area pair
The first conductive layer answered is as public electrode 101；
The photoresist of first area is removed, to form grid 102.
In array substrate manufacturing method provided in this embodiment, the first conductive layer 201 and second is sequentially formed on substrate
Conductive layer 202, by the exposure of primary half gray level mask and twice etching technique, being formed, there is the first conductive layer 201 and second to lead
The grid 102 and public electrode 101 of electric layer 202 make between the grid and substrate of middle metal material compared with the prior art
The technique of buffer layer, array substrate manufacture craft provided in this embodiment eliminate the shape between the grid and substrate of metal material
At the technique of buffer layer.
Further, further includes:
The first insulating layer 103 and active layer 104 are formed on grid 102；
Second insulating layer 106 and third conductive layer 501 are formed on active layer 104, pass through a patterning processes, the company of being formed
It is connected with the via hole of active layer 104；
The 4th conductive layer 601 that connection active layer 104 is formed on third conductive layer 501, passes through a patterning processes, shape
At source-drain electrode 108 and pixel electrode 107.
Wherein, it by a patterning processes, forms source-drain electrode 108 and pixel electrode 107 includes:
To 601 half gray level mask patterned process of the 4th conductive layer:
Region in addition to 108 region of 107 region of pixel electrode and source-drain electrode is exposed completely, patterned process removal the
Four conductive layers 601 and third conductive layer 501 form 107 figure of pixel electrode；
Region Partial exposure patterned process removal the in 107 region of pixel electrode not including 108 region of source-drain electrode
Four conductive layers 601 form source-drain electrode 108.
Specifically, referring to fig. 4, the first insulating layer 103 and semiconductor layer are sequentially formed on grid 102；
104 figure of active layer is formed to semiconductor layer patterned process.
Specifically, the first insulating layer 103 and semiconductor layer are sequentially formed on grid 102；
Photoresist layer is formed on the semiconductor layer；
Processing is exposed to the photoresist layer on semiconductor layer, by development, retains the fourth region (active layer in Fig. 4
104 corresponding regions) photoresist, remove the fourth region except the 5th region (in addition to the corresponding area of active layer 104 in Fig. 4
Region except domain) photoresist；
The corresponding semiconductor layer in the 5th region is etched away, the photoresist of the fourth region is removed, forms active layer 104.
During forming active layer 104, by single exposure technique, one time etching technics forms active layer 104.
Fig. 5 is the via hole manufacture craft schematic diagram of array substrate provided in an embodiment of the present invention.Referring to Fig. 5, in active layer
Second insulating layer 106 and third conductive layer 501 are sequentially formed on 104；
To 501 patterned process of second insulating layer 106 and third conductive layer；
The third conductive layer 501 and second insulating layer 106 in the region of removal setting source-drain electrode 108, form connection active layer
104 via hole 502.
Specifically, second insulating layer 106 and third conductive layer 501 are sequentially formed on active layer 104；
Photoresist layer is formed on third conductive layer 501；
Processing is exposed to the photoresist layer on third conductive layer 501, by development, removes the 6th region (in Fig. 5
The corresponding region of via hole 502) photoresist, retain the 6th region except District 7 domain (the corresponding area of via hole 502 in Fig. 5
Region except domain) photoresist；
The corresponding third conductive layer 501 in the 6th region is etched away, to form the third conductive layer 501 of via hole 502；
Etch away the corresponding second insulating layer 106 in the 6th region, with formed etching barrier layer 105 be connected to active layer 104
Via hole 502；
The photoresist in District 7 domain is removed, to form source-drain electrode 108 on the third conductive layer 501 for form via hole 502,
And the third conductive layer 501 for foring via hole 502 is etched, form pixel electrode 107.
Array substrate manufacturing method provided in this embodiment sequentially forms second insulating layer 106 and third on active layer
Conductive layer 501 forms the via hole 502 for being connected to active layer by single exposure with twice etching technique, to be made by the via hole 502
Make the source-drain electrode 108 that connect with active layer 104, while source electrode can drain be produced on and be formed by metal oxide materials
On the pixel electrode 107 that third conductive layer 501 is formed, avoids source-drain electrode 108 and directly contact bring with second insulating layer 106
The bad problem of adhesiveness.
Fig. 6, Fig. 7 and Fig. 8 are showing for the technique in the source-drain electrode forming process of array substrate provided in this embodiment respectively
It is intended to.Referring to Fig. 6, Fig. 7 and Fig. 8, the 4th conductive layer 601 is formed on third conductive layer 501, to 601 half ash of the 4th conductive layer
The mask patterning processing of rank；
Include: to 601 half gray level mask patterned process of the 4th conductive layer
108 region of source-drain electrode is not exposed to form source-drain electrode figure；
Region in addition to 108 region of 107 region of pixel electrode and source-drain electrode is exposed completely, patterned process removal the
Four conductive layers 601 and third conductive layer 501 form pixel electrode figure；
Region Partial exposure patterned process removal the in 107 region of pixel electrode not including 108 region of source-drain electrode
Four conductive layers 601.
Specifically, source-drain electrode 108 is formed on the third conductive layer 501 for form via hole 502, and to foring via hole
502 third conductive layer 501 is etched, and is formed pixel electrode 107, is specifically included:
The 4th conductive layer 601 and photoresist layer 602 are sequentially formed on the third conductive layer 501 for foring via hole 502；
Half gray level mask exposure-processed is carried out to the photoresist layer 602 on the 4th conductive layer 601, by development, retains the
The photoresist in eight regions (region where photoresist in Fig. 8), part retain the 9th region and (are not present in Fig. 8 and deposit in Fig. 7
Photoresist) photoresist, remove the photoresist in the tenth region except Section Eight domain and the 9th region；
As shown in fig. 7, after etching away corresponding 4th conductive layer 601 in the tenth region, the corresponding formation in the tenth region of etching
The third conductive layer 501 of via hole 502, to form pixel electrode 107；
As shown in figure 8, carrying out photoresist that is thinned, and removing the 9th region to the photoresist in Section Eight domain, the is etched away
Corresponding 4th conductive layer 601 in nine regions, to form source-drain electrode 108.
Array substrate manufacturing method provided in this embodiment, by forming photoresist layer on the 4th conductive layer 601
602, the 4th conductive layer 601 and third conductive layer 501 are performed etching by half mask exposure technique, form 108 He of source-drain electrode
Pixel electrode 107.Buffer layer is made between source-drain electrode 108 and second insulating layer 106 to increase source compared to existing needs
Adhesiveness between drain electrode 108 and second insulating layer 106, array base-plate structure provided in this embodiment are eliminated in source-drain electrode
The technical process of buffer layer is made between 108 and second insulating layer 106.
Wherein, the second conductive layer 202 is copper, and the 4th conductive layer 601 is copper.
The first conductive layer 201 and/or third conductive layer 501 in the embodiment above is IZO or ITO.
In addition, substrate 109 can be formed using glass or PET, the first insulating layer 103 and second insulating layer 106 can
With using silica, perhaps silicon nitride forms being formed using IGZO or ITZO for active layer 104, source-drain electrode 108, grid
102 can be formed using copper.
The third aspect, the present embodiment additionally provide a kind of display device, including the array substrate in above embodiments.This is aobvious
Showing device includes the display panel of any one of the above embodiment, and display device can be with are as follows: liquid crystal display panel, mobile phone, tablet computer,
Any products or components having a display function such as television set, display, laptop, Digital Frame, navigator.By adopting
It not only can be reduced processing cost with the display device of above-mentioned display panel, the embodiment of the present invention, due to being not provided with buffering
Layer, can be effectively reduced the thickness with display device, is conducive to the lightening of product.
In display device provided in this embodiment, during making the array substrate of display device, array substrate is being formed
Public electrode 101 when, formed with 101 same layer of public electrode setting the first conductive layer, form second on the first conductive layer
Conductive layer, the first conductive layer and the second conductive layer together constitute grid.In the array substrate, with the shape simultaneously of public electrode 101
At the first conductive layer and the second conductive layer together constitute grid, substrate 109 and the first conductive layer, the first conductive layer and second
The contact surface of conductive layer has preferable adhesiveness, meanwhile, the first conductive layer prevents the second conductive layer to the expansion of substrate 109
It dissipates, therefore, there is no need to specially make buffer layer to increase the adhesiveness of the second conductive layer and substrate 109, simplify array
The structure of substrate eliminates the process flow of production buffer layer.
It should be noted that, in this document, relational terms such as first and second and the like are used merely to a reality
Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation
In any actual relationship or order or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to
Non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those
Element, but also including other elements that are not explicitly listed, or further include for this process, method, article or equipment
Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that
There is also other identical elements in process, method, article or equipment including the element.Term " on ", "lower" etc. refer to
The orientation or positional relationship shown is to be based on the orientation or positional relationship shown in the drawings, and is merely for convenience of the description present invention and simplifies
Description, rather than the device or element of indication or suggestion meaning must have a particular orientation, constructed and grasped with specific orientation
Make, therefore is not considered as limiting the invention.Unless otherwise clearly defined and limited, term " installation ", " connected ",
" connection " shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or be integrally connected；It can be
Mechanical connection, is also possible to be electrically connected；It can be directly connected, two can also be can be indirectly connected through an intermediary
Connection inside element.For the ordinary skill in the art, above-mentioned term can be understood at this as the case may be
Concrete meaning in invention.
In specification of the invention, numerous specific details are set forth.Although it is understood that the embodiment of the present invention can
To practice without these specific details.In some instances, well known method, structure and skill is not been shown in detail
Art, so as not to obscure the understanding of this specification.Similarly, it should be understood that disclose in order to simplify the present invention and helps to understand respectively
One or more of a inventive aspect, in the above description of the exemplary embodiment of the present invention, each spy of the invention
Sign is grouped together into a single embodiment, figure, or description thereof sometimes.However, should not be by the method solution of the disclosure
Release is in reflect an intention that i.e. the claimed invention requires more than feature expressly recited in each claim
More features.More precisely, as the following claims reflect, inventive aspect is less than single reality disclosed above
Apply all features of example.Therefore, it then follows thus claims of specific embodiment are expressly incorporated in the specific embodiment,
It is wherein each that the claims themselves are regarded as separate embodiments of the invention.It should be noted that in the absence of conflict, this
The feature in embodiment and embodiment in application can be combined with each other.The invention is not limited to any single aspect,
It is not limited to any single embodiment, is also not limited to any combination and/or displacement of these aspects and/or embodiment.And
And can be used alone each aspect and/or embodiment of the invention or with other one or more aspects and/or its implementation
Example is used in combination.
Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent
Pipe present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: its according to
So be possible to modify the technical solutions described in the foregoing embodiments, or to some or all of the technical features into
Row equivalent replacement；And these are modified or replaceed, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution
The range of scheme should all cover within the scope of the claims and the description of the invention.
Claims (11)
1. a kind of array substrate, which is characterized in that including thin film transistor (TFT) and public electrode；
The thin film transistor (TFT) includes the grid, active layer, source-drain electrode formed on substrate；
The grid includes the first conductive layer and the second conductive layer being stacked；
First conductive layer and the public electrode same layer；
Second conductive layer is metal；
The first insulating layer is provided on the grid；
Active layer is provided on first insulating layer；
Etching barrier layer and second insulating layer figure are provided on the active layer；
Pixel electrode is provided in the second insulating layer；
The source-drain electrode is overlapped on the pixel electrode.
2. array substrate according to claim 1, which is characterized in that the source and drain extremely copper.
3. array substrate according to claim 1, which is characterized in that first conductive layer and the public electrode use
Identical material is formed, and second conductive layer is copper.
4. a kind of production method of array substrate, for making array substrate as claimed in any one of claims 1-3, feature exists
In, comprising:
After the first conductive layer and the second conductive layer is formed on the substrate, grid and public electrode are formed by a patterning processes；
Wherein, the public electrode is formed using first conductive layer, and second conductive layer is metal.
5. according to the method described in claim 4, it is characterized in that, described pass through a patterning processes formation grid and common electrical
Pole includes:
To half gray level mask patterned process of first conductive layer and the second conductive layer:
Public electrode is formed to second conductive layer in public electrode region Partial exposure patterned process removal public electrode region
Figure；
Region except area of grid and public electrode is exposed completely, forms gate patterns.
6. method according to claim 4 or 5, which is characterized in that second conductive layer is copper.
7. according to the method described in claim 4, it is characterized by further comprising:
The first insulating layer and active layer are formed on the grid；
Second insulating layer and third conductive layer are formed on the active layer, and by a patterning processes, being formed has described in connection
The via hole of active layer；
The 4th conductive layer for connecting the active layer is formed on the third conductive layer, by a patterning processes, forms source
Drain electrode and pixel electrode.
8. forming source-drain electrode and picture the method according to the description of claim 7 is characterized in that described pass through a patterning processes
Plain electrode includes:
To half gray level mask patterned process of the 4th conductive layer:
Region in addition to pixel electrode area and source drain region is exposed completely, patterned process remove the 4th conductive layer and
Third conductive layer forms pixel electrode figure；
4th conductive layer shape is removed to the region Partial exposure patterned process in pixel electrode area not including source drain region
At source-drain electrode.
9. method according to claim 7 or 8, which is characterized in that the 4th conductive layer is copper.
10. method according to claim 7 or 8, which is characterized in that first conductive layer and/or third conductive layer are
IZO or ITO.
11. a kind of display device, which is characterized in that including array substrate described in claims 1 to 3.
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| CN106959536A (en) * | 2017-03-31 | 2017-07-18 | 上海中航光电子有限公司 | Display panel, the method and display device for making display panel |
| JP2019117342A (en) * | 2017-12-27 | 2019-07-18 | シャープ株式会社 | Active matrix substrate, manufacturing method therefor, and liquid crystal display device |
| CN109037241B (en) * | 2018-07-27 | 2021-10-08 | 武汉华星光电技术有限公司 | LTPS array substrate, manufacturing method thereof and display panel |
| CN109634000B (en) * | 2019-02-02 | 2021-12-31 | 合肥京东方显示技术有限公司 | Array substrate, preparation method thereof, display panel and display device |
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| CN102290421A (en) * | 2010-06-17 | 2011-12-21 | 三星移动显示器株式会社 | Flat panel display apparatus and method of manufacturing the same |
| CN102629570A (en) * | 2011-05-18 | 2012-08-08 | 京东方科技集团股份有限公司 | Array substrate of FFS type thin-film transistor liquid crystal display and method for manufacturing the same |
| CN104617115A (en) * | 2015-03-02 | 2015-05-13 | 深圳市华星光电技术有限公司 | FFS type thin film transistor array substrate and preparation method thereof |
| CN106024809A (en) * | 2016-07-07 | 2016-10-12 | 京东方科技集团股份有限公司 | Method for fabricating array substrate, array substrate and display device |
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| CN102290421A (en) * | 2010-06-17 | 2011-12-21 | 三星移动显示器株式会社 | Flat panel display apparatus and method of manufacturing the same |
| CN102629570A (en) * | 2011-05-18 | 2012-08-08 | 京东方科技集团股份有限公司 | Array substrate of FFS type thin-film transistor liquid crystal display and method for manufacturing the same |
| CN104617115A (en) * | 2015-03-02 | 2015-05-13 | 深圳市华星光电技术有限公司 | FFS type thin film transistor array substrate and preparation method thereof |
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