CN106098706A - A kind of array base palte and preparation method thereof, display device - Google Patents
A kind of array base palte and preparation method thereof, display device Download PDFInfo
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- CN106098706A CN106098706A CN201610585770.6A CN201610585770A CN106098706A CN 106098706 A CN106098706 A CN 106098706A CN 201610585770 A CN201610585770 A CN 201610585770A CN 106098706 A CN106098706 A CN 106098706A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
Abstract
In array base palte that the present invention provides and preparation method thereof, display device, wherein, this array base palte, including thin film transistor (TFT) and public electrode；Described thin film transistor (TFT) is included on substrate grid, active layer, source electrode and the drain electrode formed；Described grid includes the first conductive layer and the second conductive layer；Described first conductive layer and the same layer of described public electrode；Described second conductive layer is metal.Array base palte, when forming public electrode, forms the second conductive layer arranged with layer with public electrode, forms the first conductive layer, the first conductive layer and the second conductive layer and together constitute grid on the second conductive layer.In this array base palte, the first conductive layer is formed while forming public electrode, it is no need to increase the second conductive layer and the adhesiveness of substrate and between the second conductive layer and substrate, makes cushion specially, simplify the structure of array base palte, eliminate the technological process making cushion between the second conductive layer and substrate.
Description
Technical field
The invention belongs to Display Technique field, be specifically related to a kind of array base palte and preparation method thereof, display device.
Background technology
Liquid crystal indicator because having the advantages such as low in energy consumption, radiationless, occupied plane display field leadingly
Position.In existing liquid crystal indicator, liquid crystal panel generally includes the array base palte and color membrane substrates being oppositely arranged, and fills
Liquid crystal layer between array base palte and color membrane substrates, wherein, array base palte is provided with multiple thin film transistor (TFT) and multiple picture
Element electrode, pixel electrode is connected with the drain electrode of thin film transistor (TFT), is provided with the common electrical corresponding with pixel electrode on color membrane substrates
Pole.When being pixel electrode charging by thin film transistor (TFT), form electric field between pixel electrode and public electrode, thus can control
Liquid crystal molecule deflection in the liquid crystal region that pixel electrode is corresponding, and then realize crystal display.
In the manufacturing process of array base palte, metallic aluminium (Al) or metal molybdenum (Mo) can be as grid and the materials of source-drain electrode
Material.But for powerful display device, the high resistivity of Al or Mo can affect the propagation of the signal of telecommunication in display device,
And metal (Cu) has lower resistivity compared to Al or Mo, the substitution material of Al or Mo can be become.
But, the poor adhesion between Cu and glass, need at glass base in the manufacturing process of existing array base palte
First deposit one layer of cushion good with glass adhesion on plate, then Ni metal is deposited the most etched technique formation grid
Pole or source-drain electrode.This employing Ni metal forms the manufacturing process of the array base palte of grid or source-drain electrode, needs by cushion
Being sticked to by Ni metal on glass or insulating barrier, array base-plate structure is complicated, and the technological process that array base palte makes is loaded down with trivial details.
Summary of the invention
The technical problem to be solved is structure and the technique of array base palte making how simplifying array base palte
Flow process.
For this technical problem, the invention provides a kind of array base palte, including thin film transistor (TFT) and public electrode；
Described thin film transistor (TFT) is included on substrate the grid of formation, active layer, source-drain electrode；
Described grid includes the first conductive layer and the second conductive layer；
Described first conductive layer and the same layer of described public electrode；
Described second conductive layer is metal.
Preferably, also include:
The first insulating barrier it is provided with on described grid；
It is provided with active layer on described first insulating barrier；
Etching barrier layer and the second layer pattern it is provided with on described active layer；
It is provided with pixel electrode on described second insulating barrier；
Described source-drain electrode is overlapped on described pixel electrode.
Preferably, described source and drain extremely copper.
Preferably, described first conductive layer is formed with the described identical material of public electrode employing, and described second conductive layer is
Copper.
Second aspect, present invention also offers the manufacture method of a kind of array base palte, including:
After substrate is formed the first conductive layer and the second conductive layer, form grid and common electrical by a patterning processes
Pole；
Wherein, described public electrode uses described first conductive layer to be formed, and described second conductive layer is metal.
Preferably, described grid is formed by patterning processes and public electrode includes:
To described first conductive layer and the second conductive layer half gray level mask patterned process:
The second conductive layer that public electrode region Partial exposure patterned process is removed public electrode region is formed public
Electrode pattern；
Region outside area of grid and public electrode is exposed completely, forms gate patterns.
Preferably, also include:
Described grid is formed the first insulating barrier and active layer；
Described active layer is formed the second insulating barrier and the 3rd conductive layer, by a patterning processes, forms connection institute
State the via of active layer；
Described 3rd conductive layer forms the 4th conductive layer connecting described active layer, by a patterning processes, shape
Become source-drain electrode and pixel electrode.
Preferably, described pass through a patterning processes, form source-drain electrode and pixel electrode includes:
To the 4th conductive layer half gray level mask patterned process:
Exposing the region in addition to pixel electrode area and source drain region completely, patterned process removes the 4th conduction
Layer and the 3rd conductive layer, form pixel electrode figure；
The region Partial exposure patterned process not including source drain region in pixel electrode area is removed the 4th conduction
Layer forms source-drain electrode.
Preferably, described second conductive layer is copper.
Preferably, described 4th conductive layer is copper.
Preferably, described first conductive layer and/or the 3rd conductive layer are IZO or ITO.
The third aspect, present invention also offers a kind of display device, including above-mentioned array base palte.
In array base palte that the present invention provides and preparation method thereof, display device, at the public electrode forming array base palte
Time, form the first conductive layer arranged with layer with public electrode, the first conductive layer is formed the second conductive layer, the first conductive layer
Grid is together constituted with the second conductive layer.In this array base palte, the first conductive layer and second concurrently formed with public electrode
Conductive layer together constitutes grid, and the contact surface of substrate and the first conductive layer, the first conductive layer and the second conductive layer all has preferably
Adhesiveness, the first conductive layer prevents the second conductive layer of being made of metal to spread to substrate simultaneously, therefore, there is no need in order to
Increase the adhesiveness of the second conductive layer and substrate and make cushion specially, simplify the structure of array base palte, eliminate making
The technological process of cushion.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
In having technology to describe, the required accompanying drawing used is briefly described, it should be apparent that, the accompanying drawing in describing below is this
Some bright embodiments, for those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to root
Other accompanying drawing is obtained according to these accompanying drawings.
Fig. 1 is the array base-plate structure schematic diagram that the embodiment of the present invention provides；
Fig. 2 is the formation signal of the first conductive layer in the array base palte that the embodiment of the present invention provides and the second conductive layer
Figure；
Fig. 3 is grid and the processing technology schematic diagram of public electrode of the array base palte that the embodiment of the present invention provides；
Fig. 4 is the first insulating barrier and the processing technology schematic diagram of active layer of the array base palte that the embodiment of the present invention provides；
Fig. 5 is the via processing technology schematic diagram of the array base palte that the embodiment of the present invention provides；
Fig. 6 is the first time exposure imaging technique in the source-drain electrode forming process of the array base palte that the embodiment of the present invention provides
Schematic diagram；
Fig. 7 is showing of the first time etching technics in the source-drain electrode forming process of the array base palte that the embodiment of the present invention provides
It is intended to；
Fig. 8 is the signal of the photoresist ashing in the source-drain electrode forming process of the array base palte that the embodiment of the present invention provides
Figure；
Reference: 101-public electrode, 102-grid, 103-the first insulating barrier, 104-active layer, 105-etch stopper
Layer, 106-the second insulating barrier, 107-pixel electrode, 108-source-drain electrode, 109-substrate, 201-the first conductive layer, 202-second leads
Electric layer, 501-the 3rd conductive layer, 502-via, 601-the 4th conductive layer, 602-photoresist layer.
Detailed description of the invention
For making the purpose of the embodiment of the present invention, technical scheme and advantage clearer, below in conjunction with the embodiment of the present invention
In accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is
The a part of embodiment of the present invention rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art
The every other embodiment obtained under not making creative work premise, broadly falls into the scope of protection of the invention.
Fig. 1 is the array base-plate structure schematic diagram that the embodiment of the present invention provides.Seeing Fig. 1, this array base palte includes thin film
Transistor and public electrode；
Thin film transistor (TFT) is included on substrate 109 grid 102 of formation, active layer 104, source-drain electrode 108；
Grid 102 includes the first conductive layer and the second conductive layer；
First conductive layer and the same layer of public electrode 101；
Second conductive layer is metal.
First conductive layer and public electrode 101 are formed with layer, can be while forming public electrode 101, by once
Patterned process forms the first conductive layer.Second conductive layer is on the first conductive layer, owing to public electrode 101 is burning
Thing, the first conductive layer is also metal-oxide, and the second conductive layer is metal, has between the first conductive layer and the second conductive layer
Adhesiveness, thereby it is ensured that the stability of array base-plate structure.
In the array base palte that the present embodiment provides, when forming public electrode 101, formed and set with layer with public electrode 101
The first conductive layer put, forms the second conductive layer, the first conductive layer and the second conductive layer on the first conductive layer and together constitutes
Grid.In this array base palte, the first conductive layer and the second conductive layer that concurrently form with public electrode 101 together constitute grid
Pole, the contact surface of substrate 109 and the first conductive layer, the first conductive layer and the second conductive layer all has a preferable adhesiveness, and simultaneously
One conductive layer prevents the second conductive layer being made of metal to spread to substrate 109, therefore, is not required to specially in the second conduction
Make cushion between layer and substrate 109 and increase the adhesiveness between the second conductive layer and substrate 109, simplify array base palte
Structure, eliminate make cushion technological process.
Further, this array base palte also includes:
The first insulating barrier 103 it is provided with on grid；
It is provided with active layer 104 on first insulating barrier 103；
Etching barrier layer 105 and the figure of the second insulating barrier 106 it is provided with on active layer 104；
It is provided with pixel electrode 107 on second insulating barrier 106；
Source-drain electrode 108 is overlapped on pixel electrode 107.
It will be appreciated that the first insulating barrier 103 formed on grid covers the second conductive layer and public electrode 101.
In the present embodiment, at etching barrier layer 105 with forming pixel electrode 107 on the second insulating barrier 106 of layer, in pixel
Source-drain electrode 108 is formed on electrode 107.Pixel electrode layer 107 is metal-oxide, and source-drain electrode 108 is metal, pixel electrode layer
The adhesiveness having had between 107 and source-drain electrode 108, meanwhile, pixel electrode 107 prevents the source-drain electrode 108 being made of metal
To the diffusion of the second insulating barrier 106, therefore, there is no need to by making cushion between source-drain electrode 108 and the second insulating barrier 106
Increase the adhesiveness between source-drain electrode 108 and the second insulating barrier 106.Compared to existing needs at source-drain electrode 108 and second
Between insulating barrier 106, making cushion is to increase the adhesiveness between source-drain electrode 108 and the second insulating barrier 106, and the present embodiment carries
The array base-plate structure of confession is simpler, and eliminates the technique making cushion between source-drain electrode 108 and the second insulating barrier 106
Process.
Further, source-drain electrode 108 is copper.
Comparing and other metal material, copper has lower resistivity, it is adaptable to powerful device.But due to copper with
The poor adhesion of glass, needs to be formed cushion before forming copper electrode.The array base palte that the present embodiment provides, using copper as the
Two conductive layers, form the second conductive layer on the first conductive layer formed with layer with public electrode 101, eliminate to ensure
Adhesiveness between two conductive layers and substrate 109 and between the second conductive layer and substrate 109, make the technical process of cushion.
Further, since copper and the poor adhesion of insulating barrier, need before the source-drain electrode that formation copper does in the prior art
Cushion it is initially formed between source-drain electrode and insulating barrier.And in the present embodiment using copper as source-drain electrode 108 time, directly in pixel
Form source-drain electrode 108 on electrode 107, eliminate and between the second insulating barrier 106 and source-drain electrode 108, make cushion to ensure the
The technique of the adhesiveness between two insulating barriers 106 and source-drain electrode 108；Additionally pixel electrode 107 prevents the source and drain being made of copper
Pole 108 is to the diffusion of the second insulating barrier 106.
Further, owing to the first conductive layer and public electrode 101 use identical material to be formed, the second conductive layer is
Copper.First conductive layer can be formed by a patterned process with public electrode 101, and technological process is simple.
Fig. 2 is the first conductive layer in the array base palte that the present embodiment provides and the formation schematic diagram of the second conductive layer, Fig. 3
It is grid and the processing technology schematic diagram of public electrode of the array base palte that the present embodiment provides.See Fig. 2 and Fig. 3, this array
The manufacture method of substrate, including:
After substrate 109 is formed the first conductive layer 201 and the second conductive layer 202, form grid by a patterning processes
Pole 102 and public electrode 101；
Wherein, public electrode 101 uses the first conductive layer 201 to be formed, and the second conductive layer 202 is metal.
Specifically, included by a patterning processes formation grid 102 and public electrode 101:
To the first conductive layer 201 and the second conductive layer 202 half gray level mask patterned process:
Public electrode 101 region Partial exposure patterned process is removed second conductive layer 202 in public electrode 101 region
Form public electrode 101 figure；
Region outside grid 102 region and public electrode 101 is exposed completely, forms grid 102 figure.
Specifically, as in figure 2 it is shown, sequentially form the first conductive layer 201 and the second conductive layer 202 on substrate 109；
Second conductive layer 202 is formed photoresist layer.
Photoresist layer on second conductive layer 202 is carried out half gray level mask exposure-processed, by development, retains the firstth district
The photoresist in territory (region of grid 102 correspondence in Fig. 3), part retains second area, and (public electrode 101 in Fig. 3 is corresponding
Region) photoresist, remove the 3rd region (grid 102 in Fig. 3 and the public electrode outside first area and second area
Region between 101) photoresist；
Etch away the first conductive layer corresponding to the 3rd region and the second conductive layer；
Remove the photoresist of second area, etch away the second conductive layer 202 that second area is corresponding, with by second area pair
The first conductive layer answered is as public electrode 101；
Remove the photoresist of first area, to form grid 102.
In the array substrate manufacturing method that the present embodiment provides, substrate sequentially forms the first conductive layer 201 and second
Conductive layer 202, by once half gray level mask exposure and twice etching technique, formation has the first conductive layer 201 and second and leads
The grid 102 of electric layer 202, and public electrode 101, make between grid and the substrate of metal material compared in prior art
The technique of cushion, the array base palte processing technology that the present embodiment provides eliminates shape between the grid and substrate of metal material
The technique becoming cushion.
Further, also include:
Grid 102 is formed the first insulating barrier 103 and active layer 104；
Active layer 104 is formed the second insulating barrier 106 and the 3rd conductive layer 501, by a patterning processes, the company of being formed
It is connected with the via of active layer 104；
3rd conductive layer 501 forms the 4th conductive layer 601 connecting active layer 104, by a patterning processes, shape
Become source-drain electrode 108 and pixel electrode 107.
Wherein, by a patterning processes, form source-drain electrode 108 and pixel electrode 107 include:
To the 4th conductive layer 601 half gray level mask patterned process:
Exposing the region in addition to pixel electrode 107 region and source-drain electrode 108 region completely, patterned process removes the
Four conductive layer 601 and the 3rd conductive layers 501, form pixel electrode 107 figure；
The region Partial exposure patterned process not including source-drain electrode 108 region in pixel electrode 107 region is removed the
Four conductive layers 601 form source-drain electrode 108.
Specifically, see Fig. 4, grid 102 sequentially forms the first insulating barrier 103 and semiconductor layer；
Quasiconductor pattern layers is processed and is formed with active layer 104 figure.
Specifically, grid 102 sequentially forms the first insulating barrier 103 and semiconductor layer；
Form photoresist layer on the semiconductor layer；
It is exposed the photoresist layer on semiconductor layer processing, by development, retains the 4th region (active layer in Fig. 4
The region of 104 correspondences) photoresist, remove the 5th region outside the 4th region (except the district of active layer 104 correspondence in Fig. 4
Region outside territory) photoresist；
Etch away the semiconductor layer that the 5th region is corresponding, remove four-range photoresist, be formed with active layer 104.
During being formed with active layer 104, by single exposure technique, one time etching technics is formed with active layer 104.
Fig. 5 is the via processing technology schematic diagram of the array base palte that the embodiment of the present invention provides.See Fig. 5, at active layer
The second insulating barrier 106 and the 3rd conductive layer 501 is sequentially formed on 104；
To the second insulating barrier 106 and the 3rd conductive layer 501 patterned process；
Remove the 3rd conductive layer 501 and second insulating barrier 106 in the region that source-drain electrode 108 is set, formed and be communicated with active layer
The via 502 of 104.
Specifically, active layer 104 sequentially forms the second insulating barrier 106 and the 3rd conductive layer 501；
3rd conductive layer 501 is formed photoresist layer；
It is exposed the photoresist layer on the 3rd conductive layer 501 processing, by development, removes the 6th region (in Fig. 5
The region of via 502 correspondence) photoresist, retain (the district of via 502 correspondence in Fig. 5, SECTOR-SEVEN territory outside the 6th region
Region outside territory) photoresist；
Etch away the 3rd conductive layer 501 that the 6th region is corresponding, to define the 3rd conductive layer 501 of via 502；
Etch away the second insulating barrier 106 that the 6th region is corresponding, to form etching barrier layer 105 and to be communicated with active layer 104
Via 502；
Remove the photoresist in SECTOR-SEVEN territory, to form source-drain electrode 108 on the 3rd conductive layer 501 define via 502,
And the 3rd conductive layer 501 defining via 502 is etched, form pixel electrode 107.
The array substrate manufacturing method that the present embodiment provides, sequentially forms the second insulating barrier 106 and the 3rd on active layer
Conductive layer 501, forms the via 502 being communicated with active layer, to be made by this via 502 by single exposure and twice etching technique
Making the source-drain electrode 108 that is connected with active layer 104, source electrode can drain to be produced on and be formed by metal oxide materials simultaneously
On the pixel electrode 107 that 3rd conductive layer 501 is formed, it is to avoid source-drain electrode 108 directly contacts with the second insulating barrier 106 and to bring
The problem that adhesiveness is bad.
Fig. 6, Fig. 7 and Fig. 8 are showing of the technique in the source-drain electrode forming process of the array base palte that the present embodiment provides respectively
It is intended to.See Fig. 6, Fig. 7 and Fig. 8, the 3rd conductive layer 501 is formed the 4th conductive layer 601, to the 4th conductive layer 601 half ash
The mask patterning process in rank；
4th conductive layer 601 half gray level mask patterned process is included:
Source-drain electrode 108 region is not exposed formation source-drain electrode figure；
Exposing the region in addition to pixel electrode 107 region and source-drain electrode 108 region completely, patterned process removes the
Four conductive layer 601 and the 3rd conductive layers 501, form pixel electrode figure；
The region Partial exposure patterned process not including source-drain electrode 108 region in pixel electrode 107 region is removed the
Four conductive layers 601.
Specifically, the 3rd conductive layer 501 define via 502 forms source-drain electrode 108, and to defining via
3rd conductive layer 501 of 502 is etched, and forms pixel electrode 107, specifically includes:
The 3rd conductive layer 501 define via 502 sequentially forms the 4th conductive layer 601 and photoresist layer 602；
Photoresist layer 602 on 4th conductive layer 601 is carried out half gray level mask exposure-processed, by development, retains the
The photoresist in eight regions (region at the photoresist place in Fig. 8), part retains the 9th region and (does not exists in Fig. 8 and deposit in Fig. 7
Photoresist) photoresist, remove the photoresist in the tenth region outside Section Eight territory and the 9th region；
As it is shown in fig. 7, after etching away the 4th conductive layer 601 that the tenth region is corresponding, the formation that etching the tenth region is corresponding
3rd conductive layer 501 of via 502, forming pixel electrode 107；
As shown in Figure 8, the photoresist in Section Eight territory is carried out thinning, and removes the photoresist in the 9th region, etch away
The 4th conductive layer 601 that nine regions are corresponding, to form source-drain electrode 108.
The array substrate manufacturing method that the present embodiment provides, by forming photoresist layer on the 4th conductive layer 601
602, by half mask exposure technique, the 4th conductive layer 601 and the 3rd conductive layer 501 are performed etching, form source-drain electrode 108 He
Pixel electrode 107.Between source-drain electrode 108 and the second insulating barrier 106, cushion is made to increase source compared to existing needs
Adhesiveness between drain electrode 108 and the second insulating barrier 106, the array base-plate structure that the present embodiment provides eliminates at source-drain electrode
108 and second technical processs making cushion between insulating barrier 106.
Wherein, the second conductive layer 202 is copper, and the 4th conductive layer 601 is copper.
The first conductive layer 201 and/or the 3rd conductive layer 501 in the embodiment above are IZO or ITO.
Additionally, can use glass or the PET of substrate 109 are formed, the first insulating barrier 103 and the second insulating barrier 106 can
To use silicon oxide or silicon nitride to be formed, IGZO or ITZO that can use of active layer 104 is formed, source-drain electrode 108, grid
102 can use copper to be formed.
The third aspect, the present embodiment additionally provides a kind of display device, including the array base palte in above example.This shows
Showing device includes the display floater of any one embodiment above-mentioned, and display device can be: liquid crystal panel, mobile phone, panel computer,
Any product with display function or the parts such as television set, display, notebook computer, DPF, navigator.By adopting
Using above-mentioned display floater, the display device of the embodiment of the present invention is possible not only to reduce processing cost, owing to being not provided with buffering
Layer, can effectively reduce the lightening of the thickness with display device, beneficially product.
In the display device that the present embodiment provides, during making the array base palte of display device, forming array base palte
Public electrode 101 time, form the first conductive layer arranged with public electrode 101 with layer, formation second on the first conductive layer
Conductive layer, the first conductive layer and the second conductive layer together constitute grid.In this array base palte, with public electrode 101 shape simultaneously
The first conductive layer and the second conductive layer that become together constitute grid, substrate 109 and the first conductive layer, the first conductive layer and second
The contact surface of conductive layer all has preferable adhesiveness, and meanwhile, the first conductive layer prevents the second conductive layer to the expansion of substrate 109
Dissipate, therefore, there is no need to make cushion specially to increase the adhesiveness of the second conductive layer and substrate 109, simplify array
The structure of substrate, eliminates the technological process making cushion.
It should be noted that in this article, the relational terms of such as first and second or the like is used merely to a reality
Body or operation separate with another entity or operating space, and deposit between not necessarily requiring or imply these entities or operating
Relation or order in any this reality.And, term " includes ", " comprising " or its any other variant are intended to
Comprising of nonexcludability, so that include that the process of a series of key element, method, article or equipment not only include that those are wanted
Element, but also include other key elements being not expressly set out, or also include for this process, method, article or equipment
Intrinsic key element.In the case of there is no more restriction, statement " including ... " key element limited, it is not excluded that
Including process, method, article or the equipment of described key element there is also other identical element.Term " on ", D score etc. refers to
The orientation shown or position relationship, for based on orientation shown in the drawings or position relationship, are for only for ease of the description present invention and simplification
Describe rather than indicate or imply that the device of indication or element must have specific orientation, with specific azimuth configuration and behaviour
Make, be therefore not considered as limiting the invention.Unless otherwise clearly defined and limited, term " install ", " being connected ",
" connect " and should be interpreted broadly, connect for example, it may be fixing, it is also possible to be to removably connect, or be integrally connected；Can be
It is mechanically connected, it is also possible to be electrical connection；Can be to be joined directly together, it is also possible to be indirectly connected to by intermediary, can be two
The connection of element internal.For the ordinary skill in the art, can understand that above-mentioned term is at this as the case may be
Concrete meaning in invention.
In the description of the present invention, illustrate a large amount of detail.Although it is understood that, embodiments of the invention can
To put into practice in the case of there is no these details.In some instances, it is not shown specifically known method, structure and skill
Art, in order to do not obscure the understanding of this description.Similarly, it will be appreciated that disclose to simplify the present invention and help to understand respectively
One or more in individual inventive aspect, above in the description of the exemplary embodiment of the present invention, each of the present invention is special
Levy and be sometimes grouped together in single embodiment, figure or descriptions thereof.But, should be by the method solution of the disclosure
Release in reflecting an intention that i.e. the present invention for required protection requires than the feature being expressly recited in each claim more
Many features.More precisely, as the following claims reflect, inventive aspect is less than single reality disclosed above
Execute all features of example.Therefore, it then follows claims of detailed description of the invention are thus expressly incorporated in this detailed description of the invention,
The most each claim itself is as the independent embodiment of the present invention.It should be noted that in the case of not conflicting, this
Embodiment in application and the feature in embodiment can be mutually combined.The invention is not limited in any single aspect, also
It is not limited to any single embodiment, is also not limited to these aspects and/or the combination in any of embodiment and/or displacement.And
And, can be used alone each aspect of the present invention and/or embodiment or with other aspects one or more and/or its implement
Example is used in combination.
Last it is noted that various embodiments above is only in order to illustrate technical scheme, it is not intended to limit；To the greatest extent
The present invention has been described in detail by pipe with reference to foregoing embodiments, it will be understood by those within the art that: it depends on
So the technical scheme described in foregoing embodiments can be modified, or the most some or all of technical characteristic is entered
Row equivalent；And these amendments or replacement, do not make the essence of appropriate technical solution depart from various embodiments of the present invention technology
The scope of scheme, it all should be contained in the middle of the claim of the present invention and the scope of description.
Claims (12)
1. an array base palte, it is characterised in that include thin film transistor (TFT) and public electrode；
Described thin film transistor (TFT) is included on substrate the grid of formation, active layer, source-drain electrode；
Described grid includes the first conductive layer and the second conductive layer that stacking arranges；
Described first conductive layer and the same layer of described public electrode；
Described second conductive layer is metal.
Array base palte the most according to claim 1, it is characterised in that also include:
The first insulating barrier it is provided with on described grid；
It is provided with active layer on described first insulating barrier；
Etching barrier layer and the second layer pattern it is provided with on described active layer；
It is provided with pixel electrode on described second insulating barrier；
Described source-drain electrode is overlapped on described pixel electrode.
Array base palte the most according to claim 1 and 2, it is characterised in that described source and drain extremely copper.
Array base palte the most according to claim 1, it is characterised in that described first conductive layer uses with described public electrode
Identical material is formed, and described second conductive layer is copper.
5. the manufacture method of an array base palte, it is characterised in that including:
After substrate is formed the first conductive layer and the second conductive layer, form grid and public electrode by a patterning processes；
Wherein, described public electrode uses described first conductive layer to be formed, and described second conductive layer is metal.
Method the most according to claim 5, it is characterised in that described pass through patterning processes and form grid and common electrical
Pole includes:
To described first conductive layer and the second conductive layer half gray level mask patterned process:
The second conductive layer that public electrode region Partial exposure patterned process is removed public electrode region forms public electrode
Figure；
Region outside area of grid and public electrode is exposed completely, forms gate patterns.
7. according to the method described in claim 5 or 6, it is characterised in that described second conductive layer is copper.
Method the most according to claim 5, it is characterised in that also include:
Described grid is formed the first insulating barrier and active layer；
Described active layer is formed the second insulating barrier and the 3rd conductive layer, by a patterning processes, is formed and have described in connection
The via of active layer；
Described 3rd conductive layer is formed the 4th conductive layer connecting described active layer, by a patterning processes, forms source
Drain electrode and pixel electrode.
Method the most according to claim 8, it is characterised in that described pass through a patterning processes, forms source-drain electrode and picture
Element electrode includes:
To the 4th conductive layer half gray level mask patterned process:
Region in addition to pixel electrode area and source drain region is exposed completely, patterned process remove the 4th conductive layer and
3rd conductive layer, forms pixel electrode figure；
The region Partial exposure patterned process not including source drain region in pixel electrode area is removed the 4th conductive layer shape
Become source-drain electrode.
Method the most according to claim 8 or claim 9, it is characterised in that described 4th conductive layer is copper.
11. methods according to claim 8 or claim 9, it is characterised in that described first conductive layer and/or the 3rd conductive layer are
IZO or ITO.
12. 1 kinds of display devices, it is characterised in that include the array base palte described in Claims 1-4.
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