TWI753990B - 用於支持來自未終結端點之雙向發信之程式化接墊 - Google Patents

用於支持來自未終結端點之雙向發信之程式化接墊 Download PDF

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TWI753990B
TWI753990B TW107101940A TW107101940A TWI753990B TW I753990 B TWI753990 B TW I753990B TW 107101940 A TW107101940 A TW 107101940A TW 107101940 A TW107101940 A TW 107101940A TW I753990 B TWI753990 B TW I753990B
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unterminated
switch
die
pad
capacitor
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TW107101940A
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TW201832410A (zh
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史考特 波爾斯
湯瑪士 布萊恩
安德魯 托麥可
蘇伯拉曼亞 普雷迪普 莫魯蘇帕里
婷婷 衛
肯尼斯 杜鮑斯基
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美商高通公司
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
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    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
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    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
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    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

本發明提供一種晶粒，其具有一未終結端點，該未終結端點在充當一接收端點時藉由來自電容器之一電容對其輸入阻抗進行電容性加載且在充當一傳輸端點時隔離其輸出阻抗與該電容。

Description

用於支持來自未終結端點之雙向發信之程式化接墊
本申請案係關於晶粒間介面，且更特定而言，係關於一種用於支援未終結雙向晶粒間發信之可程式化接墊電容。
為防止經由傳輸線耦接的傳輸器與接收器之間的反射，習知地每一端點使其阻抗與傳輸線阻抗匹配。舉例而言，共同傳輸線阻抗係50 Ω，使得每一端點亦將向傳輸線呈現匹配的50 Ω阻抗。由於信號之上升邊緣或下降邊緣自傳輸器沿傳輸線往下傳播至具有此匹配阻抗之接收器，因此傳輸線與接收器端點之間不存在阻抗不連續性使得不存在信號邊緣之反射。但所匹配負載耦接至接地且因此耗散電力，其在諸如智慧型手機或平板電腦之電池操作式裝置中成問題。為節省電力，習知地，晶片間介面在行動應用中未終結。舉例而言，智慧型手機將通常包括充當智慧型手機之「大腦」的系統單晶片(SoC)。SoC通常與一或多個動態隨機存取記憶體(DRAM)一起封裝。為節省電力，已針對使用未終結端點之SoC/DRAM介面開發出各種低功率雙資料速率(LPDDR)通信協定。 儘管功率消耗減少，但用於SoC及DRAM之未終結端點引起信號邊緣在接收時之反射。舉例而言，假設未終結端點正接收二進位高信號，其後接著二進位0傳輸。二進位1信號之上升邊緣將自接收端點反射回至傳輸端點，該傳輸端點又將所反射信號重新反射回至接收端點，等等，此現象本文中指示為「回鈴(ringback)」。回鈴雜訊可因此引起接收端點處之位元錯誤，尤其在存在諸如鄰近傳輸線之間的串擾的其他雜訊源之情況下。為防止位元錯誤，可重新設計傳輸線以降低串擾。但減少串擾之此類技術增加製造成本。 因此，此項技術中需要減少回鈴之改良的雙向未終結端點。
為提供提高的接收信號品質，提供未終結端點，其包括經由電容器及開關耦接至接地之接墊(其亦可表示為端點端子)。在一回鈴減少操作模式下，一控制器在該未終結端點用以經由端點接墊接收信號時控制該開關閉合。該開關在該回鈴減少操作模式期間之該閉合藉由來自該電容器之一電容對該未終結端點之一輸入阻抗進行加載。相反，在該未終結端點用以經由該端點接墊傳輸信號時，該控制器斷開該開關。該開關之該斷開防止藉由來自該電容器之該電容對該未終結端點之一輸出阻抗進行的一加載。 若在該回鈴減少操作模式不處於作用中時該未終結端點用以接收信號，則該控制器不閉合該開關以免藉由該電容對該未終結端點之該輸入阻抗進行加載。舉例而言，該控制器可比較資料速率與一臨限值以辨別該回鈴減少操作模式是否在作用中。在低於該臨限值之資料速率下，該資料速率使得在連續資料位元之傳輸之間，回鈴雜訊得到充分解決。相反，隨著該資料速率增加至超過該臨限值，在連續資料位元傳輸之間，回鈴雜訊將未得到充分解決使得該控制器閉合該開關以減弱該回鈴雜訊。在信號接收期間電容至端點輸入阻抗之所得選擇性添加係相當有利的，此係因為所接收信號之上升及下降邊緣自端點接墊的反射由於電容器自信號上升邊緣接收電荷且將電荷放電至信號下降邊緣而得以緩解。因此，自一接收端點至一傳輸端點之回鈴實質上減少，藉此減小位元錯誤速率。儘管添加的電容減少自接收端點之回鈴，但其將傾向於加重傳輸端點處之反射。該電容器僅在該端點充當一接收器時之選擇性連接因此相當有利。 經由以下實施方式可較佳地瞭解此等及其他有利特徵。
為減少自接收端點之回鈴，經由開關藉由電容對未終結端點之接墊進行加載，該開關係藉由控制器啟動。在回鈴減少操作模式下，在未終結端點充當接收端點時，控制器閉合開關以經由電容器將接墊耦接至接地使得藉由電容器之電容對未終結端點之輸入阻抗進行加載。若未終結端點接著充當傳輸端點(或充當接收端點，其中回鈴減少操作模式不在作用中)，則該控制器斷開開關使得未終結端點之輸出阻抗不由該電容器進行加載。 現轉向圖式，實例未終結端點100展示於圖 1 中。如本文中所使用，術語端點可與輸入/輸出(I/O)電路互換使用。未終結端點100包括用於包括未終結端點100之主機晶粒(未圖示)的接墊105。接墊105係用於主機晶粒之I/O端子的一般表示，諸如主機晶粒用以連接至外部傳輸線120之實際接墊或接腳。遠端晶粒(未圖示)包括類似端點以經由外部傳輸線120與主機晶粒通信。外部傳輸線120經組態以具有諸如50 Ω之特性阻抗。如其名稱所暗示，未終結端點100不經由耦接於接墊105與接地之間的任何類別之電阻器來匹配此特性阻抗，以防止否則將經由此電阻器發生之功率損失。未終結端點100係雙向的，使得其既可在接墊105處自外部傳輸線120接收信號，且亦可經由接墊105傳輸信號以沿外部傳輸線120往下傳播至遠端晶粒。因此，未終結端點100包括用於自接墊105接收信號之接收器115以及用於經由接墊105將信號驅動至外部傳輸線120之驅動器110。 遠端晶粒藉由將傳輸線120充電至二進位高電壓或藉由使外部傳輸線120接地來經由外部傳輸線120將二進位信號傳輸至未終結端點100。在其他實施例中，外部傳輸線120可係差分傳輸線之部分，但在不失一般性的情況下，以下論述將假定經由外部傳輸線120之通信係單端的。在此單端傳輸中，自遠端晶粒傳輸二進位1位元，其後接著傳輸二進位0，此導致在接墊105處接收到上升邊緣，使得接墊之電壓自接地驟然升高至二進位高電壓。由於未終結端點100之輸入阻抗相較於外部傳輸線120之特性阻抗的不連續性，上升邊緣將傾向於自未終結端點100反射且沿外部傳輸線120往下傳播至遠端晶粒，此作為如較早所論述之表示為「回鈴」的現象之部分。類似地，自遠端晶粒傳輸二進位0，其後接著傳輸二進位1位元，此導致在接墊105處接收到下降邊緣，使得接墊之電壓自二進位高電壓驟然下降至接地。接墊105處之阻抗不連續性將類似地傾向於經由外部傳輸通道120將下降邊緣反射回至遠端晶粒。 為實質上減少此回鈴而不管阻抗不連續性，未終結端點100包括連接於接墊105與開關S1之間的電容器C1，該開關又連接至接地。在替代實施例中，開關S1可替代地位於電容器C1與接墊105之間。控制器125在未終結端點100充當接收端點時控制開關S1閉合，且在未終結端點100充當傳輸端點時控制開關斷開。特定而言，驅動器110可具有作用中操作模式，其中其用以經由接墊105將信號傳輸至遠端晶粒。類似地，未終結端點100可具有回鈴減少操作模式，其中接收器115用以經由接墊105自遠端晶粒接收信號。控制器125經組態以在未終結端點110處於回鈴減少操作模式下時閉合開關S1，且在驅動器110處於其作用中操作模式下時斷開開關S1。 應注意，在資料速率減小時，回鈴雜訊變得不太成問題。在此類減小之資料傳輸速率下，回鈴雜訊有機會在自一個資料位元傳輸至下一資料位元傳輸之相對較長間隔期間充分衰減。但在較高資料速率下，連續資料位元傳輸之間的間隔變短使得回鈴雜訊成問題。因此，在接收器115用以接收資料時，控制器125可藉由在接收啟用信號(未圖示)經確證時判定資料傳輸速率是否大於臨限值來判定回鈴減少操作模式是否在作用中。舉例而言，在接收器115處於作用中時，控制器125可比較同步於資料傳輸速率之時脈信號與臨限值以判定回鈴減少操作模式是否在作用中。此外應注意，控制器125亦可對超控信號(未圖示)作出回應，使得其抑制閉合開關S1而不管資料傳輸速率。回應於啟動回鈴減少操作模式，控制器125閉合開關S1。相反，控制器125可藉由斷開開關S1 (諸如當驅動器110在其作用中操作模式下起作用時將發生的)來對撤銷啟動回鈴減少操作模式作出回應。替代地，即使接收器115在作用中，控制器125亦可斷開開關S1，此係因為資料傳輸速率低於臨限值。 在開關S1閉合時藉由來自電容器C1之電容對接墊105進行加載關於減弱回鈴係相當有利的。舉例而言，電容器C1可吸收來自在接墊105處正接收之二進位1位元信號傳輸之上升邊緣的電荷，以便減弱上升邊緣自接墊105返回至外部傳輸線120上之反射。類似地，電容器C1可將電荷釋放至在接墊105處正接收之二進位0位元信號之下降邊緣，以便減弱下降邊緣自接墊105返回至外部傳輸線120上之反射。 可使用任何合適的電晶體實施開關S1。舉例而言，圖 2 中所展示之未終結端點200包括充當開關之n型金屬氧化物半導體(NMOS)電晶體M1及另一NMOS電晶體M2。每一電晶體M1及M2連接至其自身的對應電容器，對應電容器在未終結端點200中係分別使用一對電晶體M3及M4之閘極電容來實施。電晶體M1連接於接地與電晶體M3之汲極/源極端子之間，電晶體M3具有連接至接墊105之閘極。類似地，電晶體M2連接於接地與電晶體M4之汲極/源極端子之間，電晶體M4具有連接至接墊105之閘極。控制器125驅動電晶體M1及M2之閘極以判定該等閘極接通抑或斷開。當電晶體M1接通時，對應電晶體M3之閘極電容對接墊105進行加載。類似地，當電晶體M2接通時，對應電晶體M4之閘極電容對接墊105進行加載。以此方式，控制器125可藉由選擇性地接通電晶體M1及M2中之僅一者或兩者來調整所要電容量以用於對接墊105進行加載。在替代實施例中，當終結端點200充當接收端點時，可添加額外電容器以增大所要電容之調整範圍以用於對接墊105進行加載。 經由諸如M3或M4之電晶體的閘極電容實施電容器C1係有利的，此係因為不需要外部電容器。給定電晶體之閘極電容的量將取決於處理節點而變化，但典型值之範圍係大約200至400毫微微法拉。然而將瞭解，在替代實施例中，電容器C1可包含外部電容器。此外應注意，電晶體M1及M2可重新配置成替代地位於其各別電容器與接墊105之間。類似地，電晶體M1、M2、M3及M4可替代地實施為P型金屬氧化物半導體(PMOS)電晶體。 在一個實施例中，圖1之開關S1與電容器C1的組合(或圖2之電晶體M1及M3或圖2之電晶體M2及M4)可被視為包含用於在接收器115處於作用中且用於接收器115之資料速率高於臨限值時藉由電容對接墊105進行加載且用於在驅動器110處於作用中時或在接收器115處於作用中且用於接收器115之資料速率低於臨限值時隔離接墊與電容的構件。 本文中所揭示之未終結端點對於晶粒間輸入/輸出(I/O)介面具有廣泛的應用。舉例而言，SoC晶粒305可包括用於與複數個DRAM晶粒310中之對應端點通信的複數個未終結端點100，如圖 3 中所展示(為說明清楚起見，針對SoC晶粒305以及DRAM晶粒310中之一者僅展示一個未終結端點100)。SoC晶粒305及DRAM晶粒310經配置以形成實例疊層封裝(PoP)積體電路封裝300。底部封裝320包括SoC晶粒305，而上部封裝315包括四個DRAM晶粒310。如PoP技術中已知的，每一封裝320及315包括具有金屬層之基板，諸如有機基板，該等金屬層經圖案化以形成所要外部傳輸線120 (為說明清楚起見，在圖3中僅展示一個外部傳輸線120，其自SoC晶粒305延伸至DRAM晶粒310中之作用中的一者)。特定而言，外部傳輸線120可包括來自用於SoC晶粒305中之未終結端點100之接墊的銅柱，其經由底部封裝320中之有機基板中的跡線耦接至焊球325，該焊球將底部封裝有機基板連接至上部封裝有機基板。外部傳輸線120經由上部封裝有機基板中之跡線繼續連接至導線接合件，其通向用於DRAM晶粒310中之作用中的一者中的未終結端點100之接墊。如本文中所論述，各種DRAM晶粒310與SoC晶粒305之間的回鈴將因此被有利地減弱。 現將關於圖 4 之流程圖論述用於未終結端點之實例操作方法。該方法包括動作400：當在用於第一晶粒中之未終結端點的接墊處接收信號時，閉合開關以藉由來自電容器之電容對接墊進行加載。如關於圖1所論述之開關S1的閉合或圖2之電晶體M1及/或M2的接通係動作400之實例。該方法進一步包括動作405：在將信號自用於第一晶粒中之未終結端點的接墊傳輸至遠端晶粒時，斷開開關從而不藉由電容對接墊進行加載。如關於圖1所論述之開關S1的斷開或圖2之電晶體M1及M2的切斷係動作405之實例。 如熟習此項技術者至今將瞭解且取決於即將進行之特定應用，可在不脫離本發明之範圍的情況下對本發明之裝置的材料、設備、組態及使用方法作出許多修改、替代及變化。鑒於此，本發明之範圍不應限於本文中所說明及描述之特定實施例的範圍，此係因為該等實施例僅為其一些實例，實際上本發明之範圍應與下文隨附申請專利範圍及其功能等效物之範圍完全相稱。
100‧‧‧未終結端點105‧‧‧接墊110‧‧‧驅動器115‧‧‧接收器120‧‧‧外部傳輸線/外部傳輸通道125‧‧‧控制器200‧‧‧未終結端點300‧‧‧疊層封裝(PoP)積體電路封裝305‧‧‧系統單晶片(SoC)晶粒310‧‧‧動態隨機存取記憶體(DRAM)晶粒315‧‧‧上部封裝320‧‧‧底部封裝325‧‧‧焊球400‧‧‧動作405‧‧‧動作C1‧‧‧電容器M1‧‧‧n型金屬氧化物半導體(NMOS)電晶體M2‧‧‧n型金屬氧化物半導體(NMOS)電晶體M3‧‧‧電晶體M4‧‧‧電晶體S1‧‧‧開關
圖1係根據本發明之態樣的實例未終結端點之圖。 圖2係根據本發明之態樣的圖1之未終結端點的實施例之電路圖。 圖3係根據本發明之態樣的疊層封裝積體電路之圖，在該疊層封裝積體電路中，晶粒包括諸如圖1或圖2中所展示之複數個未終結端點。 圖4係根據本發明之態樣的用於未終結端點之實例操作方法的流程圖。 藉由參考以下實施方式最佳地理解本發明之實施例及其優點。應瞭解，相同參考數字用以識別諸圖中之一或多者中所說明的相同元件。
100‧‧‧未終結端點
105‧‧‧接墊
110‧‧‧驅動器
115‧‧‧接收器
120‧‧‧外部傳輸線/外部傳輸通道
125‧‧‧控制器
C1‧‧‧電容器
S1‧‧‧開關

Claims (18)

  1. 一種用於一第一晶粒之未終結端點，其包含：一接墊；一驅動器，其具有一作用中模式，在該模式下，該驅動器經組態以經由該接墊將信號驅動至一遠端晶粒；一接收器，其具有一作用中模式，在該模式下，該接收器經組態以經由該接墊自該遠端晶粒接收信號；一電容器；一開關，其連接至該電容器，其中該開關經組態以在該開關閉合時經由該電容器將該接墊耦接至接地且在該開關斷開時不經由該電容器將該接墊耦接至接地；及一控制器，其經組態以：在該接收器處於該作用中模式下時閉合該開關且在該驅動器處於該作用中模式下時斷開該開關；及僅在該接收器處於該作用中模式下且用於該接收器之一資料速率高於一臨限值時閉合該開關。
  2. 如請求項1之未終結端點，其中該電容器包含一電晶體之一閘極。
  3. 如請求項1之未終結端點，其中該開關連接於該電容器與接地之間。
  4. 如請求項1之未終結端點，其中該電容器包含複數個電容器，且其中 該開關包含在一對一的基礎上與該複數個電容器對應之複數個開關。
  5. 如請求項1之未終結端點，其中該控制器經進一步組態以在該接收器處於該作用中模式下時選擇性地閉合來自複數個開關之開關以調整來自該等電容器之一電容性負載。
  6. 如請求項1之未終結端點，其中該開關包含一NMOS電晶體，且其中該控制器經組態以藉由對該NMOS電晶體之一閘極充電來閉合該開關。
  7. 如請求項1之未終結端點，其中該第一晶粒係一系統單晶片(SoC)晶粒，且其中該遠端晶粒係一動態隨機存取記憶體(DRAM)晶粒。
  8. 如請求項7之未終結端點，其中該SoC晶粒係整合於一疊層封裝積體電路之一底部封裝內，且其中該DRAM晶粒係整合於該疊層封裝積體電路之一頂部封裝內。
  9. 如請求項8之未終結端點，其中該DRAM晶粒係一低功率雙資料速率(LPDDR)DRAM晶粒。
  10. 如請求項1之未終結端點，其中DRAM晶粒包含複數個DRAM晶粒。
  11. 一種晶粒間雙向發信之方法，其包含：當在用於一第一晶粒中之一未終結端點的一接墊處接收第一信號 時，閉合一開關以藉由來自一電容器之一電容對該接墊進行加載；在將第二信號自用於該第一晶粒中之該未終結端點的該接墊傳輸至一遠端晶粒時，斷開該開關從而不藉由該電容對該接墊進行加載；及當在該接墊處接收第三信號時，斷開該開關，其中接收該等第三信號係以低於一臨限值之一第二資料速率發生。
  12. 如請求項11之方法，其中閉合該開關經由一電晶體之一閘極電容將該接墊連接至接地以對用於該未終結端點之該接墊進行電容性加載。
  13. 如請求項12之方法，其中閉合該開關將該電晶體之一汲極及源極連接至接地。
  14. 如請求項12之方法，其中斷開該開關隔離該電晶體之該閘極電容與接地。
  15. 如請求項11之方法，其進一步包含：調整該電容器之一電容以調節該接墊之該電容性加載。
  16. 一種用於一晶粒之未終結端點，其包含：一接墊；一驅動器，其具有一作用中模式，在該模式下，該驅動器經組態以經由該接墊將信號驅動至一遠端晶粒；一接收器，其具有一作用中模式，在該模式下，該接收器經組態以 經由該接墊自該遠端晶粒接收信號；一電容器；用於在該接收器處於該作用中模式下時閉合一開關且在該驅動器處於該作用中模式下時斷開該開關的構件；及用於僅在該接收器處於該作用中模式下且用於該接收器之一資料速率高於一臨限值時閉合該開關的構件。
  17. 如請求項16之未終結端點，其中該電容器包含一電晶體之一閘極。
  18. 如請求項17之未終結端點，其中該電晶體包含一NMOS電晶體。
TW107101940A 2017-02-15 2018-01-19 用於支持來自未終結端點之雙向發信之程式化接墊 TWI753990B (zh)

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