TWI753464B - 半導體、積體電路元件及其製造方法 - Google Patents
半導體、積體電路元件及其製造方法 Download PDFInfo
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- TWI753464B TWI753464B TW109120901A TW109120901A TWI753464B TW I753464 B TWI753464 B TW I753464B TW 109120901 A TW109120901 A TW 109120901A TW 109120901 A TW109120901 A TW 109120901A TW I753464 B TWI753464 B TW I753464B
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Abstract
一種積體電路元件包括第一電力軌、在第一方向上延伸的第一主動區、及接觸第一主動區且在垂直於第一方向的第二方向上延伸的複數個閘極。第一電晶體包括第一主動區及第一個閘極。第一電晶體具有第一閾值電壓(VT)。第二電晶體包括第一主動區及第二個閘極。第二電晶體具有與第一VT不同的第二VT。約束電晶體在第一電晶體與第二電晶體之間定位,並且包括第一主動區及第三個閘極,其中第三閘極連接到第一電力軌。
Description
本揭露是有關一種半導體積體電路元件及其製造方法。
垂直半導體元件,諸如基於鰭的金屬氧化物半導體場效電晶體(FinFET),係在半導體基板的表面上的三維結構。鰭從基板的主體向上延伸,並且可藉由在基板上沉積鰭材料、蝕刻基板的非鰭區、或其組合來形成。FET的通道在此垂直鰭中形成,並且閘極在鰭上方提供(例如,纏繞)。將閘極纏繞在鰭周圍增加在通道區域與閘極之間的接觸面積,並且允許閘極從兩側控制通道。隨著積體電路元件變小,在元件之間的間隔或「間距」可在相鄰元件之中導致電磁干擾。
相鄰元件(諸如FinFET)可電氣隔離,其中相鄰電晶體可用作隔離元件。此種隔離元件可稱為「約束」元件,其中將約束元件的主動區設置為關閉狀態。隔離元件的閘極(「約束閘極」)可經偏置來將隔離元件置於OFF狀態,並且為相鄰主動元件提供隔離。
根據本揭露一實施方式,一種積體電路元件包含:
一第一電力軌;一第一主動區,在一第一方向上延伸;複數個閘極,接觸該第一主動區並且在垂直於該第一方向的一第二方向上延伸;一第一電晶體,包括該第一主動區及該些閘極的一第一閘極,該第一電晶體具有一第一閾值電壓(VT);一第二電晶體,包括該第一主動區及該些閘極的一第二閘極,該第二電晶體具有與該第一VT不同的一第二VT;以及一約束電晶體,在該第一電晶體與該第二電晶體之間定位,該約束電晶體包括該第一主動區及該些閘極的一第三閘極,其中該第三閘極連接到該第一電力軌。
根據本揭露一實施方式,一種半導體元件,包含:一第一電力軌;一第二電力軌;一第一鰭,在一第一方向上延伸;一第一PMOS電晶體,包括該第一鰭及一第一閘極,該第一PMOS電晶體具有一第一閾值電壓(VT),該第一閘極在垂直於該第一方向的一第二方向上延伸;一第二PMOS電晶體,包括該第一鰭及在該第二方向上延伸的一第二閘極,該第二PMOS電晶體具有與該第一VT不同的一第二VT,並且其中該第二閘極連接到該第一電力軌;一第二鰭,在該第一方向上延伸;一第一NMOS電晶體,包括該第二鰭及該第一閘極,該第一NMOS電晶體具有該第一VT;一第二NMOS電晶體,包括該第二鰭及該第二閘極,該第二NMOS電晶體具有該第二VT,並且其中該第二閘極連接到該第二電力軌。
根據本揭露一實施方式,一種積體電路元件的製造方法,包含:在一基板上形成一第一主動區,該第一主動區包括一第一閾值電壓(VT)區域及一第二VT區域;形成一第一閘極,該第一閘極接觸該第一主動區的該第一VT區域以形成具有一第一VT的一第一電晶體;形成一第二閘極,該第二閘極接觸該第一主動區的該第二VT區域以形成具有與該第一VT不同的一第二VT的一第二電晶體;形成一第三閘極,該第三閘極接觸在該第一閘極與該第二閘極之間的該第一主動區以形成在該第一電晶體與該第二電晶體之間定位的一約束電晶體;以及將該第三閘極連接到一電力軌以將該約束電晶體維持在一關閉狀態。
1:連通柱
2:連通柱
10:半導體結構
12:基層
14:互連層
16:介電材料
20:金屬層結構
30:半導體結構
32:FinFET電晶體
34:半導體基板
36:鰭
38:隔離區域
40:多晶矽
100:積體電路元件
101:積體電路元件
102:積體電路元件
103:積體電路元件
104:元件
105:元件
106:元件
110:主動區/鰭
111:主動區/鰭
112:第一電力軌
114:第二電力軌
120a:多晶矽閘極
120b:多晶矽閘極
120c:多晶矽閘極
120d:多晶矽閘極
120e:多晶矽閘極
122:導電連通柱
123:導電連通柱
124:導電連通柱
125:導電連通柱
126:導電連通柱
127:導電連通柱
128:導電連通柱
129:導電連通柱
130:電晶體
131:電晶體
132:電晶體
133:電晶體
134:電晶體
135:電晶體
140:第一VT區域
142:第二VT區域
150:PMOS區域
152:NMOS區域
154:分離部/切割多晶矽
160:M0金屬層
162:金屬接線
164:金屬接線
200:方法
210:步驟
212:步驟
214:步驟
216:步驟
218:步驟
300:系統
301:系統
302:處理器
303:製造工具
304:儲存媒體
306:電腦程式碼
307:程式庫
308:匯流排
310:I/O介面
312:網路介面
314:網路
320:設計室
322:IC設計佈局圖
330:遮罩室
332:資料準備
342:使用者介面
344:遮罩製造
345:遮罩
350:IC Fab
352:晶圓製造
353:半導體晶圓
360:IC元件
SC:S觸點
DC:D觸點
GC:G觸點
M1LP:導電著陸墊
當結合隨附圖式閱讀時,自以下詳細描述將很好地理解本揭示的態樣。應注意,根據工業中的標準實務,各個特徵並非按比例繪製。事實上,出於論述清晰的目的,可任意增加或減小各個特徵的尺寸。此外,圖式作為本揭露的實施例的實例係說明性的,並且不意欲為限制性。
第1圖係示出根據一些實施例的半導體元件的實例的方塊圖。
第2圖係示出根據一些實施例的第1圖所示的半導體元件的示例金屬層的方塊圖。
第3圖係示出根據一些實施例的示例FinFET元件的方
塊圖。
第4圖係示出根據一些實施例的示例半導體元件的方塊圖。
第5圖係示出根據一些實施例的另一示例半導體元件的方塊圖。
第6圖係示出根據一些實施例的另外的示例半導體元件的方塊圖。
第7圖係示出根據一些實施例的又一示例半導體元件的方塊圖。
第8圖係示出根據一些實施例的另外的示例半導體元件的方塊圖。
第9圖係示出根據一些實施例的另一示例半導體元件的方塊圖。
第10圖係示出根據一些實施例的另一示例半導體元件的方塊圖。
第11圖係示出根據一些實施例的方法的實例的流程圖。
第12圖係示出根據一些實施例的電子設計自動化(EDA)系統態樣的方塊圖。
第13圖係示出根據一些實施例的IC製造系統及製造流程的實例的態樣的方塊圖。
以下揭示內容提供許多不同的實施例或實例,用於實施所提供標的的不同特徵。下文描述部件及佈置的具
體實例以簡化本揭示。當然,此等僅為實例且並不意欲為限制性。例如,以下描述中在第二特徵上方或第二特徵上形成第一特徵可包括以直接接觸形成第一特徵及第二特徵的實施例,且亦可包括在第一特徵與第二特徵之間形成額外特徵以使得第一特徵及第二特徵可不處於直接接觸的實施例。此外,本揭示可在各個實例中重複元件符號及/或字母。此重複係出於簡便性及清晰的目的且本身並不指示所論述的各個實施例及/或構造之間的關係。
另外,為了便於描述,本文可使用空間相對性術語(諸如「下方」、「之下」、「下部」、「之上」、「上部」及類似者)來描述諸圖中所示出的一個元件或特徵與另一元件或特徵的關係。除了諸圖所描繪的定向外,空間相對性術語意欲涵蓋使用或操作中元件的不同定向。設備可經其他方式定向(旋轉90度或處於其他定向)且由此可同樣地解讀本文所使用的空間相對性描述詞。
多閾值電壓IC元件有時用於最佳化各種電路及元件中的延遲或功率。多閾值電壓IC元件可包括若干不同的元件,每種元件具有不同的閾值電壓(亦即,操作電壓)。例如,多閾值電壓IC元件可包括下列中的兩種或多種:低閾值電壓(LVT)元件、標準閾值電壓(SVT)元件及高閾值電壓(HVT)元件。
包括相鄰多閾值IC元件(諸如多閾值FinFET)的相鄰元件可使用一或多個隔離元件而達成電氣隔離。
此種隔離元件可被稱為「約束」元件。在一些實例中,電晶體經構造為隔離元件,其中將約束元件的主動區設置為關閉狀態。隔離元件的閘極(「約束閘極」)可經偏置來將隔離元件置於關閉狀態,並且為相鄰主動元件提供隔離。例如,約束元件可位於元件之間的閾值電壓(VT)邊界。
根據一些揭示的實施例,用於約束電晶體的多晶矽閘極在混合VT結構的VT邊界處定位。電晶體可藉由將多晶矽閘極連接到電力軌的導電連通柱約束,將元件維持於關閉狀態。將多晶矽閘極定位在VT邊界處並且藉由通孔將多晶矽閘極直接連接到電力軌可節省元件面積。
第1圖係示出根據一些實施例的示例半導體結構10的橫截面的方塊圖。在第1圖中在X軸及Z軸方向上示出結構10,而Y軸方向與第1圖中示出的橫截面的平面正交。結構10包括基層12及互連層14。
大體上,基層12包括半導體基板,此半導體基板繼而包括多晶矽區域(在本揭示全文中亦稱為「多晶矽(poly))、擴散區域、半導體井(例如,N井、P井、深N井、深P井)等,其中形成半導體元件(例如,電晶體、二極體等)。互連層14包括N個(例如,整數個)導電層(例如,金屬層M1至MN),此等導電層用於在互連層14中使層內的元件互連並且用於形成到外部元件的電氣連接等。互連層14通常包括通孔、層
級間介電材料、鈍化層、接合墊、封裝資源等。互連層14中的每個金屬(例如,導電)層M常常稱為金屬一、金屬二、金屬三(M1、M2、M3等)層等。用於絕緣金屬層M的介電材料(例如,高介電常數、低介電常數材料等)16在各個金屬層M之間。基層12及互連層14經常分別稱為前端結構及後端結構,因此此等層在半導體製造製程中係相應的「線程前端」(FEOL)及「線程後端」(BEOL)。
第2圖係示出根據一些實施例的示例互連金屬層結構20的方塊圖。金屬層結構20包括複數個導電層M(例如,M1、M2、M3等)。在所示的實施例中,金屬層結構20僅示出兩層(例如,M2及M3)。具有不同數量層(例如,從1到N個層)的金屬層結構係在所揭示實施例的範疇內。
在第2圖所示的實施例中,每個金屬層M包括複數個金屬桿MB,例如,層M2中的金屬桿MB21、MB22、及MB23以及層M3中的金屬桿MB31、MB32、MB33。在一些實施例中,金屬桿的形狀係圓柱形或一些其他形狀,並且可以係任何橫截面形狀。在所示的實施例中,層M中的金屬桿MB的每一者實質上彼此平行。在所示的實施例中,每個金屬層M2及M3包括三個金屬桿MB,然而,每個金屬層M具有不同數量的金屬桿MB的構造係在所揭示實施例的範疇內。在一些實施例中,第一組金屬桿MB(例如,金屬層M1、M3、M5等中
的金屬桿MB)在第一方向(例如,X軸方向)上延伸,而第二組金屬桿MB(例如,在金屬層M2、M4、M6等中)在第二方向(例如,Y軸方向)上延伸,其中X軸方向垂直於Y軸方向。其中所有桿MB在一個方向(例如,X軸方向、Y軸方向、或任何其他習知方向、或方向的組合,包括非垂直方向)上延伸的不同構造係在所揭示實施例的範疇內。在第2圖所示的實施例中,每個金屬桿MB具有寬度Wbar。在一些實施例中,所有寬度Wbar具有相同大小,但所揭示實施例不限於此種構造。取決於設計選擇,寬度Wbar可具有不同大小(例如,一個寬度Wbar可比另一者短或長)。兩個相鄰金屬桿MB藉由一距離(例如,距離D)間隔或分離。在一些實施例中,選擇距離D以滿足在兩個金屬桿MB之間的間隔的最小需求,從而在彼等兩個桿之間形成電容。在一些實施例中,金屬層結構20中的所有距離D具有相同大小,但所揭示實施例不限於此種構造。亦即,距離D可具有不同大小(例如,一個距離D可比另一者短或長)。層M中的金屬桿MB的厚度與層M的厚度成比例,此可以取決於製程技術,並且不同群組的層M可以具有不同厚度。例如,第一群組的金屬層M(例如,Mx)可以具有第一厚度,第二群組的金屬層M(例如,My)可以具有第二厚度,並且第三群組的金屬層(例如,Mz)可以具有第三厚度等,其中第一、第二、及第三厚度係不同的。在所示的實施例中,金屬層結構20具有
寬度W及長度L。
第3圖係示出根據一些實施例的示例半導體結構30的橫截面的方塊圖。所示的實施例包括FEOL層(包括半導體結構)及BEOL層(包括互連金屬層結構)。
在所示的實施例中,FEOL層包括FinFET電晶體32。FinFET電晶體32包括半導體基板34、鰭36、隔離區域38、多晶矽結構(例如,多晶矽40)、連接到鰭的導電S觸點SC及D觸點DC、以及連接到多晶矽40的導電G觸點GC。在所示的實施例中,電流的導電路徑係鰭36(鰭亦可以稱為主動區或區域)。多晶矽40作為電流在鰭中從S(例如,源極)觸點SC流到D(例如,汲極)觸點DC的閘極。大體上,此種閘極結構包括一或多個導電區段,此等導電區段包括一或多種導電材料,諸如上文提及的多晶矽。其他閘極材料可包括一或多種金屬、摻雜的多晶矽、及/或其他導電材料。導電區段因此用以控制向下層介電層提供的電壓。在各個實施例中,例如,閘極介電層包括下列中的一或多者:二氧化矽及/或高介電常數介電材料,例如,介電常數值高於3.8或7.0的介電材料。在一些實施例中,高介電常數材料包括氧化鋁、氧化鉿(hafnium oxide)、氧化鑭(lanthanum oxide)、或另一適宜材料。例如,針對在S觸點SC及D觸點DC之間的電壓電位,取決於施加到多晶矽40的電壓,電流可以在鰭中從S流到D。若將小於閾值電壓(VT)的電壓施加到多晶矽40,
則可以察覺的電流不能在鰭中從S觸點SC流到D觸點DC,並且電晶體32「關閉」。若將大於或等於VT的電壓施加到多晶矽40,則可以察覺的電流經由鰭從S流到D,並且電晶體32「接通」。在一些實施例中,S觸點SC、D觸點DC、及G觸點GC在FEOL層中的多個鰭與多晶矽之間形成連接,藉此連接一或多個電晶體的源極、汲極、及閘極。在一些實施例中,電晶體32的源極、汲極、及閘極連接到BEOL層中的互連金屬層結構。例如,電晶體32的閘極可藉由BEOL層中的互連金屬結構層之一中的金屬桿的一或多者連接到其他結構,並且電晶體32的S觸點SC/D觸點DC可使用BEOL層中的金屬層的一或多者中的另一些金屬桿類似地連接到其他結構。在一些實施例中,BEOL層用以將電晶體32連接到周邊電路。在所示的實施例中,D觸點DC及G觸點GC使用通孔連接到BEOL層中的金屬桿。例如,連通柱1在D觸點DC到FEOL層之上的第一金屬層M1中的金屬桿之間形成連接。在所示的實施例中,分離的連通柱1將G觸點GC連接到M1層中的導電著陸墊M1LP,並且連通柱2將導電著陸墊M1LP連接到M2層中的金屬桿。
第4圖示出了根據所揭示態樣的積體電路元件100的實例。大體上,積體電路元件100可包括FinFET結構,諸如第1圖至第3圖所示的彼等。第4圖所示的積體電路元件100包括第一電力軌112,諸如
VDD或VSS電力軌。在第4圖的實例中,電力軌112係VDD軌。第一主動區110在X軸方向上延伸。在一些實例中,主動區110包括鰭,諸如第3圖所示的鰭36。複數個多晶矽閘極120接觸主動區110,並且在Y軸方向上延伸。換言之,多晶矽閘極120大體垂直於主動區110延伸。在第4圖中示出的實例中,複數個多晶矽閘極120包括標記為120a-120e的五個多晶矽閘極。
第一電晶體130藉由第一主動區110及第一個多晶矽閘極120a來形成,並且第二電晶體132藉由第一主動區110及第二個多晶矽閘極120b來形成。在所示出的實例中,第一電晶體130具有第一VT,並且第二電晶體132具有與第一VT不同的第二VT。積體電路元件100因此包括界定兩個不同VT位準的連續主動區110。在所示出的實施例中,主動區110包括第一VT區域140及第二VT區域142。例如,第一及第二VT可以係下列中的任一者:標準VT(SVT)、低VT(LVT)、超低VT(uLVT)、高VT(HVT)等。因此,例如,第一電晶體130可具有標準VT(SVT),且第二電晶體132可具有低VT(LVT)。
多個VT元件可在一些IC元件中實現較佳的功率效率。在一些實例中,藉由使用通道及/或暈圈植入(halo implantation optimization)最佳化,主動區110經製造為具有不同VT特性。例如,HVT元件
可藉由重度植入元件通道/暈袋(halo pockets)(包括離子植入及熱退火)來實現。
約束電晶體134在第一電晶體130與第二電晶體134之間定位。約束電晶體134藉由第一主動區110及第三個多晶矽閘極120c來形成。約束電晶體134的第三多晶矽閘極120c連接到電力軌112,將約束電晶體維持在關閉狀態。約束電晶體134用以將具有第一VT的第一電晶體130與具有第二VT的第二電晶體132電氣隔離。在第1圖中示出的實例中,第一電晶體130及第二電晶體132以及約束電晶體134係PMOS電晶體。PMOS約束電晶體132使其多晶矽閘極120c藉由導電連通柱122連接到VDD電力軌112,以保持約束電晶體134關閉,從而將第一電晶體130與第二電晶體132電氣隔離。
在一些實例中,約束電晶體134可位於第一VT區域140及第二VT區域142的邊界處。因此,將約束電晶體134連接到VDD軌112的多晶矽閘極120c沿著Y軸方向直接在VT邊界上方延伸。與將金屬接線用於約束元件相比,使用多晶矽閘極120c將約束電晶體連接到電力軌112節省面積。
在第4圖的實例中,多晶矽閘極120d及120e IC可係氧化物界定邊緣(CPODE)圖案上的連續多晶矽。在一些實施方式中,IC元件(諸如金屬氧化物半導體場效電晶體(MOSFET))經由各個技術節點按比例縮小,
元件裝填密度及元件效能因元件佈局及隔離而受到挑戰。為了避免在相鄰元件之間的洩漏,多晶矽區段可在主動區域(諸如FinFET中的鰭110)的邊緣上形成。此種多晶矽區段有時亦被稱為OD邊緣上多晶矽(PODE)。PODE有助於實現較佳元件效能及較佳多晶矽輪廓控制。
在一些實施例中,PODE結構在積體電路元件100的邊緣上形成,並且用於在處理期間保護鰭110的末端。亦即,PODE多晶矽結構未電氣連接,作為用於電晶體的閘極,而是替代地作為「虛設」結構,從而在電路中不起作用。PODE結構覆蓋並且保護鰭110的末端,從而在處理期間提供額外的可靠性。
大體上,與鰭110接觸的多晶矽閘極120的數量可以被認為係IC元件沿著一個維度的「間距(pitch)」,經常稱為「接觸多晶矽間距(contacted poly pitch)」或CPP。CPP可至少部分決定IC元件的密度。藉由將約束電晶體134的多晶矽閘極120c直接定位在VT區域邊界上方,多晶矽閘極120c由第一VT區域140及第二VT區域142二者「共享」,而不需要個別的多晶矽接線來用於在第一VT區域140及第二VT區域142的每一者中的分離約束元件。因此,可在所揭示實例中減少一個多晶矽間距,從而產生5個CPP的元件。
第5圖示出了根據所揭示態樣的另一示例積體電路元件101。第5圖所示的積體電路元件101與第4
圖的積體電路元件100類似,儘管積體電路元件101包括第二電力軌114(在所示出實例中為VSS電力軌),而非如在第4圖的積體電路元件100中一般包括PMOS電晶體,第5圖揭示了NMOS電晶體。與上文揭示的積體電路元件100一樣,積體電路元件101包括在X軸方向上延伸的主動區或鰭111。複數個多晶矽閘極120接觸主動區111並且在Y軸方向上延伸,使得多晶矽閘極120通常垂直於主動區111延伸。第5圖中示出的複數個多晶矽閘極120再次標記為120a-120e。換言之,積體電路元件101亦為五個CPP的結構。
具有第一VT的第一NMOS電晶體131藉由主動區111及第一多晶矽閘極120a來形成,並且具有第二VT的第二NMOS電晶體133藉由主動區111及第二多晶矽閘極120b來形成。積體電路元件101因此包括具有第一VT區域140及第二VT區域142的連續主動區111。如上文提及,第一及第二VT可係下列中的任一者:標準VT(SVT)、低VT(LVT)、超低VT(uLVT)、高VT(HVT)等。
約束電晶體135在第一NMOS電晶體131與第二NMOS電晶體133之間定位。約束電晶體135藉由主動區111及第三多晶矽閘極120c來形成。在第5圖中示出的實例中,約束電晶體135係NMOS電晶體,其中多晶矽閘極120c藉由導電連通柱123連接到
VSS電力軌114以保持約束電晶體135關閉,從而使第一NMOS電晶體131與第二NMOS電晶體133電氣隔離。約束電晶體135位於第一VT區域140及第二VT區域142的邊界處。
第6圖示出了包括PMOS及NMOS電晶體二者的積體電路元件102的實施例,其中約束電晶體具有耦接到VDD及VSS電力軌的多晶矽閘極。因此,積體電路元件102包括界定PMOS區域150及NMOS區域152的第一鰭110及第二鰭111。積體電路元件102包括第一電力軌112及第二電力軌114,此等電力軌在示出的實例中分別係VDD及VSS電力軌。主動區或鰭110及111在X軸方向上延伸。複數個多晶矽閘極120接觸主動區111並且在Y軸方向上延伸,使得多晶矽閘極120大體垂直於主動區110、111延伸。積體電路元件102具有五個多晶矽閘極120a-120e,並且因此亦是五個CPP的結構。
PMOS區域150包括藉由第一主動區110及第一多晶矽閘極120a形成的第一PMOS電晶體130、以及藉由第一主動區110及多晶矽閘極120b形成的第二PMOS電晶體132。第一NMOS電晶體131藉由主動區111及第一多晶矽閘極120a來形成,並且第二NMOS電晶體133藉由主動區111及第二多晶矽閘極120b來形成。積體電路元件102包括具有第一VT區域140及第二VT區域142的連續主動區110、111。
由此,第一PMOS電晶體130及第一NMOS電晶體131具有第一VT,且第二PMOS電晶體132及第二NMOS電晶體133具有第二VT。如上文提及,第一及第二VT可為下列中的任一者:標準VT(SVT)、低VT(LVT)、超低VT(uLVT)、高VT(HVT)等。
約束電晶體134及135藉由主動區110、111及第三多晶矽閘極120c來形成,並且在第一VT區域140及第二VT區域142的邊界處定位。因此,PMOS約束電晶體134在第一PMOS電晶體130與第二PMOS電晶體132之間定位,並且NMOS約束電晶體135在第一NMOS電晶體131與第二NMOS電晶體133之間定位。
在第6圖中示出的實例中,約束電晶體134係PMOS電晶體,並且約束電晶體135係NMOS電晶體。多晶矽閘極120c藉由導電連通柱122連接到VDD電力軌,並且藉由導電連通柱123連接到VSS電力軌114。多晶矽閘極120在分離部154處經圖案化或切割,使得多晶矽閘極120c的上部將PMOS約束電晶體134連接到VDD軌112,但不將PMOS約束電晶體134的閘極連接到VSS端子。多晶矽閘極120c的下部將NMOS約束電晶體135連接到VSS軌114,但不將NMOS約束電晶體135的閘極連接到VDD端子。換言之,多晶矽閘極120c不將VDD軌直接連接或短路到VSS軌。以此方式,約束電晶體134及135均保持
在關閉狀態以使第一PMOS電晶體130及第二PMOS電晶體132彼此電氣隔離,並且使第一NMOS電晶體131及第二NMOS電晶體133彼此電氣隔離。
在第4圖至第6圖所示的積體電路元件100-102中,用於約束電晶體134、135的每一者的多晶矽閘極120c藉由導電連通柱122或123連接到電力軌112或114。更特定而言,導電連通柱122及123從多晶矽閘極120c直接延伸到相應的電力軌。第7圖示出了根據另外實施例的示例積體電路元件103,其中約束電晶體的多晶矽閘極經由一或多個金屬連接器連接到電力軌。第7圖所示的積體電路元件103包括第一(VDD)電力軌112並且具有PMOS電晶體。第一主動區或鰭110在X軸方向上延伸,並且多晶矽閘極120接觸主動區110且在Y軸方向上延伸。在第7圖中示出的實例中,複數個多晶矽閘極120再次包括標記為120a-120e的五個多晶矽閘極。
在第一VT區域140中的第一PMOS電晶體130藉由第一主動區110及第一多晶矽閘極120a來形成,並且在第二VT區域142中的第二PMOS電晶體132藉由第一主動區110及第二多晶矽閘極120b來形成。因此,第一電晶體130具有第一VT,且第二電晶體132具有與如上文描述的第一VT不同的第二VT。
PMOS約束電晶體134在第一PMOS電晶體130與第二PMOS電晶體132之間定位。約束電晶體
134藉由第一主動區110及多晶矽閘極120c來形成。約束電晶體134的多晶矽閘極120c連接到電力軌112以將約束電晶體維持在關閉狀態。更具體而言,在第7圖所示的實例中,導電連通柱124將多晶矽閘極120c連接到金屬層160之一(諸如M0金屬層)中的金屬導體或金屬桿。在所示出的實例中,M0金屬層160在X軸方向上延伸。金屬層160藉由導電連通柱125連接到金屬接線162(諸如在主動區110上方的金屬沉積物),並且金屬接線162藉由另一導電連通柱126連接到VDD軌112。在所示出的實例中,金屬接線162在Y軸方向上延伸。因此,多晶矽閘極120c藉由M0金屬層160及金屬接線162連接到VDD軌112,以將約束電晶體134維持在關閉狀態來用於使PMOS電晶體130、132彼此隔離。
第8圖示出了另一實例,其中約束電晶體的多晶矽閘極經由一或多個金屬連接器連接到電力軌。第8圖所示的元件104包括第二(VSS)電力軌114並且具有NMOS電晶體。主動區或鰭111在X軸方向上延伸,並且多晶矽閘極120接觸主動區111且在Y軸方向上延伸。在第8圖中示出的實例中,複數個多晶矽閘極120再次包括標記為120a-120e的五個多晶矽閘極。
在第一VT區域140中的第一NMOS電晶體131藉由第一主動區111及第一多晶矽閘極120a來形成,並且在第二VT區域142中的第二NMOS電晶體133
藉由主動區111及第二多晶矽閘極120b來形成。因此,第一NMOS電晶體131具有第一VT,並且第二NMOS電晶體133具有與如上文描述的第一VT不同的第二VT。
NMOS約束電晶體135在第一NMOS電晶體131與第二NMOS電晶體133之間定位。約束電晶體135藉由主動區111及多晶矽閘極120c形成,此多晶矽閘極連接到VSS電力軌114以將NMOS約束電晶體135維持在關閉狀態。更具體而言,在第8圖所示的實例中,導電連通柱124將多晶矽閘極120c連接到M0金屬層160。金屬層160藉由導電連通柱125連接到金屬接線162(諸如在主動區110上方的金屬沉積物),並且金屬接線162藉由導電連通柱127連接到VSS軌114。因此,多晶矽閘極120c藉由M0金屬層160及金屬接線162連接到VSS軌114,以將NMOS約束電晶體135維持在關閉狀態來用於使NMOS電晶體131、133彼此隔離。
第9圖及第10圖示出了使用約束電晶體到適當電力軌的「軟」連接的示例元件。例如,第9圖示出了元件105,此元件包括界定PMOS區域150及NMOS區域152的第一鰭110及第二鰭111。元件105包括第一電力軌112及第二電力軌114,此等電力軌在示出的實例中分別係VDD及VSS電力軌。主動區或鰭110及111在X軸方向上延伸。複數個多晶矽閘極120接
觸主動區111並且在Y軸方向上延伸,使得多晶矽閘極120大體垂直於主動區110、111延伸。元件105具有五個多晶矽閘極120a-120e,並且因此亦係五個CPP的結構。
PMOS區域150包括藉由第一主動區110及第一多晶矽閘極120a形成的第一PMOS電晶體130、以及藉由第一主動區110及多晶矽閘極120b形成的第二PMOS電晶體132。第一NMOS電晶體131藉由主動區111及第一多晶矽閘極120a來形成,並且第二NMOS電晶體133藉由主動區111及第二多晶矽閘極120b來形成。元件105包括具有第一VT區域140及第二VT區域142的連續主動區110、111。由此,第一PMOS電晶體130及第一NMOS電晶體131具有第一VT,且第二PMOS電晶體132及第二NMOS電晶體133具有第二VT。如上文提及,第一及第二VT可係下列中的任一者:標準VT(SVT)、低VT(LVT)、超低VT(uLVT)、高VT(HVT)等。
在第9圖的實施例中,導電連通柱127將VSS軌114連接到第一PMOS電晶體130的多晶矽閘極120a。由此,第一PMOS電晶體130總是接通。然而,金屬接線162藉由導電連通柱128連接到VDD,並且第二PMOS電晶體132的多晶矽閘極120b經由M0金屬層160連接到金屬接線164。第二多晶矽閘極120b包括切割多晶矽154。因此,VDD電壓從其源極
洩漏到PMOS電晶體130的汲極側。「洩漏」的VDD電壓如此被稱為「軟」VDD連接,此連接約束PMOS電晶體132。
類似地,第10圖示出了元件106,此元件包括界定PMOS區域150及NMOS區域152的第一鰭110及第二鰭111。元件106包括第一電力軌112及第二電力軌114,此等電力軌在示出的實例中分別係VDD及VSS電力軌。主動區或鰭110及111在X軸方向上延伸。複數個多晶矽閘極120接觸主動區111並且在Y軸方向上延伸,使得多晶矽閘極120大體垂直於主動區110、111延伸。元件105具有五個多晶矽閘極120a-120e,並且因此亦係五個CPP的結構。
PMOS區域150包括藉由第一主動區110及第一多晶矽閘極120a形成的第一PMOS電晶體130、以及藉由第一主動區110及多晶矽閘極120b形成的第二PMOS電晶體132。第一NMOS電晶體131藉由主動區111及第一多晶矽閘極120a來形成,並且第二NMOS電晶體133藉由主動區111及第二多晶矽閘極120b來形成。元件105包括具有第一VT區域140及第二VT區域142的連續主動區110、111。由此,第一PMOS電晶體130及第一NMOS電晶體131具有第一VT,且第二PMOS電晶體132及第二NMOS電晶體133具有第二VT。如上文提及,第一及第二VT可係下列中的任一者:標準VT(SVT)、低VT(LVT)、
超低VT(uLVT)、高VT(HVT)等。
在第10圖的實施例中,導電連通柱126將VDD軌112連接到第一NMOS電晶體131的多晶矽閘極120a。由此,第一NMOS電晶體131總是接通。金屬接線162藉由導電連通柱129連接到VSS軌114,並且第二NMOS電晶體133的多晶矽閘極120b經由M0金屬層160連接到金屬接線164。第二多晶矽閘極120b包括切割多晶矽154。因此,VSS電壓從其源極洩漏到NMOS電晶體131的汲極側。「洩漏」的VSS電壓如此被稱為「軟VSS」連接,此連接約束NMOS電晶體133。
第11圖示出了根據所揭示實施例的方法。所示出的方法200提供了約束元件。更特定而言,在步驟210處,方法包括在基板上形成第一主動區。第一主動區(諸如鰭110)具有第一VT區域140及第二VT區域142。在步驟212處,形成第一閘極120a,此第一閘極接觸第一主動區的第一VT區域140以形成具有第一VT的第一電晶體。在一些實例中,第一電晶體可係PMOS電晶體(諸如PMOS電晶體130)、或NMOS電晶體(諸如第4圖至第10圖所示的NMOS電晶體131)。在步驟214處,形成第二閘極120b,此第二閘極接觸第一主動區110的第二VT區域142,以形成具有與第一VT不同的第二VT的第二電晶體。在一些實例中,第二電晶體可係PMOS電晶體(諸如PMOS電晶體132)、
或NMOS電晶體(諸如第4圖至第10圖所示的NMOS電晶體133)。在步驟216處形成第三閘極120c以接觸在第一閘極120a與第二閘極120b之間的第一主動區110,從而形成在第一電晶體與第二電晶體之間定位的約束電晶體。在一些實例中,約束電晶體可係PMOS電晶體(諸如PMOS約束電晶體134)、或NMOS約束電晶體(諸如第4圖至第10圖所示的NMOS約束電晶體135)。在步驟218處,第三閘極120c連接到電力軌,諸如VDD或VSS電力軌,以將約束電晶體134維持在關閉狀態並且因此將第一電晶體與第二電晶體電氣隔離。
在一些實施例中,一些或全部的方法200由電腦的處理器執行。在一些實施例中,一些或全部的方法200由下文關於第12圖論述的EDA系統300的處理器302執行。
方法200的一些或全部操作能夠作為設計程序的部分執行,此設計程序在設計室(諸如,下文關於第13圖論述的設計室320)中執行。
第12圖係根據一些實施例的電子設計自動化(EDA)系統300的方塊圖。在一些實施例中,EDA系統300包括自動放置及路由(APR)系統。在一些實施例中,EDA系統300係包括處理器302及非暫時性電腦可讀取儲存媒體304的通用計算裝置。電腦可讀取儲存媒體304可用電腦程式碼306(亦即,可執行指令集)
編碼,例如,儲存電腦程式碼306。藉由處理器302執行指令306表示(至少部分)EDA工具,此EDA工具實施例如上文關於第11圖描述的方法200的的一部分或全部(後文為所提及的製程及/或方法)。另外,製造工具303可包括在內,用於根據本文揭示的方法(諸如第11圖的方法200)的IC元件的佈局及實體實施方式。
處理器302經由匯流排308電氣耦接到電腦可讀取儲存媒體304。處理器302亦藉由匯流排308電氣耦接到I/O介面310。網路介面312亦經由匯流排308電氣連接到處理器302。網路介面312連接到網路314,使得處理器302及電腦可讀取儲存媒體304能夠經由網路314連接到外部元件。處理器302用以執行在電腦可讀取儲存媒體304中編碼的電腦程式碼306,以便致使系統300可用於執行所提及的製程及/或方法的一部分或全部。在一或多個實施例中,處理器302係中央處理單元(CPU)、多處理器、分散式處理系統、特殊應用積體電路(ASIC)、及/或適宜的處理單元。
在一或多個實施例中,電腦可讀取儲存媒體304係電子、磁性、光學、電磁、紅外、及/或半導體系統(或者設備或裝置)。例如,電腦可讀取儲存媒體304包括半導體或固態記憶體、磁帶、可移除電腦磁片、隨機存取記憶體(RAM)、唯讀記憶體(ROM)、剛性磁碟、及/或光碟。在使用光碟的一或多個實施例中,電腦可讀取
儲存媒體304包括壓縮磁碟-唯讀記憶體(CD-ROM)、壓縮磁碟-讀/寫(CD-R/W)、及/或數位視訊光碟(DVD)。
在一或多個實施例中,電腦可讀取儲存媒體304儲存電腦程式碼306,此電腦程式碼用以致使系統300可用於執行所提及的製程及/或方法的一部分或全部。在一或多個實施例中,電腦可讀取儲存媒體304亦儲存促進執行所提及製程及/或方法的一部分或全部的資訊。在一或多個實施例中,電腦可讀取儲存媒體304儲存標準單元(包括本文揭示的各種IC元件)的程式庫307。
EDA系統300包括I/O介面310。I/O介面310耦接到外部電路系統。在一或多個實施例中,I/O介面310包括用於將資訊及命令通訊到處理器302的鍵盤、小鍵盤、滑鼠、軌跡球、軌跡板、觸控式螢幕、及/或游標方向鍵。
EDA系統300亦包括耦接到處理器302的網路介面312。網路介面312允許系統300與網路314通訊,其中一或多個其他電腦系統連接到此網路。網路介面312包括:無線網路介面,諸如BLUETOOTH、WIFI、WIMAX、GPRS、或WCDMA;或有線網路介面,諸如ETHERNET、USB、或IEEE-1364。在一或多個實施例中,在兩個或多個系統300中實施所提及的製程及/或方法的一部分或全部。
系統300用以經由I/O介面310接收資訊。經由
I/O介面310接收的資訊包括下列中的一或多者:指令、資料、設計規則、標準單元程式庫、及/或用於由處理器302處理的其他參數。將資訊經由匯流排308傳遞到處理器302。EDA系統300用以經由I/O介面310接收關於UI的資訊。資訊在電腦可讀取儲存媒體304中儲存為使用者介面(UI)342。
在一些實施例中,將所提及的製程及/或方法的一部分或全部實施為由處理器執行的獨立式軟體應用。在一些實施例中,將所提及的製程及/或方法的一部分或全部實施為軟體應用,此軟體應用係額外軟體應用的一部分。在一些實施例中,將所提及的製程及/或方法的一部分或全部實施為到軟體應用的插件。在一些實施例中,將所提及的製程及/或方法中的至少一個實施為軟體應用,此軟體應用為EDA工具的一部分。在一些實施例中,將所提及的製程及/或方法的一部分或全部實施為軟體應用,此軟體應用由EDA系統300使用。在一些實施例中,包括標準單元的佈局圖使用諸如獲自CADENCE DESIGN SYSTEMS,Inc.的VIRTUOSO的工具或另一適宜佈局產生工具來產生。
在一些實施例中,製程被認為隨著在非暫時性電腦可讀取記錄媒體中儲存的程式變化。非暫時性電腦可讀取記錄媒體的實例包括但不限於外部/可移除及/或內部/內置儲存或記憶體單元,例如,下列中的一或多者:光碟(諸如DVD)、磁碟(諸如硬碟)、半導體記憶體
(諸如ROM、RAM、記憶卡)、及類似者。
如上文提及,EDA系統300的實施例可包括製造工具303,此等製造工具用於實施在儲存媒體304中儲存的製程及/或方法。例如,可對設計執行合成,其中藉由將設計與選自標準單元程式庫307的標準單元匹配將設計所期望的行為及/或功能轉換為功能等效邏輯閘極位準電路描述。合成導致功能等效邏輯閘極位準電路描述,諸如閘極位準網路連線表。基於閘極位準網路連線表,可產生用於藉由製造工具303製造積體電路的光微影遮罩。元件製造的另外態樣結合第13圖揭示,第13圖係根據一些實施例的IC製造系統301及與其相關聯的IC製造流程的方塊圖。在一些實施例中,基於佈局圖,使用製造系統301製造下列中的至少一者:(A)一或多個半導體遮罩或(B)在半導體積體電路層中的至少一個部件。
在第13圖中,IC製造系統301包括實體,諸如設計室320、遮罩室330、及IC Fab 350,此等實體在關於製造IC元件360(諸如本文揭示的積體電路元件100-103與元件104-106)的設計、開發、及製造循環及/或服務中彼此相互作用。系統301中的實體由通訊網路連接。在一些實施例中,通訊網路係單個網路。在一些實施例中,通訊網路係各種不同的網路,諸如網內網路及網際網路。通訊網路包括有線及/或無線通訊通道。每個實體與其他實體中的一或多者相互作用,並且
將服務提供到其他實體中的一或多者及/或從其他實體中的一或多者接收服務。在一些實施例中,設計室320、遮罩室330、及IC Fab 350中的兩個或多個由單個較大的公司擁有。在一些實施例中,設計室320、遮罩室330、及IC Fab 350中的兩個或多個在共用設施中共存並且使用共用資源。
設計室(或設計團隊)320產生IC設計佈局圖322。IC設計佈局圖322包括各種幾何圖案、或針對IC元件360(例如,上文論述的包括所揭示的IC結構100-106中的一或多者的IC元件)設計的IC佈局圖。幾何圖案對應於構成待製造的IC元件360的各個部件的金屬、氧化物、或半導體層的圖案。各個層結合以形成各種IC特徵。例如,IC設計佈局圖322的一部分包括待在半導體基板(諸如矽晶圓)中形成的各種IC特徵(諸如主動區域、閘電極、源極及汲極、層間互連的金屬接線或通孔、以及用於接合墊的開口)以及在半導體基板上設置的各種材料層。設計室320實施設計程序以形成IC設計佈局圖322。設計程序包括下列中的一或多者:邏輯設計、實體設計或放置及路由。IC設計佈局圖322存在於具有幾何圖案的資訊的一或多個資料檔案中。例如,IC設計佈局圖322可以GDSII檔案格式或DFII檔案格式表達。
遮罩室330包括資料準備332及遮罩製造344。遮罩室330使用IC設計佈局圖322,以製造一或多個
遮罩345,此等遮罩將用於根據IC設計佈局圖322製造IC元件360的各個層。遮罩室330執行遮罩資料準備332,其中IC設計佈局圖322轉換為代表性資料檔案(「RDF」)。遮罩資料準備332向遮罩製造344提供RDF。遮罩製造344包括遮罩寫入器。遮罩寫入器將RDF轉換為基板上的影像,諸如遮罩(主光罩)345或半導體晶圓353。IC設計佈局圖322由遮罩資料準備332操控,以符合遮罩寫入器的特定特性及/或IC Fab 350的需求。在第13圖中,將遮罩資料準備332及遮罩製造344示出為單獨的元素。在一些實施例中,遮罩資料準備332及遮罩製造344可以共同稱為遮罩資料準備。
在一些實施例中,遮罩資料準備332包括光學鄰近修正(OPC),此OPC使用微影增強技術來補償影像誤差,諸如可以由繞射、干涉、其他製程效應及類似者產生的彼等誤差。OPC調節IC設計佈局圖322。在一些實施例中,遮罩資料準備332包括進一步的解析度增強技術(RET),諸如偏軸照明、次解析度輔助特徵、相移遮罩、其他適宜技術、及類似者或其組合。在一些實施例中,亦使用反向微影技術(ILT),其將OPC視作反向成像問題。
在一些實施例中,遮罩資料準備332包括遮罩規則檢驗器(MRC),此遮罩規則檢驗器用一組遮罩產生規則檢驗已經歷OPC中的製程的IC設計佈局圖322,此
等遮罩產生規則含有某些幾何及/或連接性限制以確保足夠裕度,用於考慮在半導體製造製程中的變化性及類似者。在一些實施例中,MRC修改IC設計佈局圖322以在遮罩製造344期間補償限制,此可抵消由OPC執行的部分修改,以便滿足遮罩產生規則。
在一些實施例中,遮罩資料準備332包括模擬處理的微影製程檢驗(LPC),此處理將由IC Fab 350實施以製造IC元件360。LPC基於IC設計佈局圖322模擬此處理以產生模擬的製造元件,諸如IC元件360。在LPC模擬中的處理參數可以包括與IC製造循環的各個製程相關聯的參數、與用於製造IC的工具相關聯的參數、及/或製造製程的其他態樣。LPC考慮到各種因素,諸如天線影像對比、焦點深度(「DOF」)、遮罩誤差增強因素(「MEEF」)、其他適宜因素、及類似者或其組合。在一些實施例中,在模擬的製造元件已經由LPC產生之後,若模擬的元件形狀不足夠緊密而不滿足設計規則,則將重複OPC及/或MRC以進一步細化IC設計佈局圖322。
應當理解,遮罩資料準備332的以上描述出於清晰目的已經簡化。在一些實施例中,資料準備332包括額外特徵,諸如包括邏輯運算(LOP)以根據製造規則修改IC設計佈局圖322。此外,在資料準備332期間應用到IC設計佈局圖322的製程可以各種不同次序執行。
在遮罩資料準備332之後並且在遮罩製造344期間,基於經修改的IC設計佈局圖322製造遮罩345或遮罩345的群組。在一些實施例中,遮罩製造344包括基於IC設計佈局圖322執行一或多次微影曝光。在一些實施例中,電子束(e束)或多個電子束的機制用於基於經修改的IC設計佈局圖322在遮罩(光罩或主光罩)345上形成圖案。遮罩345可以在各種技術中形成。在一些實施例中,遮罩345使用二元技術形成。在一些實施例中,遮罩圖案包括不透明區域及透明區域。用於暴露已經在晶圓上塗佈的影像敏感材料層(例如,光阻劑)的輻射光束(諸如紫外(UV)光束)由不透明區域阻擋並且透射穿過透明區域。在一個實例中,遮罩345的二元遮罩版本包括透明基板(例如,熔凝石英)及在二元遮罩的不透明區域中塗佈的不透明材料(例如,鉻)。在另一實例中,遮罩345使用相轉移技術形成。在遮罩345的相轉移遮罩(PSM)版本中,在相轉移遮罩上形成的圖案中的各種特徵用以具有適當相位差,以增強解析度及成像品質。在各個實例中,相轉移遮罩可以係衰減PSM或交替PSM。由遮罩製造344產生的遮罩用在各種製程中。例如,此種遮罩在離子植入製程中使用以在半導體晶圓353中形成各種摻雜區域、在蝕刻製程中使用以在半導體晶圓353中形成各種蝕刻區域、及/或在其他適宜製程中使用。
IC Fab 350包括晶圓製造352。IC Fab 350
係包括用於製造各種不同的IC產品的一或多個製造設施的IC製造公司。在一些實施例中,IC Fab 350係半導體代工廠。例如,可存在用於複數種IC產品的前端製造(FEOL製造)的製造設施,而第二製造設施可為互連及封裝IC產品提供後端製造(BEOL製造),並且第三製造設施可為代工廠公司提供其他服務。
IC Fab 350使用由遮罩室330製造的遮罩345來製造IC元件360。因此,IC Fab 350至少間接地使用IC設計佈局圖322來製造IC元件360。在一些實施例中,半導體晶圓353藉由IC Fab 350使用遮罩345製造以形成IC元件360。在一些實施例中,IC製造包括至少間接地基於IC設計佈局圖322執行一或多次微影曝光。半導體晶圓353包括矽基板或其上形成有材料層的其他適當基板。半導體晶圓353進一步包括下列中的一或多者:各種摻雜區域、介電特徵、多級互連、及類似者(在後續的製造步驟處形成)。
因此,所揭示的實施例包括積體電路元件,此積體電路元件包括第一電力軌及在第一方向上延伸的第一主動區。複數個閘極接觸第一主動區並且在垂直於第一方向的第二方向上延伸。第一電晶體包括第一主動區及第一個閘極。第一電晶體具有第一VT。第二電晶體包括第一主動區及第二個閘極,並且第二電晶體具有與第一VT不同的第二VT。約束電晶體在第一電晶體與第二電晶體之間定位。約束電晶體包括第一主動區及第三個閘
極,其中第三閘極連接到第一電力軌。
根據其他揭示的實施例,第三閘極藉由一第一導電連通柱連接到第一電力軌。第一主動區包括一鰭。約束電晶體可以是一PMOS電晶體,並且第一電力軌可以是一VDD電力軌。約束電晶體可以是一NMOS電晶體,並且第一電力軌可以是一VSS電力軌。該些第一及第二電晶體可以是PMOS電晶體。該些第一及第二電晶體可以是NMOS電晶體。
根據其他揭示的實施例,該些閘極可以是多晶矽閘極,且積體電路元件進一步包含一VSS電力軌;一第二主動區在一第一方向上延伸,其中該些多晶矽閘極接觸第二主動區;一第一NMOS電晶體包括第二主動區及第一多晶矽閘極,第一NMOS電晶體具有第一VT;一第二NMOS電晶體包括第二主動區及第二多晶矽閘極,第二NMOS電晶體具有第二VT;以及一NMOS約束電晶體在第一NMOS電晶體與第二NMOS電晶體之間定位,NMOS約束電晶體包括第一主動區及第三多晶矽閘極,其中第三多晶矽閘極連接到VSS電力軌,並且其中第三多晶矽閘極包括在該些第一及第二主動區之間的一切割多晶矽。
根據其他揭示的實施例,第三多晶矽閘極藉由一第二導電連通柱連接到VSS電力軌。第三多晶矽閘極藉由一金屬層及一第三導電連通柱連接到VSS電力軌。
根據其他揭示的實施例,半導體元件包括第一電力
軌及第二電力軌。第一PMOS電晶體包括在第一方向上延伸的第一鰭及第一閘極。第一PMOS電晶體具有第一VT,並且第一閘極在垂直於第一方向的第二方向上延伸。第二PMOS電晶體包括第一鰭及在第二方向上延伸的第二閘極。第二PMOS電晶體具有與第一VT不同的第二VT。第二閘極連接到第一電力軌。第二鰭在第一方向上延伸。第一NMOS電晶體包括第二鰭及第一閘極。第一NMOS電晶體具有第一VT。第二NMOS電晶體包括第二鰭及第二閘極。第二NMOS電晶體具有第二VT。第二閘極連接到第二電力軌。
根據其他揭示的實施例,第一閘極連接到第二電力軌,並且第二閘極經由第一PMOS電晶體連接到第一電力軌。第一閘極連接到第一電力軌,並且第二閘極經由第一NMOS電晶體連接到第二電力軌。第二閘極經由在第一方向上延伸的一金屬層及在第二方向上延伸的一金屬接線連接到第一PMOS電晶體。
根據其他揭示的實施例,積體電路元件進一步包含:一第三PMOS電晶體包括該第一鰭及一第三閘極,第三PMOS電晶體具有第二VT,其中第二PMOS電晶體在該些第一及第三PMOS電晶體之間;一第三NMOS電晶體包括第一鰭及第三閘極,第三NMOS電晶體具有第二VT,其中第二NMOS電晶體在該些第一及第三NMOS電晶體之間。該些第一、第二及第三閘極包含相應的第一、第二及第三多晶矽閘極,並且第二多晶矽閘
極包括在該些第一及第二鰭之間的一切割多晶矽,其中第二多晶矽閘極直接連接到第一電力軌。
根據又一些實施例,一種積體電路元件的製造方法包括在基板上形成第一主動區,其中第一主動區具有第一VT區域及第二VT區域。形成第一閘極,此第一閘極接觸第一主動區的第一VT區域以形成具有第一VT的第一電晶體。形成第二閘極以接觸第一主動區的第二VT區域來形成具有與第一VT不同的第二VT的第二電晶體。形成第三閘極以接觸在第一閘極與第二閘極之間的第一主動區以形成在第一電晶體與第二電晶體之間定位的約束電晶體。第三閘極連接到電力軌以將約束電晶體維持在關閉狀態。
根據又一些實施例,約束電晶體可以是一PMOS電晶體並且將第三閘極連接到電力軌以將約束電晶體維持在關閉狀態包括將第三閘極連接到一VDD電力軌。將第三閘極連接到VDD電力軌包括提供在第三閘極與該VDD電力軌之間延伸的一導電連通柱。
根據又一些實施例,該些第一及第二電晶體以及約束電晶體可以是PMOS電晶體,方法進一步包含:在基板上形成一第二主動區,第二主動區包括第一VT區域及第二VT區域;形成第一閘極以進一步接觸第二主動區來形成具有第一VT的一第一NMOS電晶體;形成第二閘極以進一步接觸第二主動區來形成具有第二VT的一第二NMOS電晶體;形成第三閘極以進一步接觸
第二主動區來形成在第一NMOS電晶體與第二NMOS電晶體之間定位的一NMOS約束電晶體;以及將第三閘極連接到一第二電力軌以將NMOS約束電晶體維持在一關閉狀態。
上文概述若干實施例的特徵,使得熟習此項技術者可更好地理解本揭示的態樣。熟習此項技術者應瞭解,可輕易使用本揭示作為設計或修改其他製程及結構的基礎,以便執行本文所介紹的實施例的相同目的及/或實現相同優點。熟習此項技術者亦應認識到,此類等效構造並未脫離本揭示的精神及範疇,且可在不脫離本揭示的精神及範疇的情況下產生本文的各種變化、取代及更改。
100:積體電路元件
110:第一主動區
112:第一電力軌
120a:多晶矽閘極
120b:多晶矽閘極
120c:多晶矽閘極
120d:多晶矽閘極
120e:多晶矽閘極
122:導電連通柱
130:電晶體
132:電晶體
134:電晶體
140:第一VT區域
142:第二VT區域
Claims (10)
- 一種積體電路元件,包含:一第一電力軌;一第一主動區,在一第一方向上延伸,其中該第一主動區包括一第一閾值電壓(VT)區域及一第二VT區域;複數個閘極,接觸該第一主動區並且在垂直於該第一方向的一第二方向上延伸;一第一電晶體,包括該第一主動區的該第一VT區域及該些閘極的一第一閘極,該第一閘極接觸該第一VT區域,該第一電晶體具有一第一閾值電壓(VT);一第二電晶體,包括該第一主動區的該第二VT區域及該些閘極的一第二閘極,該第二閘極接觸該第二VT區域,該第二電晶體具有與該第一VT不同的一第二VT;以及一約束電晶體,在該第一電晶體與該第二電晶體之間定位,該約束電晶體包括在該第一閘極與該第二閘極之間的該第一主動區及該些閘極的一第三閘極,其中該第三閘極接觸在該第一閘極與該第二閘極之間的該第一主動區,該第三閘極連接到該第一電力軌,該第一電力軌配置以將該約束電晶體維持在一關閉狀態。
- 如請求項1所述的積體電路元件,其中該第三閘極藉由一第一導電連通柱連接到該第一電力軌。
- 如請求項1所述的積體電路元件,其中該約束電晶體係一PMOS電晶體,並且其中該第一電力軌係一VDD電力軌。
- 如請求項1所述的積體電路元件,其中該約束電晶體係一NMOS電晶體,並且其中該第一電力軌係一VSS電力軌。
- 如請求項3所述的積體電路元件,其中該些第一及第二電晶體係PMOS電晶體。
- 如請求項4所述的積體電路元件,其中該些第一及第二電晶體係NMOS電晶體。
- 一種半導體元件,包含:一第一電力軌;一第二電力軌;一第一鰭,在一第一方向上延伸;一第一PMOS電晶體,包括該第一鰭及一第一閘極,該第一PMOS電晶體具有一第一閾值電壓(VT),該第一閘極在垂直於該第一方向的一第二方向上延伸;一第二PMOS電晶體,包括該第一鰭及在該第二方向上延伸的一第二閘極,該第二PMOS電晶體具有與該第一VT不同的一第二VT,並且其中該第二閘極連接到該第一電力軌;一第二鰭,在該第一方向上延伸;一第一NMOS電晶體,包括該第二鰭及該第一閘極,該第一NMOS電晶體具有該第一VT;一第二NMOS電晶體,包括該第二鰭及該第二閘極,該第二NMOS電晶體具有該第二VT,並且其中該第二閘極連接到該第二電力軌。
- 如請求項7所述的半導體元件,其中該第一閘極連接到該第二電力軌,並且其中該第二閘極經由該第一PMOS電晶體連接到該第一電力軌。
- 如請求項7所述的半導體元件,其中該第一閘極連接到該第一電力軌,並且其中該第二閘極經由該第一NMOS電晶體連接到該第二電力軌。
- 一種積體電路元件的製造方法,包含:在一基板上形成一第一主動區,該第一主動區包括一第一閾值電壓(VT)區域及一第二VT區域;形成一第一閘極,該第一閘極接觸該第一主動區的該第一VT區域以形成具有一第一VT的一第一電晶體;形成一第二閘極,該第二閘極接觸該第一主動區的該第二VT區域以形成具有與該第一VT不同的一第二VT的一第二電晶體;形成一第三閘極,該第三閘極接觸在該第一閘極與該第二閘極之間的該第一主動區以形成在該第一電晶體與該第二電晶體之間定位的一約束電晶體;以及將該第三閘極連接到一電力軌以將該約束電晶體維持在一關閉狀態。
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KR102442273B1 (ko) | 2022-09-08 |
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KR20200146026A (ko) | 2020-12-31 |
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