TWI753291B - Stackable chip package - Google Patents

Abstract

A stackable chip package includes a plurality of chips, a dielectric layer, at least one redistribution layer and at least one external terminal. The plurality of chips is stacked with each other to be stacked chips encapsulated on a substrate, and conductive elements of the stacked chips are exposed to the encapsulation when the substrate is removed. The dielectric layer is disposed on the stacked chips, and has openings aligning to the conductive elements. The redistribution layer is disposed inside the openings to contact the conductive elements. The external terminal is disposed on the redistribution layer for providing an electrical transmission channel of the stackable chip package.

Description

Stacked Die Package

The present invention provides a semiconductor package, especially a stacked chip package.

The stacking technique of multiple chips has been applied in various semiconductor packaging structures to achieve the requirement of minimization of component set. Wire bonding and TSV with microbumps are common techniques for electrically connecting stacked chips and external contacts. However, these conventional approaches have the following disadvantages.

When the die is wire-bonded to external contacts, space should be left between the bond wires to avoid accidental conduction of adjacent bond wires. This spacing inevitably increases the size of conventional stacked die packages. Therefore, the conventional stacked die package with bonding wires cannot effectively reduce its volume. In addition, the bonding wires of the conventional stacked chip package cannot be bonded at the same time, so the wire bonding process takes a long time to manufacture. As a result, conventional stacked die packages fabricated using wire-bonding processes have lower throughput efficiencies.

When chips are bonded using microbumping and TSV, TSV increases stack height and processing complexity, resulting in higher thickness and lower manufacturing yields for stacked chip packages. Furthermore, the requirements for alignment and positioning accuracy between micro-bumps are extremely high. If the size of the conventional stacked chip package increases, the displacement between the micro-bumps will increase accordingly, resulting in poor packaging yield.

The present invention provides a stacked chip package to solve the above problems.

The claimed scope of the present invention further discloses a stacked chip package, which includes a plurality of chips, an insulating layer, at least one redistribution layer, and at least one external contact. The plurality of chips are stacked on each other to form a stacked chip and packaged on a substrate, and the conductive elements of the stacked chips are exposed to the packaging material after the substrate is removed. The insulating layer is disposed on the stacked wafers. The insulating layer has openings, which are respectively aligned with the conductive elements. The redistribution layer is disposed within the openings to contact the conductive elements. The external contact is disposed on the at least one redistribution layer and is used as a circuit transmission channel of the stacked chip package.

10: Stacked die package

12: Wafer

12': stacked wafers

121: end edge

13: Side

14: Insulation layer

16: Redistribution layer

18: External contact

20: Conductive elements

22: Opening

24: Substrate

26: Metal carrier

28: Release film

30: insulating film

32: The first packaging material

34: Second encapsulation material

36: Insulation layer

38: Metal Thin Film

A: line

S200, S202, S204, S206, S208, S210, S212, S214, S216: Steps

FIG. 1 is a schematic diagram of a stacked chip package according to an embodiment of the present invention.

FIG. 2 is a flowchart of a manufacturing method for fabricating a stacked chip package according to an embodiment of the present invention.

3A, 4A, 5A, 6A, 7A, 8A, 9A and 10A are schematic views of the appearance of the stacked chip package in different operation stages according to an embodiment of the present invention.

Figures 3B, 4B, 5B, 6B, 7B, 8B, 9B and 10B are prior views of the stacked chip package at different stages of operations according to embodiments of the present invention.

FIG. 11 is a front view of the stacked die package shown in FIG. 1 .

Referring to FIG. 1 , the stacked chip package 10 may include a plurality of chips 12 , an insulating layer 14 , at least one redistribution layer 16 , and at least one external contact 18 . The number of the redistribution layer 16 and the external contacts 18 is not limited to the embodiment shown in the drawings, but depends on design requirements. A plurality of wafers 12 may be stacked on each other to form a stacked wafer 12'. The plurality of conductive elements 20 of the plurality of wafers 12 may be located on the sides 13 of the stacked wafers 12' and exposed to the openings 22 of the insulating layer 14. The redistribution layer 16 and the external contact 18 can be arranged on the insulating layer 14, And the conductive element 20 is connected through the opening 22 . The manufacturing method of the present invention can connect the redistribution layer 16 and the external contacts 18 to the conductive elements 20 at the same time to establish the circuit transmission path of the stacked chip package 10 .

The stacked die 12' formed by the combination of the plurality of die 12 can be encapsulated with a specific encapsulation material. When the stacked wafers 12' are encapsulated by the first encapsulation material and the second encapsulation material, the conductive elements 20 of the plurality of wafers 12 may still be exposed through the encapsulation material. The insulating layer 14 may be disposed on the outer surface of the stacked wafer 12', where the conductive elements 20 are located. The redistribution layer 16 may be disposed on the insulating layer 14 and connected to the conductive element 20 through the opening 22 of the insulating layer 14 . The redistribution layer 16 can be made of metal material by sputtering, and is used as an adhesion layer, a diffusion barrier layer and a conductive layer in the ball placement process. The external contacts 18 can be disposed on the redistribution layer 16 to change the position of the contact points of the stacked chip package 10 , so that the stacked chip package 10 can be applied to various types of modules.

The manufacturing method described in FIG. 2 can be applied to the stacked die package 10 shown in FIG. 1 . Referring to FIGS. 3A and 3B, step S200 is performed to contact the upper surface of one wafer 12 against the lower surface of another wafer 12, and stack a plurality of wafers 12 accordingly to form a stacked wafer 12'. Adhesive may be applied between adjacent wafers 12 to secure the plurality of wafers 12 to each other. By the die attach technique, the plurality of chips 12 are preferably staggered with each other when stacked. Referring to FIGS. 4A and 4B , step S202 is performed to package the stacked chip 12 ′ with the first packaging material 32 . The first encapsulation material 32 is used to limit relative movement of the adjacent wafers 12 and may be used to protect the stacked wafers 12'.

Referring to FIGS. 5A and 5B, step S204 is executed to cut off the edge 121 of the stacked wafer 12' to expose the conductive element 20 for subsequent contact alignment, and further cut the non-exposed contacts of the stacked wafer 12'. The other end edges 122 of the dots are used for edge alignment purposes. Please refer to FIG. 6A and FIG. 6B , step S206 is executed, and the stacked wafer 12' is turned over to make the side of the stacked wafer 12' with the conductive elements 20 13 faces the substrate 24 , whereby the side surface 13 is disposed on the substrate 24 . Substrate 24 may include metal carrier 26 and release film 28 . Stacked wafer 12' may be disposed on metal carrier 26 using release film 28. The substrate 24 may be bonded to the stacked wafer 12' using die bonding techniques and metal sputtering techniques.

Please refer to FIG. 7A and FIG. 7B , step S208 is executed, and the stacked chip 12 ′ and the substrate 24 are packaged with the second packaging material 34 . The second encapsulation material 34 is used to fix the relative movement between adjacent stacked die 12' and can protect the stacked die 12' in a wrapping manner. Referring to FIGS. 8A and 8B , step S210 is executed to turn over the stacked chip 12 ′ packaged by the second packaging material 34 , and remove the release film 28 to separate the metal carrier 26 from the stacked chip 12 ′. At this time, the conductive element 20 is exposed to the side of the stacked wafer 12'. Referring to FIGS. 9A and 9B, step S212 is performed to form the insulating film 30 on the stacked wafer 12'. The insulating film 30 may be etched according to the position of the conductive element 20 to form the insulating layer 14 having the openings 22 . In other possible implementations, the insulating layer 14 with the openings 22 may be prefabricated, and then disposed on the stacked wafer 12' in such a manner that the openings 22 are aligned with the conductive elements 20.

Referring to FIG. 10A and FIG. 10B , step S214 is executed to dispose the redistribution layer 16 on the insulating layer 14 and contact the conductive element 20 through the opening 22 . In this embodiment, another insulating layer 36 may also be formed on the redistribution layer 16 , and a metal thin film 38 may be formed on the insulating layer 36 to contact the redistribution layer 16 through the opening of the insulating layer 36 . Referring to FIG. 11 , step S216 is executed to set the external contact 18 on the metal film 38 , and the external contact 18 can be electrically connected to the conductive element 20 through the redistribution layer 16 and the metal film 38 . Finally, the stacked wafer 12' can be cut along line A. The external contacts 18 may be solder balls, solder paste, contact electrodes or pins.

In the present invention, the stacked chip package is to stack a plurality of chips to form a chip stack assembly, and then turn the chip stack assembly so that the side surface of the chip stack assembly with conductive elements is arranged on the base Then, the chip stack assembly and the substrate are packaged with a second packaging material. The stacked chip package of the present invention does not carry out the removal of the second packaging material, but separates the substrate and the chip stack combination to expose the side surface with the conductive elements. The insulating layer, the redistribution layer, the metal film and the external contacts are sequentially disposed on the chip stack according to the redistribution layer process (RDL) and the under bump metallurgy process (UBM). Therefore, the present invention can rapidly manufacture a stacked chip package with high capacity, thereby reducing manufacturing cost and increasing productivity, and can further provide electromagnetic shielding function by using its specific structural design.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

S200, S202, S204, S206, S208, S210, S212, S214, S216: Steps

Claims (10)

A stacked chip package includes: a first packaging material with a first recessed space; a second packaging material with a second recessed space, the second packaging material wrapping the first packaging material to make the An inner bottom surface of the second recessed space contacts an outer bottom surface of the first packaging material; a plurality of chips are stacked on each other to form a stacked chip, and the stacked chips are arranged in the first recessed space to limit the stacked chips Relative movement of adjacent chips within, the stacked chips are disposed in the second concave space and packaged in a substrate to limit the relative movement between the stacked chips, and the conductive elements of the stacked chips are removed after the substrate is removed exposed to the first packaging material; an insulating layer disposed on the stacked chips, the insulating layer having openings, respectively aligned with the conductive elements; at least one redistribution layer disposed in the openings to contact the conductive elements components; and at least one external contact, disposed on the at least one redistribution layer, used as a circuit transmission channel of the stacked chip package. The stacked chip package as claimed in claim 1, wherein the plurality of chips are stacked with the upper surface of one chip contacting the lower surface of another chip, and the conductive elements are disposed on one side of the stacked chips. The stacked chip package of claim 2, wherein the stacked chips are turned over so that the conductive elements face upward for packaging. The stacked chip package of claim 1, wherein an end edge of the stacked chips is cut away to align the conductive elements on a side of the stacked chips. The stacked die package of claim 4, wherein other ends of the stacked die are cut away for edge alignment. The stacked chip package of claim 1, wherein the plurality of chips are packaged to form the stacked chips, and the stacked chips are disposed on a substrate for another package. The stacked chip package of claim 6, wherein the substrate comprises a metal carrier and a release film, the stacked chips are disposed on the metal carrier by the release film, and removal of the release film can separate the metal carrier with these stacked wafers. The stacked chip package of claim 1, wherein an insulating film is disposed on the stacked chips, and the insulating film is etched according to the positions of the conductive elements to form the insulating layer having the openings. The stacked chip package of claim 1, wherein the substrate is bonded to the stacked chips using die bonding technology and metal sputtering technology. The stacked chip package of claim 1, wherein the plurality of chips are staggered and stacked using a die attach technique.

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