TW202040784A - Stackable chip package - Google Patents

Abstract

A stackable chip package includes a plurality of chips, a dielectric layer, at least one redistribution layer and at least one external terminal. The plurality of chips is stacked with each other to be stacked chips encapsulated on a substrate, and conductive elements of the stacked chips are exposed to the encapsulation when the substrate is removed. The dielectric layer is disposed on the stacked chips, and has openings aligning to the conductive elements. The redistribution layer is disposed inside the openings to contact the conductive elements. The external terminal is disposed on the redistribution layer for providing an electrical transmission channel of the stackable chip package.

Description

Stacked chip package

The invention provides a semiconductor package, especially a stacked chip package.

The stacking technology of multiple chips has been applied to a variety of semiconductor packaging structures to achieve the requirement of minimizing the assembly of components. The wire bonding method and the silicon through hole method with micro bumps are common technologies for electrically connecting stacked chips and external contacts. However, these traditional practices have the following disadvantages.

When the chip is connected to external contacts by wire bonding, a space must be reserved between the bonding wires to avoid accidental conduction of adjacent bonding wires. This gap inevitably increases the size of the traditional stacked chip package. Therefore, the traditional stacked chip package with bonding wires cannot effectively reduce its volume. In addition, the bonding wires of the traditional stacked chip package cannot be bonded at the same time, so the wire bonding process requires a long manufacturing time. As a result, the traditional stacked chip package manufactured by the wire bonding process will have lower productivity efficiency.

When the wafers are bonded by the micro bump and silicon through hole method, the silicon through hole method will increase the stack height and increase the processing complexity, resulting in a higher thickness of the stacked chip package and low manufacturing yield. Furthermore, the alignment and positioning accuracy between the micro bumps are extremely demanding. If the size of the traditional stacked chip package increases, the displacement between the micro bumps will increase correspondingly, resulting in poor package yield.

The present invention provides a stacked chip package to solve the above-mentioned problems.

The patent application scope of the present invention also discloses a stacked chip package, which includes a plurality of chips, an insulating layer, at least one redistribution layer, and at least one external contact. The plurality of chips are stacked on each other to form a stacked chip and packaged on a substrate, and the conductive elements of the stacked chips are exposed to the packaging material after the substrate is removed. The insulating layer is disposed on the stacked wafers. The insulating layer has openings which are respectively aligned with the conductive elements. The redistribution layer is arranged in the openings to contact the conductive elements. The external contact is arranged on the at least one redistribution layer and is used as a circuit transmission channel of the stacked chip package.

Please refer to FIG. 1, the stacked chip package 10 may include a plurality of chips 12, an insulating layer 14, at least one redistribution layer 16, and at least one external contact 18. The number of the redistribution layer 16 and the external contacts 18 is not limited to the embodiment shown in the drawings, and depends on the design requirements. A plurality of wafers 12 may be stacked on each other to form a stacked wafer 12'. The plurality of conductive elements 20 of the plurality of wafers 12 may be located on the side surface 13 of the stacked wafer 12' and exposed to the opening 22 of the insulating layer 14. The redistribution layer 16 and the external contact 18 may be disposed on the insulating layer 14 and connected to the conductive element 20 through the opening 22. The manufacturing method of the present invention can connect the redistribution layer 16 and the external contact 18 to the conductive element 20 at the same time to establish a circuit transmission channel of the stacked chip package 10.

The stacked chip 12' formed by combining a plurality of chips 12 can be packaged with a specific packaging material. When the stacked chips 12' are packaged by the first packaging material and the second packaging material, the conductive elements 20 of the plurality of chips 12 can still be exposed through the packaging material. The insulating layer 14 may be disposed on the outer surface of the stacked wafer 12', and the other surface is the location of the conductive element 20. The redistribution layer 16 may be disposed on the insulating layer 14 and connected to the conductive element 20 through the opening 22 of the insulating layer 14. The redistribution layer 16 can be made of a metal material by sputtering, and serves as an adhesion layer, a diffusion barrier layer and a conductive layer in the ball planting process. The external contacts 18 can be provided on the redistribution layer 16 to change the position of the contact points of the stacked chip package 10, so the stacked chip package 10 can be applied to various types of modules.

The manufacturing method described in FIG. 2 can be applied to the stacked chip package 10 shown in FIG. 1. Referring to FIGS. 3A and 3B, step S200 is performed to contact the top surface of one chip 12 against the bottom surface of another chip 12, and stack a plurality of chips 12 accordingly to form a stacked chip 12'. Adhesive can be applied between adjacent wafers 12 to fix a plurality of wafers 12 together. With die bonding technology, a plurality of chips 12 are preferably arranged in a staggered arrangement when stacked. Referring to FIGS. 4A and 4B, step S202 is performed to package the stacked chip 12' with the first packaging material 32. The first packaging material 32 is used to limit the relative movement of adjacent wafers 12 and can be used to protect stacked wafers 12'.

Referring to FIGS. 5A and 5B, step S204 is performed to cut off the edge 121 of the stacked chip 12' to expose the conductive element 20 for subsequent contact alignment, and further cut away the non-exposed connections of the stacked chip 12' The other end edges 122 are clicked to achieve the purpose of edge alignment. Referring to FIGS. 6A and 6B, step S206 is performed to turn the stacked wafer 12' over so that the side surface 13 with the conductive element 20 of the stacked wafer 12' faces the substrate 24, thereby setting the side surface 13 on the substrate 24. The substrate 24 may include a metal carrier 26 and a release film 28. The stacked wafers 12' can be disposed on the metal carrier 26 using the release film 28. The substrate 24 can be bonded to the stacked wafer 12' by using die bonding technology and metal sputtering technology.

Referring to FIGS. 7A and 7B, step S208 is performed to encapsulate the stacked chip 12' and the substrate 24 with the second packaging material 34. The second packaging material 34 is used to fix the relative movement between the adjacent stacked chips 12', and can protect the stacked chips 12' in a coating manner. Referring to FIGS. 8A and 8B, step S210 is performed to turn over the stacked chip 12' encapsulated by the second packaging material 34, and the release film 28 is removed to separate the metal carrier 26 from the stacked chip 12'. At this time, the conductive element 20 Will be exposed on the side of the stacked wafer 12'. Referring to FIGS. 9A and 9B, step S212 is performed to form an insulating film 30 on the stacked wafer 12'. The insulating film 30 can be etched according to the position of the conductive element 20 to form the insulating layer 14 having the opening 22. In other possible implementations, the insulating layer 14 with the opening 22 can be fabricated in advance, and then placed on the stacked chip 12' in such a way that the opening 22 is aligned with the conductive element 20.

Please refer to FIG. 10A and FIG. 10B to perform step S214 to dispose the redistribution layer 16 on the insulating layer 14 and contact the conductive element 20 through the opening 22. In this embodiment, another insulating layer 36 can also be formed on the redistribution layer 16, and the metal film 38 can be formed on the insulating layer 36 to contact the redistribution layer 16 through the opening of the insulating layer 36. Referring to FIG. 11, step S216 is performed to set the external contact 18 on the metal film 38, and the external contact 18 can be electrically connected to the conductive element 20 through the redistribution layer 16 and the metal film 38. Finally, the stacked wafer 12' can be cut along the line A. The external contacts 18 can be solder balls, solder paste, contact electrodes or pins.

In the present invention, the stacked chip package is to stack a plurality of chips to form a chip stack combination, and then turn the chip stack combination so that the side of the chip stack combination with conductive elements is set on the substrate, and then the chip stack combination and the substrate Two packaging materials for packaging. The stacked chip package of the present invention does not remove the second packaging material, but separates the substrate and the chip stack to expose the side surface with the conductive element. The insulating layer, the redistribution layer, the metal film and the external contacts are arranged in the chip stack assembly in sequence according to the redistribution layer process (RDL) and the under bump metallurgy process (UBM). Therefore, the present invention can quickly manufacture stacked chip packages with high-capacity characteristics, thereby reducing manufacturing costs and increasing productivity, and can further provide electromagnetic shielding functions by using its specific structure design. The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention should fall within the scope of the present invention.

10: Stacked chip package 12: chip 12’: Stacked chips 121: end 13: side 14: Insulation layer 16: Redistribution layer 18: External contact 20: conductive element 22: opening 24: substrate 26: Metal carrier 28: release film 30: insulating film 32: The first packaging material 34: second packaging material 36: insulating layer 38: metal film A: Line S200, S202, S204, S206, S208, S210, S212, S214, S216: steps

Figure 1 is a schematic diagram of a stacked chip package according to an embodiment of the present invention. FIG. 2 is a flowchart of a manufacturing method for manufacturing a stacked chip package according to an embodiment of the present invention. Fig. 3A, Fig. 4A, Fig. 5A, Fig. 6A, Fig. 7A, Fig. 8A, Fig. 9A and Fig. 10A are schematic diagrams of the appearance of the stacked chip package in different stages of operation according to the embodiment of the present invention. 3B, 4B, 5B, 6B, 7B, 8B, 9B, and 10B are front views of the stacked chip package in different stages of operation according to the embodiment of the present invention. Figure 11 is a front view of the stacked chip package shown in Figure 1.

S200, S202, S204, S206, S208, S210, S212, S214, S216: steps

Claims (10)

A stacked chip package, which includes: A plurality of chips are stacked on each other to form a stacked chip and packaged on a substrate, and the conductive elements of the stacked chips are exposed to the packaging material after the substrate is removed; An insulating layer disposed on the stacked wafers, the insulating layer having openings aligned with the conductive elements; At least one redistribution layer is disposed in the openings to contact the conductive elements; and At least one external contact is arranged on the at least one redistribution layer and used as a circuit transmission channel of the stacked chip package. The stacked chip package according to claim 1, wherein the plurality of chips are stacked with the top surface of one chip in contact with the bottom surface of another chip, and the conductive elements are arranged on one side of the stacked chips. The stacked chip package according to claim 2, wherein the stacked chips are turned over so that the conductive elements face upward for packaging. The stacked chip package according to claim 1, wherein one end of the stacked chips is cut to align the conductive elements on one side of the stacked chips. The stacked chip package according to claim 4, wherein the other edges of the stacked chips are cut off for edge alignment. The stacked chip package according to claim 1, wherein the plurality of chips are packaged to form the stacked chips, and the stacked chips are arranged on a substrate for another package. The stacked chip package according to claim 6, wherein the substrate includes a metal carrier and a release film, the stacked chips are disposed on the metal carrier by using the release film, and the removal of the release film can separate the metal carrier Stack the wafers with these. The stacked chip package according to claim 1, wherein an insulating film is provided on the stacked chips, and the insulating film is etched according to the positions of the conductive elements to form the insulating layer with the openings. The stacked chip package according to claim 1, wherein the substrate is bonded to the stacked chips using die bonding technology and metal sputtering technology. The stacked chip package according to claim 1, wherein the plurality of chips are staggered stacked by die bonding technology.

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