TWI752617B - Wafer offset correction method for maskless exposure machine - Google Patents

Wafer offset correction method for maskless exposure machine Download PDF

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TWI752617B
TWI752617B TW109130356A TW109130356A TWI752617B TW I752617 B TWI752617 B TW I752617B TW 109130356 A TW109130356 A TW 109130356A TW 109130356 A TW109130356 A TW 109130356A TW I752617 B TWI752617 B TW I752617B
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wafer
exposure machine
substrate
maskless exposure
chip
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TW202210933A (en
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劉大有
簡志樺
賴建華
陳世勳
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劉大有
簡志樺
賴建華
陳世勳
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Abstract

一種無光罩曝光機之晶片偏移校正方法,其中晶片結合於底材上,底材具有複數個接孔,晶片上具有複數個接點,並分別於各接點上預定曝光形成一連接至各接孔之導接部;此校正方法包括有:以一第一預掃描手段取得晶片的狀態資訊,包括形狀及位置資訊;將前述晶片的狀態資訊與一基準狀態進行比對,並計算將該基準狀態修正為與晶片的狀態資訊一致的補償值;依補償值計算出一曝光區域的補償段,使各導接部可於對應之接孔位置上形成曝光圖形。A method for correcting wafer offset of a maskless exposure machine, wherein the wafer is bonded to a substrate, the substrate has a plurality of contact holes, the wafer has a plurality of contacts, and each contact is pre-exposed to form a connection to the The guiding part of each contact hole; the calibration method includes: obtaining state information of the chip by a first pre-scanning method, including shape and position information; comparing the state information of the chip with a reference state, and calculating the The reference state is corrected to a compensation value consistent with the state information of the wafer; a compensation segment of an exposure area is calculated according to the compensation value, so that each lead part can form an exposure pattern at the corresponding contact hole position.

Description

無光罩曝光機之晶片偏移校正方法Wafer offset correction method for maskless exposure machine

本發明與黃光微影製程有關,尤指一種無光罩曝光機之晶片偏移校正方法。 The present invention relates to a yellow light lithography process, in particular to a wafer offset correction method for a maskless exposure machine.

在積體電路的製造過程中,晶片具有複數個接點,而晶圓底材設有對應接點數量的接孔,將晶片「黏晶」在底材上後,接著進行曝光,即可在各接點處形成構成電路的導接部,其中各導接部之另一端理應成形於對應各接孔的位置,才能在後續製程中使外部電路正確連接該導接部。然而如第7A圖所示,將晶片6結合在底材7上後,有時會因操作誤差而發生偏離標準位置的情形,因而如第8圖所示地使預定曝光形成的導接部81也隨之偏離正確位置,以致無法與底材7的接孔71準確對應,難以確保後續製程中與外部電路連接的正確性。 In the manufacturing process of integrated circuits, the chip has a plurality of contacts, and the substrate of the wafer is provided with contact holes corresponding to the number of contacts. Each contact is formed with a conductive portion forming a circuit, wherein the other end of each conductive portion should be formed at a position corresponding to each contact hole, so that the external circuit can be correctly connected to the conductive portion in the subsequent manufacturing process. However, as shown in FIG. 7A , after the wafer 6 is bonded to the substrate 7 , the position may deviate from the standard position due to an operation error, so as shown in FIG. It also deviates from the correct position, so that it cannot correspond to the contact hole 71 of the substrate 7 accurately, and it is difficult to ensure the correctness of the connection with the external circuit in the subsequent process.

習知一種解決上述問題的方法是將底材接孔71的面積擴大,令晶片6黏晶發生誤差時仍可使偏移的導接部81落在接孔71的範圍內。惟隨著材料及技術的進步,晶片6及底材7的體積越來越小,且構造日漸精細,因而接孔71面積不能獲得足夠的提升;另一方面,擴大接孔71面積後將導致底材7的結構強度降低,使底材7更容易崩毀,因此不是一個好的解決方式。 A conventional method to solve the above problem is to enlarge the area of the substrate contact hole 71 , so that the offset guide portion 81 can still fall within the range of the contact hole 71 when an error occurs in the die bonding of the wafer 6 . However, with the advancement of materials and technology, the volume of the wafer 6 and the substrate 7 is getting smaller and smaller, and the structure is getting more and more refined, so the area of the contact hole 71 cannot be improved enough; on the other hand, enlarging the area of the contact hole 71 will lead to The structural strength of the substrate 7 is reduced, which makes the substrate 7 more likely to collapse, so it is not a good solution.

另一方面,晶片6不良地結合在底材7上的情形更包括如第7B圖所示的高低傾斜或翹曲等態樣,以致在曝光成形導接部時,光線9的焦點將如第9圖所示地不能精準地打在晶片6上,而使所成形之導接部82的線寬擴大(見第8圖),在越小的晶片上則更顯現其影響產品品質的嚴重性。 On the other hand, the situation that the wafer 6 is poorly bonded to the substrate 7 includes high and low inclination or warping as shown in FIG. 7B, so that when the formed lead portion is exposed, the focal point of the light 9 will be as shown in Fig. 7B. As shown in Fig. 9, the wafer 6 cannot be accurately hit, and the line width of the formed guide portion 82 is enlarged (see Fig. 8), and the smaller the wafer, the more serious it affects the product quality. .

習知技術為了解決上述問題,則在曝光機上設置一測距裝置,用以測量光源與晶片之間的距離,當使用曝光機進行曝光的同時進行測距,並在回傳距離資訊後即時地調整曝光焦距,進而令曝光焦點保持在晶片上。惟如第9圖所示,光源9移動進行曝光的速度甚快,相形之下,測距裝置測得距離後再控制曝光機改變焦距所花費的時間太長,以致跟不上光源9的移動速度,則仍無法良好地解決曝光線寬過大的問題。 In order to solve the above problems in the prior art, a distance measuring device is installed on the exposure machine to measure the distance between the light source and the wafer. When the exposure machine is used for exposure, the distance measurement is performed at the same time, and the distance information is sent back immediately. The exposure focus is adjusted to keep the exposure focus on the wafer. However, as shown in Figure 9, the light source 9 moves very fast for exposure. In contrast, it takes too long for the distance measuring device to measure the distance and then control the exposure machine to change the focal length, so that it cannot keep up with the movement of the light source 9. speed, it still cannot solve the problem of excessive exposure line width.

有鑑於此,如何改進上述問題即為本發明所欲解決之首要課題。 In view of this, how to improve the above problem is the primary problem to be solved by the present invention.

本發明之主要目的在於提供一種無光罩曝光機之晶片偏移校正方法,其依晶片黏晶於底材上的形狀及位置狀態計算出一補償段,以改變曝光圖形的落點位置,使曝光圖形可於對應之接孔位置上形成,達到校正因黏晶發生偏移所致誤差的功效。 The main purpose of the present invention is to provide a wafer offset correction method for a maskless exposure machine, which calculates a compensation section according to the shape and position of the wafer bonding on the substrate, so as to change the position of the exposure pattern, so as to make The exposure pattern can be formed on the corresponding contact hole position to achieve the effect of correcting the error caused by the offset of the sticky die.

為達前述之目的,本發明提供一種無光罩曝光機之晶片偏移校正方法,其中晶片結合於底材上,底材具有複數個接孔,晶片上具有複數個接點,並分別於各接點上預定曝光形成一連接至各接孔之導接部;該校正方法包括有: 以一第一預掃描手段取得該晶片的狀態資訊,包括形狀及位置資訊;將前述晶片的狀態資訊與一基準狀態進行比對,並計算將該基準狀態修正為與該晶片的狀態資訊一致的補償值;依該補償值計算出一曝光區域的補償段,使各導接部可於對應之接孔位置上形成曝光圖形。 In order to achieve the aforementioned purpose, the present invention provides a wafer offset correction method for a maskless exposure machine, wherein a wafer is bonded to a substrate, the substrate has a plurality of contact holes, and the wafer has a plurality of contacts, which are respectively connected to each other. Predetermined exposure on the contacts forms a guide portion connected to each contact hole; the calibration method includes: Obtain the state information of the wafer by a first pre-scanning method, including shape and position information; compare the state information of the wafer with a reference state, and calculate and correct the reference state to be consistent with the state information of the wafer Compensation value; according to the compensation value, a compensation segment of the exposure area is calculated, so that each lead part can form an exposure pattern at the corresponding contact hole position.

較佳地,該第一預掃描手段係為擷取晶片在底材上的影像。 Preferably, the first pre-scanning means is to capture the image of the wafer on the substrate.

於一實施例中,本校正方法更包括有:以一第二預掃描手段取得該晶片的高程資訊;將該晶片的高程資訊輸入無光罩曝光機,使無光罩曝光機在進行曝光時依該晶片的高程資訊調整焦距,以令曝光的焦點總是位於該晶片上。 In one embodiment, the calibration method further includes: obtaining the elevation information of the wafer by a second pre-scanning method; inputting the elevation information of the wafer into the maskless exposure machine, so that the maskless exposure machine performs exposure during exposure. The focus is adjusted according to the elevation information of the wafer, so that the focus of exposure is always on the wafer.

較佳地,該第二預掃描手段係為以雷射測距儀測定其與晶片之間的距離。 Preferably, the second pre-scanning means is to measure the distance between it and the wafer with a laser range finder.

本發明之上述目的與優點,不難從以下所選用實施例之詳細說明與附圖中獲得深入了解。 The above-mentioned objects and advantages of the present invention can be easily understood from the detailed description and accompanying drawings of the following selected embodiments.

1:晶片 1: Wafer

10:接點 10: Contact

2:底材 2: Substrate

21:接孔 21: Access hole

3:導接部 3: Guide part

4:補償段 4: Compensation section

5:光線 5: Light

6:晶片 6: Wafer

7:底材 7: Substrate

71:接孔 71: Access hole

81、82:導接部 81, 82: guide part

9:光線 9: Light

第1圖為本發明晶片偏移校正方法之流程圖,用以校正曝光圖形的位置;第2圖為本發明顯示晶片狀態資訊之影像示意圖;第3圖為本發明基準檔之示意圖;第4圖為使用本發明方法校正後之結果示意圖;第5圖為本發明晶片偏移校正方法之流程圖,用以校正曝光圖形的線寬;第6圖為使用本發明方法校正後之曝光機操作過程示意圖; 第7A、7B圖為習知晶片黏晶在晶圓上之示意圖;第8圖為習知不良晶片進行曝光後之曝光圖形示意圖;第9圖為習知不良晶片進行曝光時之曝光機操作過程示意圖。 Fig. 1 is a flow chart of the wafer offset correction method of the present invention, which is used to correct the position of the exposure pattern; Fig. 2 is a schematic diagram of an image showing the wafer status information of the present invention; Fig. 3 is a schematic diagram of a reference file of the present invention; Figure 5 is a schematic diagram of the result after calibration using the method of the present invention; Figure 5 is a flow chart of the wafer offset correction method of the present invention for correcting the line width of the exposure pattern; Figure 6 is the operation of the exposure machine after calibration using the method of the present invention Process diagram; Figures 7A and 7B are schematic diagrams of conventional wafer bonding on the wafer; Figure 8 is a schematic diagram of exposure patterns after exposure of conventional defective chips; Figure 9 is the operation process of the exposure machine when conventional defective chips are exposed Schematic.

本發明提供一種無光罩曝光機之晶片偏移校正方法,其應用於一結合於晶圓底材上的晶片結構,其中底材2具有複數個接孔21,晶片1上具有複數個接點10,各接點10可透過無光罩曝光機曝光形成一做為電路之導接部3,該導接部3預定延伸至底材2上對應的接孔21位置。 The present invention provides a chip offset correction method for a maskless exposure machine, which is applied to a chip structure bonded to a wafer substrate, wherein the substrate 2 has a plurality of contact holes 21, and the chip 1 has a plurality of contacts 10. Each contact 10 can be exposed by a maskless exposure machine to form a lead portion 3 serving as a circuit. The lead portion 3 is intended to extend to the corresponding contact hole 21 on the substrate 2 .

本發明之校正方法,如第1圖所示,包括有:以一第一預掃描手段取得該晶片的狀態資訊,包括形狀及位置資訊;將前述晶片的狀態資訊與一基準狀態進行比對,並計算將該基準狀態修正為與該晶片的狀態資訊一致的補償值;依該補償值計算出一曝光區域的補償段,使各導接部可於對應之接孔位置上形成曝光圖形。 The calibration method of the present invention, as shown in FIG. 1, includes: obtaining state information of the wafer, including shape and position information, by a first pre-scanning means; comparing the state information of the wafer with a reference state, And calculate the compensation value that corrects the reference state to be consistent with the state information of the chip; calculates a compensation segment of an exposure area according to the compensation value, so that each lead part can form an exposure pattern at the corresponding contact hole position.

將晶片1結合至晶圓底材2上(又稱黏晶)的過程中,有時會如第2圖所示地產生偏離於預定位置的情形,因而使預定曝光形成的導接部3也隨之偏離正確位置,以致無法與底材2的接孔21準確對應,難以確保後續製程中與外部電路連接的正確性。因此,本發明之校正方法首先以一第一預掃描手段取得該晶片1的狀態資訊,包括形狀及位置資訊;於本實施例中,該第一預掃描手段是以影像擷取裝置擷取晶片1在底材2上的影像,所擷取的影像如第2圖所示者,可在其中解析出晶片1於底材2上的形狀及位置等資訊。接 著將該晶片1的狀態資訊與一如第3圖所示的基準檔進行比對,其中該基準檔具有晶片1於底材2上的正確形狀及位置等基準狀態資訊,並對準晶片基準檔外圈位置(UBM)及對準實際晶片內接腳(DIE PAD)為基準,則經比對之後可得到兩者的差異,再以線性或非線性數值計算方式調整導接部的圖檔,進而計算出將該基準狀態修正為與該晶片1的實際形狀及位置一致的補償值。據此再依該補償值計算出一曝光區域的補償段4,使各導接部3的曝光圖形可如第4圖所示地藉由該補償段4連接到對應之接孔21位置上,而在該晶片1之各接點10與對應之接孔21之間形成連續無斷差的佈線,進而校正因黏晶發生偏移所致的誤差。 In the process of bonding the wafer 1 to the wafer substrate 2 (also known as die bonding), as shown in Fig. 2, the situation may sometimes deviate from the predetermined position, so that the conductive portion 3 formed by the predetermined exposure is also As a result, it deviates from the correct position, so that it cannot correspond to the contact hole 21 of the substrate 2 accurately, and it is difficult to ensure the correctness of the connection with the external circuit in the subsequent process. Therefore, the calibration method of the present invention first obtains the state information of the wafer 1 by a first pre-scanning means, including shape and position information; in this embodiment, the first pre-scanning means captures the wafer by an image capture device 1. The image on the substrate 2. The captured image is as shown in FIG. 2, in which information such as the shape and position of the wafer 1 on the substrate 2 can be analyzed. catch Then, the state information of the wafer 1 is compared with a reference file as shown in FIG. 3, wherein the reference file has reference state information such as the correct shape and position of the wafer 1 on the substrate 2, and is aligned with the wafer reference The position of the outer ring of the gear (UBM) and the alignment of the actual chip internal pins (DIE PAD) are used as benchmarks. After comparison, the difference between the two can be obtained, and then the drawing file of the lead part can be adjusted by linear or nonlinear numerical calculation. , and then calculate the compensation value for correcting the reference state to be consistent with the actual shape and position of the wafer 1 . Accordingly, a compensation section 4 of the exposure area is calculated according to the compensation value, so that the exposure pattern of each lead portion 3 can be connected to the corresponding contact hole 21 through the compensation section 4 as shown in FIG. 4 . A continuous and unbroken wiring is formed between each contact point 10 of the wafer 1 and the corresponding contact hole 21, so as to correct the error caused by the offset of the die bonding.

再者,如第5圖所示,本發明更進一步地提供校正曝光線寬的方法,其包括有:以一第二預掃描手段取得該晶片的高程資訊;將該晶片的高程資訊輸入無光罩曝光機,使無光罩曝光機在進行曝光時依該晶片的高程資訊調整焦距,以令曝光的焦點總是位於該晶片上。 Furthermore, as shown in FIG. 5, the present invention further provides a method for calibrating the exposure line width, which includes: obtaining the elevation information of the wafer by a second pre-scanning method; inputting the elevation information of the wafer into a matte The mask exposure machine enables the maskless exposure machine to adjust the focal length according to the elevation information of the wafer during exposure, so that the exposure focus is always located on the wafer.

上述該第二預掃描手段可以是一雷射測距儀,藉由測定其與晶片之間的距離以描繪出晶片的高程資訊。上述該第二預掃描手段係於開始進行曝光作業之前就先實施,以預先取得晶片的高程資訊;較佳地,該第二預掃描手段可與前述該第一預掃描手段一起進行。接著,將取得的晶片高程資訊輸入無光罩曝光機,令其可在進行曝光的過程中,如第6圖所示,即時地依據預先取得晶片1的高程資訊變化曝光的焦距,使光線5的焦點總是保持在晶片1上,進而維持曝光的線寬而不會被放大,以提升產品的良率。 The above-mentioned second pre-scanning means may be a laser range finder, which depicts the elevation information of the wafer by measuring the distance between it and the wafer. The above-mentioned second pre-scanning means is implemented before the exposure operation is started, so as to obtain the elevation information of the wafer in advance; preferably, the second pre-scanning means can be performed together with the aforementioned first pre-scanning means. Then, the obtained wafer elevation information is input into the maskless exposure machine, so that it can change the exposure focal length in real time according to the pre-acquired elevation information of the wafer 1 during the exposure process, as shown in Fig. 6, so that the light 5 The focal point is always kept on the wafer 1, thereby maintaining the exposed line width without being enlarged, so as to improve the yield of the product.

惟以上實施例之揭示僅用以說明本發明,並非用以限制本發明,舉凡等效元件之置換仍應隸屬本發明之範疇。 However, the disclosure of the above embodiments is only used to illustrate the present invention, not to limit the present invention, and the replacement of equivalent elements should still belong to the scope of the present invention.

綜上所述,可使熟知本領域技術者明瞭本發明確可達成前述目的,實已符合專利法之規定,爰依法提出申請。 To sum up, those skilled in the art can understand that the present invention can achieve the above-mentioned purpose, and it complies with the provisions of the Patent Law.

Claims (4)

一種無光罩曝光機之晶片偏移校正方法,其中晶片結合於底材上,底材具有複數個接孔,晶片上具有複數個接點,並分別於各接點上預定曝光形成一連接至各接孔之導接部;該校正方法包括有:以一第一預掃描手段取得該晶片的狀態資訊,包括形狀及位置資訊;將前述晶片的狀態資訊與一基準狀態進行比對,並計算將該基準狀態修正為與該晶片的狀態資訊一致的補償值;依該補償值計算出一曝光區域的補償段,其中該補償段係自各導接部連接至對應之接孔,使該晶片之各接點與對應之接孔之間形成連續無斷差的佈線。 A method for correcting wafer offset of a maskless exposure machine, wherein the wafer is bonded to a substrate, the substrate has a plurality of contact holes, the wafer has a plurality of contacts, and each contact is pre-exposed to form a connection to the The guide portion of each contact hole; the calibration method includes: obtaining state information of the chip, including shape and position information, by a first pre-scanning means; comparing the state information of the chip with a reference state, and calculating Correcting the reference state to a compensation value consistent with the state information of the chip; calculating a compensation segment of the exposure area according to the compensation value, wherein the compensation segment is connected from each lead portion to the corresponding contact hole, so that the chip is A continuous and uninterrupted wiring is formed between each contact and the corresponding contact hole. 如請求項1所述之無光罩曝光機之晶片偏移校正方法,其中,該第一預掃描手段係為擷取晶片在底材上的影像。 The wafer offset correction method for a maskless exposure machine according to claim 1, wherein the first pre-scanning means is to capture an image of the wafer on the substrate. 如請求項1所述之無光罩曝光機之晶片偏移校正方法,其中更包括有:以一第二預掃描手段取得該晶片的高程資訊;將該晶片的高程資訊輸入無光罩曝光機,使無光罩曝光機在進行曝光時依該晶片的高程資訊調整焦距,以令曝光的焦點總是位於該晶片上。 The wafer offset correction method for a maskless exposure machine as claimed in claim 1, further comprising: obtaining the elevation information of the wafer by a second pre-scanning means; inputting the elevation information of the wafer into the maskless exposure machine , so that the maskless exposure machine adjusts the focal length according to the elevation information of the wafer during exposure, so that the exposure focus is always located on the wafer. 如請求項3所述之無光罩曝光機之晶片偏移校正方法,其中,該第二預掃描手段係為以雷射測距儀測定其與晶片之間的距離。 The wafer offset correction method for a maskless exposure machine according to claim 3, wherein the second pre-scanning means is to measure the distance between the wafer and the wafer with a laser range finder.
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