TWI751839B - Merge and split sar analog-digital converter - Google Patents

Abstract

The tri-level switch of a merge and split SAR analog-digital converter selectively couples the second end of the positive capacitor to the second end of the negative capacitor, lets the second end of the positive capacitor to the reference voltage, the ground or the adjustment voltage, or lets the second end of the negative capacitor to the reference voltage, the ground or the adjustment voltage. The potential of the adjustment voltage is 3/2, 3/4, or 3/8 times the potential of the reference voltage to make the capacitor capacity used by the merge and split capacitor array can be reduced, and the layout area of the merge and split SAR analog-digital converter is greatly reduced.

Description

Split-merge progressive approximation to analog-to-digital converter

The present invention relates to a progressive approximation analog-to-digital converter, in particular to a split-merge type progressive approximation analog-to-digital converter.

Successive-approximation register ADC (Successive-approximation register ADC) is a device that converts continuous analog signals into digital signals. The potential of the array is compared and the charge of the capacitor array is redistributed, so that the potential comparison of the two groups of capacitor arrays in each cycle can conform to the binary search method, and the comparison result of each cycle is the converted digital signal. .

Please refer to Patent Publication No. I644520 of the Republic of China, which is the approved patent of the inventor of the present application, which is a split-merge-type progressive approximation-analog digital converter. A three-stage switch enables a capacitor array to be selectively coupled to the analog digital converter. The reference voltage, the ground terminal or the half reference voltage allows the capacitor with the smallest capacity to perform a period of potential comparison, so that the original capacitor array designed as an N-bit gradually approximating analog digital converter can become an N+1-bit digital converter. The progressive approximation of the analog-to-digital converter greatly reduces the required capacitance and reduces the overall area and power consumption of the progressive approximation of the analog-to-digital converter.

The main purpose of the present invention is to allow the capacitor array to be connected to a regulated voltage by means of a three-stage switch, in addition to enabling the split-merge progressive approximation analog digital converter to have N+1 bits, it can further reduce the required The required capacitance capacity is reduced, and the overall layout area and the loss when switching the capacitor array are reduced.

A split and merged gradual approximation analog digital converter of the present invention includes a split and merged capacitor array, a plurality of three-level switches, a comparator and a SAR logic circuit, and the split and merged capacitor array has a plurality of A positive terminal capacitor and a plurality of negative terminal capacitors, a first terminal of each positive terminal capacitor is electrically connected to a positive terminal potential line, and a first terminal of each negative terminal capacitor is electrically connected to a negative terminal potential line, Each of the three-stage switching switches is electrically connected to a second terminal of each of the positive terminal capacitors and a second terminal of each of the negative terminal capacitors, and each of the three-stage switching switches selectively switches the second terminal of each of the positive terminal capacitors. The terminal is coupled to the second terminal of the negative terminal capacitor, or the second terminal of each positive terminal capacitor is coupled to a reference voltage, a ground terminal or an adjustment voltage, or the negative terminal capacitor is connected to the The second terminal is coupled to the reference voltage, the ground terminal or the adjustment voltage, wherein the potential of the adjustment voltage is 3/2, 3/4 or 3/8 times the potential of the reference voltage, and the comparator is electrically connected The positive-end potential line and the negative-end potential line, and the comparator outputs a comparison signal, the SAR logic circuit receives the comparison signal, and the SAR logic circuit controls the three-stage switching switches according to the comparison signal.

The present invention selectively couples the second terminal of each positive terminal capacitor to the second terminal of each negative terminal capacitor, or allows the second terminal of each positive terminal capacitor to be selectively coupled by each of the three-stage switching switches be coupled to the reference voltage, the ground terminal or the adjustment voltage, or the second terminal of each negative terminal capacitor is coupled to the reference voltage, the ground terminal or the adjustment voltage, and the potential of the adjustment voltage is the The potential of the reference voltage is 3/2, 3/4 or 3/8 times, so that the capacitance used by the split-combined capacitor array of the present invention can be reduced, and the split-combined type is gradually approaching analog digital. The layout area of the converter.

Please refer to FIG. 1, which is an embodiment of the present invention, a block diagram of a split-merge progressive approximation-to-analog digital converter 100, the split-merge progressive approximation analog-to-digital converter 100 has a split-merge capacitor The array 110 , a plurality of three-stage switching switches 120 , a comparator 130 , a SAR logic circuit 140 , a positive-end sampling switch 150 and a negative-end sampling switch 160 . The split-combined capacitor array 110 has a plurality of positive terminal capacitors 111 and a plurality of negative terminal capacitors 112 , one end of each positive terminal capacitor 111 is electrically connected to a positive terminal potential line PL, and each positive terminal capacitor 111 has a The other end is electrically connected to each of the three-stage switching switches 120, one end of each of the negative-end capacitors 112 is electrically connected to a negative-end potential line NL, and the other end of each of the negative-end capacitors 112 is electrically connected to each of the three-stage Toggle switch 120 . Each of the three-stage switch 120 selectively couples the other end of each positive end capacitor 111 to the other end of the negative end capacitor 112 , or couples the other end of each positive end capacitor 111 to a reference voltage V _r , a ground terminal or an adjustment voltage V _g , or the other end of each negative terminal capacitor 112 is coupled to the reference voltage V _r , the ground terminal or the adjustment voltage V _g . In this embodiment, the adjustment The potential of the voltage V _g is 3/2, 3/4 or 3/8 times the potential of the reference voltage V _{r .}

The comparator 130 is electrically connected to the positive-end potential line PL and the negative-end potential line NL, and the comparator 130 is used for comparing the potentials of the positive-end potential line PL and the negative-end potential line NL and outputting a comparison signal S _c to the SAR logic circuit 140, the SAR logic circuit 140 based on the comparison signal S _c outputs a plurality of control signals S _p, S _n, S _ms controlling the plurality of three switch 120, and the SAR logic circuit 140 outputs a digital Output signal D _out .

The positive terminal sampling switch 150 is electrically connected to a positive terminal voltage input terminal T _p and the positive terminal potential line PL. During the sampling stage, the positive terminal sampling switch 150 is turned on, and a positive terminal voltage V _inp is input through the positive terminal voltage The terminal T _p and the positive terminal sampling switch 150 are transmitted to the positive terminal potential line PL and charge the positive terminal capacitors 111 to accumulate charges. The negative terminal sampling switch 160 is electrically connected to a negative terminal voltage input terminal T _n and the negative terminal potential line NL. During the sampling stage, the negative terminal sampling switch 160 is turned on, and a negative terminal voltage V _inn is input through the negative terminal voltage transmitter T _n and the negative terminal of the sampling switch 160 to the negative terminal potential line NL and the more negative terminal of the capacitor 112 is charged while the electric charge is accumulated, wherein the positive voltage V _inp subtracting the negative terminal electrically sampled voltage is equal to V _inn .

Please refer to FIG. 2 , which is a circuit diagram of the split-merge progressive approximation analog-to-digital converter 100 of this embodiment, wherein the positive terminal capacitors 111 include three first positive terminal capacitors 113 and three second positive terminal capacitors The terminal capacitors 114, the negative terminal capacitors 112 include three first negative terminal capacitors 115 and three second negative terminal capacitors 116, the three-stage switch 120 has three first three-stage switch 121 and three second Three-stage switch 122, each of the first three-stage switch 121 has a first merge switch 121a, a first positive terminal switch 121b and a first negative terminal switch 121c, each of the second three-stage switch 122 There is a second merging switch 122a, a second positive terminal switch 122b and a second negative terminal switch 122c. In this embodiment, the split-and-merge type gradually approximating the analog-to-digital converter 100 with 4+1 bits is taken as an example for convenience of description, but in other embodiments, the split-and-merge type gradually approximates the analog-to-digital converter 100 can have more positive terminal capacitors, negative terminal capacitors, and three-level switches, so that the split-merge approximation analog digital converter 100 has a higher bit count.

Please refer to FIG. 2 again, one of the first terminals 113 a and 114 a of each of the first and second positive terminal capacitors 113 and 114 is electrically connected to the positive terminal potential line PL, and each of the first and second positive terminal capacitors 113 A second terminal 113b, 114b of 114 is respectively electrically connected to the first positive terminal switch 121b of each of the first three-stage switch 121 and the second positive terminal of each second three-stage switch 122 Toggle switch 122b. A first terminal 115a, 116a of each of the first and second negative terminal capacitors 115, 116 is electrically connected to the negative terminal potential line NL, and a second terminal of each of the first and second negative terminal capacitors 115, 116 115b and 116b are respectively electrically connected to the first negative terminal switch 121c of each of the first three-stage switch switches 121 and the second negative terminal switch 122c of each of the second three-stage switch switches 122 . Two ends of each of the first merging switches 121a are electrically connected to each of the first positive-end switching switches 121b and each of the first negative-end switching switches 121c, respectively, and two ends of each of the second merging switches 122a are respectively electrically connected to each of the The second positive terminal switch 122b and each of the second negative terminal switch 122c.

Among the first three-stage switching switches 121, the first positive terminal switching switch 121b of the first three-stage switching switch 121 on the left side can switch the second terminal 113b of the first positive terminal capacitor 113 on the left side to connect To the ground terminal, the reference voltage V _r , the adjustment voltage (the potential magnitude _{is 3/2 of the reference voltage V r} , so the figure is marked as 3/2 V _r ) or the first merging switch 121a, the left The first negative terminal switch 121c of a three-stage switch 121 can switch the second terminal 115b of the first negative terminal capacitor 115 on the left side to the ground terminal, the reference voltage V _r , the adjustment voltage (potential The magnitude is 3/2 of the reference voltage V _r , so the figure is denoted as 3/2 V _r ) or the first merge switch 121a. The first positive terminal switch 121b of the first three-stage switch 121 in the middle can switch the second terminal 113b of the first positive terminal capacitor 113 in the middle to the ground terminal, the reference voltage V _r , the Adjust the voltage (the potential size _{is 3/4 of the reference voltage V r} , so the figure is marked as 3/4 V _r ) or the first merging switch 121a, the first negative terminal of the first three-stage switch 121 in the middle The switch 121c can switch the second terminal 115b of the first negative terminal capacitor 115 in the middle to the ground terminal, the reference voltage V _r , and the adjustment voltage (the potential magnitude is 3/4 of _{the reference voltage V r ,} The diagram is therefore denoted as 3/4V _r ) or the first merge switch 121a. The first positive terminal switch 121b of the first three-stage switch 121 on the right side can switch the second terminal 113b of the first positive terminal capacitor 113 on the right side to the ground terminal, the reference voltage V _r , the Adjust the voltage (potential size _{is 3/8 of the reference voltage V r} , so the figure is marked as 3/8 V _r ) or the first merging switch 121a, the first negative terminal of the first three-stage switch 121 on the right side The switch 121c can switch the second terminal 115b of the first negative terminal capacitor 115 on the right side to the ground terminal, the reference voltage V _r , and the adjustment voltage (potential magnitude is 3/8 of _{the reference voltage V r ,} The drawing is therefore denoted as 3/8V _r ) or the first merge switch 121a.

Among the second tertiary switches 122, the second positive terminal switch 122b of the left second tertiary switch 122 can switch the second terminal 114b of the left second positive terminal capacitor 114 to connect To the ground terminal, the reference voltage V _r , the adjustment voltage (potential size _{is 3/2 of the reference voltage V r} , so the figure is marked as 3/2 V _r ) or the second merging switch 122a, the left The second negative terminal switch 122c of the two-stage three-stage switch 122 can switch the second terminal 116b of the second negative terminal capacitor 116 on the left side to the ground terminal, the reference voltage V _r , the adjustment voltage (potential The magnitude is 3/2 of the reference voltage V _r , so the figure is denoted as 3/2 V _r ) or the second merge switch 122a. The second positive terminal switch 122b of the second three-stage switch 122 in the middle can switch the second terminal 114b of the second positive terminal capacitor 114 in the middle to the ground terminal, the reference voltage V _r , the Adjust the voltage (potential size _{is 3/4 of the reference voltage V r} , so the figure is marked as 3/4 V _r ) or the second merging switch 121a, the second negative terminal of the second three-stage switch 122 in the middle The switch 1221c can switch the second terminal 116b of the second negative terminal capacitor 116 in the middle to the ground terminal, the reference voltage V _r , the adjustment voltage (potential magnitude is 3/4 of _{the reference voltage V r ,} The drawing is therefore denoted 3/4V _r ) or the second merge switch 122a. The second positive terminal switch 122b of the second three-stage switch 122 on the right side can switch the second terminal 114b of the second positive terminal capacitor 114 on the right side to the ground terminal, the reference voltage V _r , the Adjust the voltage (potential size _{is 3/8 of the reference voltage V r} , so the figure is marked as 3/8 V _r ) or the second merging switch 122a, the second negative terminal of the second three-stage switch 122 on the right side The switch 122c can switch the second terminal 116b of the second negative terminal capacitor 116 on the right side to the ground terminal, the reference voltage V _r , and the adjustment voltage (potential magnitude is 3/8 of _{the reference voltage V r ,} The drawing is therefore denoted 3/8V _r ) or the second merge switch 122a.

A positive input terminal 131 and a negative input terminal 132 of the comparator 130 are respectively electrically connected to the positive terminal potential line PL and the negative terminal potential line NL. Therefore, when the potential of the positive terminal potential line PL is high, the _{The comparison signal S c} output by the comparator 130 is at a high level. When the potential of the negative terminal potential line NL is at a high level, the comparison signal S _c output by the comparator 130 is at a low level. The SAR logic circuit 140 outputs a plurality of split and merge control signals S _ms1-6 , a plurality of positive terminal control signals S _p1-6 and a plurality of negative terminal control signals S _n1-6 according to the comparison signal S _c to control each of the The first merging switch 121a, each of the second merging switches 122a, each of the first positive terminal switch 121b, each of the second positive terminal switch 122b, each of the first negative terminal switch 121c and each of the second negative terminal Toggle switch 122c. When each of the first positive terminal switch 121b and the corresponding first negative terminal switch 121c are switched, the second terminal 113b of each first positive terminal capacitor 113 and each of the first negative terminal capacitors 115 are switched. When the second terminal 115b is coupled to each of the first combining switches 121a, each of the first combining switches 121a is turned on, so that each of the first positive terminal capacitors 113 and each of the first negative terminal capacitors 115 are coupled and combined. Similarly, when each of the second positive terminal switch 122b and the corresponding second negative terminal switch 122c are switched, the second terminal 114b of each of the second positive terminal capacitors 114 and each of the second negative terminal capacitors are switched. When the second end 116b of 116 is coupled to each of the second merging switches 122a, each of the second merging switches 122a is turned on, so that each of the second positive terminal capacitors 114 and each of the second negative terminal capacitors 116 are coupled and merged .

In the 4+1-bit split-and-merge gradual approximation analog-to-digital converter 100 of the present embodiment, the first positive terminal capacitors 113 and the second positive terminal capacitors 113 and the second positive terminal capacitors 113 and the second positive terminals are respectively controlled by controlling the three-stage switching switches 120 . The terminal capacitors 114 , the first negative terminal capacitors 115 and the second negative terminal capacitors 116 are coupled to the adjustment voltage whose _{potential is 3/2, 3/4 and 3/8 times the reference voltage V r .} Let these capacitors use capacitors with a capacity of 1C to reduce the layout area of the capacitor array. Even if this case is expanded to a 10-bit structure, the largest capacitance in the capacitor array is only 48C. Since the layout area of the capacitor array is gradually approaching the largest part of the analog digital converter, this embodiment can greatly reduce the The split-merge method gradually approaches the layout area required by the entire analog-to-digital converter 100 , wherein the unit capacitance value C is 1 fF.

Please refer to FIGS. 3 to 13, which are circuit diagrams of the switching process of the three-level switch 120 of the split-merge-type gradual approximation analog-to-digital converter 100 of the present invention. First, please refer to FIG. 3, the positive terminal The sampling switch 150 and the negative-end sampling switch 160 are closed to allow the positive-end potential line PL and the negative-end potential line NL to receive the positive-end voltage V _inp and the negative-end voltage V _inn , respectively. The second terminal and the second terminal of the second negative terminal capacitors 116 receive the reference voltage V _r , the second terminal of the second positive terminal capacitor 114 and the second terminal of the first negative terminal capacitor 115 Then it is connected to the ground terminal, so that the capacitors accumulate charge. At this time, the potential of the positive terminal potential line PL is the positive terminal voltage V _inp , and the potential of the negative terminal potential line NL is the negative terminal voltage V _inn .

Please refer to FIG. 4 , the positive-end sampling switch 150 and the negative-end sampling switch 160 are turned off, and the comparator 130 compares the potentials of the positive-end potential line PL and the negative-end potential line NL with the first bit , if the potential of the positive terminal potential line PL is greater than the potential of the negative terminal potential line NL, output 1, otherwise, output 0. Next, please refer to FIG. 5, when the potential of the positive terminal potential line PL is greater than the potential of the negative terminal potential line NL, each of the first positive terminal capacitors 113 and each of the first negative terminal capacitors 115 are switched to be mutually coupled Then, the second positive terminal capacitors 114 and the second negative terminal capacitors 116 remain coupled to the ground terminal and the reference voltage V _{r , respectively} . At this time, the charges of the capacitors are redistributed. According to the law of charge conservation, the potential of the positive terminal potential line PL changes to V _inp -1/4V _r , and the potential of the negative terminal potential line NL changes to V _inn +1/4V _r , therefore, the comparator 130 can determine that V _inp -V _inn >1/2V _r or V _inp -V _inn <1/2V _{r by} comparing the second bit, which is consistent with the binary search method. On the other hand, please refer to FIG. 6, if in the comparison of the first bit, the potential of the positive terminal potential line PL is lower than the potential of the negative terminal potential line NL, the second positive terminal capacitors 114 and the first The two negative terminal capacitors 116 are switched to be coupled to each other, and the first positive terminal capacitors 113 and the first negative terminal capacitors 115 remain coupled to the reference voltage V _r and the ground terminal, respectively. At this time, the charges of the capacitors are redistributed. According to the law of charge conservation, the potential of the positive terminal potential line PL changes to V _inp +1/4V _r , and the potential of the negative terminal potential line NL changes to V _inn -1/4V _r , therefore, the comparator 130 can determine that V _inp -V _inn >-1/2V _r or V _inp -V _inn <-1/2V _{r by} comparing the second bit, which conforms to the binary search method.

Referring to FIG. 7, when the first bit comparison is 1 and the second bit comparison result V _inp -V _inn > 1/2V _r is also 1, the first positive terminal capacitor 113 on the left is switched to is coupled to the ground terminal, and the first negative terminal capacitor 115 on the left is switched to be coupled to the adjustment voltage 3/2V _r , and the rest of the first positive terminal capacitor 113 , the second positive terminal capacitor 114 , and the first The negative terminal capacitor 115 and the second negative terminal capacitor 116 remain unswitched. At this time, the charges of the capacitors are redistributed. According to the law of charge conservation, the potential of the positive terminal potential line PL changes to V _inp -3/8V _r , and the potential of the negative terminal potential line NL changes to V _inn +3/8V _r , therefore, the comparator 130 can determine that V _inp -V _inn >3/4V _r or V _inp -V _inn <3/4V _{r by} comparing the third bit, which can surely conform to the binary search method. On the other hand, please refer to Figure 8, when the first bit comparison is 1 and the second bit comparison result V _inp -V _inn <1/2V _ref is 0 and the second positive terminal capacitor on the left is 114 is switched to be coupled to the adjustment voltage 3/2V _r , and the second negative terminal capacitor 116 on the left side is switched to be coupled to the ground terminal, and the rest of the first positive terminal capacitor 113 , the second positive terminal capacitor 114 , The first negative terminal capacitor 115 and the second negative terminal capacitor 116 remain unswitched. At this time, the charges of the capacitors are redistributed. According to the law of charge conservation, the potential of the positive terminal potential line PL changes to V _inp -1/8V _r , and the potential of the negative terminal potential line NL changes to V _inn +1/8V _r Therefore, the comparator 130 can determine that V _inp -V _inn >1/4V _r or V _inp -V _inn <1/4V _{r by} comparing the third bit, which is consistent with the binary search method.

Please refer to Figure 9, when the 1st bit alignment is 1, the 2nd bit alignment is 1, and the 3rd bit alignment result V _inp -V _inn >3/4V _r is 1, the middle The first positive terminal capacitor 113 is switched to be coupled to the ground terminal, and the first negative terminal capacitor 115 in the middle is switched to be coupled to the adjustment voltage 3/4V _r , and the rest of the first positive terminal capacitor 113, the third The two positive terminal capacitors 114 , the first negative terminal capacitor 115 and the second negative terminal capacitor 116 remain unswitched. At this time, the charges of the capacitors are redistributed. According to the law of charge conservation, the potential of the positive terminal potential line PL changes to V _inp -7/16V _r , and the potential of the negative terminal potential line NL changes to V _inn +7/16V _r , therefore, the comparator 130 can determine that V _inp -V _inn >7/8V _r or V _inp -V _inn <7/8V _{r by} comparing the fourth bit, which can surely conform to the binary search method. Relatively, please refer to Figure 10. When the first bit alignment is 1, the second bit alignment is 1, and the third bit alignment result is V _inp -V _inn <3/4V _r , the middle The second positive terminal capacitor 114 is switched to be coupled to the adjustment voltage 3/4V _r , and the second negative terminal capacitor 116 in the middle is switched to be coupled to the ground terminal, and the rest of the first positive terminal capacitor 113 , the The second positive terminal capacitor 114 , the first negative terminal capacitor 115 and the second negative terminal capacitor 116 remain unswitched. At this time, the charges of these capacitors are redistributed. According to the law of charge conservation, the potential of the positive terminal potential line PL Changed to V _inp -5/16V _r , the potential of the negative terminal potential line NL is changed to V _inn +5/16V _r , therefore, the comparator 130 can determine that V _inp -V _inn > 5/8V _r or V _inp -V _inn <5/8V _r , which is consistent with the binary search method.

Please refer to Figure 11, when the 1-bit alignment is 1, the 2-bit alignment is 1, the 3-bit alignment is 1, and the 4-bit alignment result is V _inp -V _inn >7/8V _r , the first positive terminal capacitor 113 on the right side is switched to be coupled to the ground terminal, the first negative terminal capacitor 115 on the right side is switched to be coupled to the adjustment voltage 3/8V _r , and the rest of the first positive terminal The terminal capacitor 113 , the second positive terminal capacitor 114 , the first negative terminal capacitor 115 and the second negative terminal capacitor 116 remain unswitched. At this time, the charges of these capacitors are redistributed. According to the law of charge conservation, the positive terminal The potential of the potential line PL is changed to V _inp -15/32V _r , and the potential of the negative terminal potential line NL is changed to V _inn +15/32V _r . Therefore, the comparator 130 can determine V by comparing the fifth bit. _inp -V _inn > 15/16V _r or V _inp -V _inn < 15/16V _r , and the binary search method can be met with certainty.

Please refer to Figure 12, when the 1-bit alignment is 1, the 2-bit alignment is 1, the 3-bit alignment is 0, and the 4-bit alignment result is V _inp -V _inn >5/8V _r , the first positive terminal capacitor 113 on the right side is switched to be coupled to the ground terminal, and the first negative terminal capacitor 115 on the right side is switched to be coupled to the adjustment voltage 3/8V _r , so that the positive terminal potential The potential of the line PL is changed to V _inp -11/32V _r , and the potential of the negative terminal line NL is changed to V _inn +11/32V _r . Therefore, the comparator 130 can determine V _{inp by comparing the fifth bit.} -V _inn > 11/16V _r or V _inp -V _inn < 11/16V _r , and the binary search method can be reliably met.

Please refer to Figure 13, when the 1-bit alignment is 1, the 2-bit alignment is 0, the 3-bit alignment is 1, and the 4-bit alignment result is V _inp -V _inn > 3/8V _r , the first positive terminal capacitor 113 on the right side is switched to be coupled to the ground terminal, and the first negative terminal capacitor 115 on the right side is switched to be coupled to the adjustment voltage 3/8V _r , so that the positive terminal potential The potential of the line PL changes to V _inp -7/32V _r , and the potential of the negative terminal line NL changes to V _inn +7/32V _r . Therefore, the comparator 130 can determine V _{inp by comparing the fifth bit.} -V _inn > 7/16V _r or V _inp -V _inn < 7/16V _r , and the binary search method can be met with certainty.

The present invention selectively couples the positive terminal capacitors 111 to the negative terminal capacitors 112, or allows the second terminal of the positive terminal capacitors 111 to be coupled to the reference through the three-stage switch 120. voltage V _r , the ground terminal or the adjustment voltage V _g , or the second terminal of each negative terminal capacitor 112 is coupled to the reference voltage V _r , the ground terminal or the adjustment voltage V _g , and the adjustment voltage The potential of V _g is 3/2, 3/4 or 3/8 times of the potential of the reference voltage V _r , so that the capacitance used by the split-merge capacitor array 110 of the present invention can be reduced, and greatly reduced The split-and-merge approach gradually approaches the layout area of the analog-to-digital converter 100 .

The protection scope of the present invention shall be determined by the scope of the appended patent application. Any changes and modifications made by anyone who is familiar with the art without departing from the spirit and scope of the present invention shall fall within the protection scope of the present invention. .

100: split and merged gradual approximation analog digital converter 110: split and merged capacitor array 111: positive terminal capacitor 112: negative terminal capacitor 113: first positive terminal capacitor 113a: first terminal 113b: second terminal 114: first terminal Two positive terminal capacitors 114a: first terminal 114b: second terminal 115: first negative terminal capacitor 115a: first terminal 115b: second terminal 116: second negative terminal capacitor 116a: first terminal 116b: second terminal 120: Three-stage switch 121: first three-stage switch 121a: first combining switch 121b: first positive terminal switch 121c: first negative terminal switch 122: second three-stage switch 122a: second combining switch 122b: Second positive terminal switch 122c: second negative terminal switch 130: comparator 131: positive terminal 132: negative input terminal 140: SAR logic circuit 150: positive terminal sampling switch 160: negative terminal sampling switch PL: positive terminal potential line NL: potential line V _r negative terminal: the reference voltage S v _c: Comparative signal V _g: adjusting a voltage S _p: the positive terminal of the control signal S _n: the negative terminal of the control signal T _p: positive voltage input terminal T _n: a negative terminal Voltage input terminal S _ms : Split and merge control signal V _inp : Positive terminal voltage _Vinn : Negative terminal voltage D _out : Digital output signal

FIG. 1 is a block diagram of a split-merge progressive approximation analog-to-digital converter according to an embodiment of the present invention. Fig. 2: According to an embodiment of the present invention, a circuit diagram of the split-merge-type progressive approximation analog-to-digital converter. Fig. 3-13: According to an embodiment of the present invention, the circuit diagram of the switching process of the three-level switch of the split-merge-type gradual approximation analog-to-digital converter.

100: Split Merge Gradual Approximation Analog-to-Digital Converter

110: Split and merged capacitor array

111: Positive terminal capacitance

112: Negative terminal capacitance

120: Three-stage toggle switch

130: Comparator

140: SAR logic circuit

150: Positive sampling switch

160: Negative end sampling circuit

V _r : reference voltage

V _g : Adjustment voltage

PL: positive terminal potential line

NL: Negative terminal potential line

T _p : Positive terminal voltage input terminal

T _n : rich terminal voltage input terminal

S _p: a positive terminal of the control signal

S _n : Rich end control signal

S _c : Comparison signal

S _ms : Split and merge control signal

V _inp : Positive terminal voltage

V _inn : negative terminal voltage

D _out : digital output signal

Claims (9)

A split-merge type gradually approximating analog digital converter, which comprises: a split-merge capacitor array, which has a plurality of positive terminal capacitors and a plurality of negative terminal capacitors, and a first terminal of each of the positive terminal capacitors is electrically connected to a positive terminal potential line, a first end of each negative terminal capacitor is electrically connected to a negative terminal potential line, the positive terminal capacitors include a plurality of first positive terminal capacitors and a plurality of second positive terminal capacitors, the The negative terminal capacitors include a plurality of first negative terminal capacitors and a plurality of second negative terminal capacitors. A first terminal of each of the first and second positive terminal capacitors is electrically connected to the positive terminal potential line. and a first terminal of the second negative terminal capacitor is electrically connected to the negative terminal potential line; a plurality of three-stage switching switches are electrically connected to a second terminal of each positive terminal capacitor and a first terminal of each negative terminal capacitor Two terminals, each of the three-stage switch selectively couples the second terminal of each positive terminal capacitor to the second terminal of the negative terminal capacitor, or couples the second terminal of each positive terminal capacitor to a reference voltage, a ground terminal, a first adjustment voltage, a second adjustment voltage or a third adjustment voltage, or the second terminal of each negative terminal capacitor is coupled to the reference voltage, the ground terminal, The first adjustment voltage, the second adjustment voltage or the third adjustment voltage, wherein the potential of the first adjustment voltage is 3/2 times the potential of the reference voltage, and the potential of the second adjustment voltage is the value of the reference voltage 3/4 times of the potential, the potential of the third adjustment voltage is 3/8 times of the potential of the reference voltage, the three-level switch includes a plurality of first three-level switch and a plurality of second three-level switch , each of the first three-stage switching switches is electrically connected to a second terminal of each of the first positive terminal capacitors and a second terminal of each of the first negative terminal capacitors, and each of the first three-stage switching switches selectively connects The second terminal of each of the first positive terminal capacitors is coupled to the second terminal of the first negative terminal capacitor, or the second terminal of each of the first positive terminal capacitors is coupled to the reference voltage, the ground terminal, the first adjustment voltage, the second adjustment voltage or the third adjustment voltage, or the second terminal of each of the first negative terminal capacitors is coupled to the reference voltage, the ground terminal, the first adjustment voltage , the second adjustment voltage or the third adjustment voltage, each of the second adjustment voltage A three-stage switch is electrically connected to a second terminal of each of the second positive terminal capacitors and a second terminal of each of the second negative terminal capacitors, and each of the second three-stage switch selectively connects each of the second positive terminal The second terminal of the terminal capacitor is coupled to the second terminal of the second negative terminal capacitor, or the second terminal of each of the second positive terminal capacitors is coupled to the reference voltage, the ground terminal, the first terminal The adjustment voltage, the second adjustment voltage or the third adjustment voltage, or the second terminal of each of the second negative terminal capacitors is coupled to the reference voltage, the ground terminal, the first adjustment voltage, the second adjustment voltage or the third adjustment voltage. ; a comparator electrically connected to the positive terminal potential line and the negative terminal potential line, and the comparator outputs a comparison signal; and a SAR logic circuit that receives the comparison signal, and the SAR logic circuit controls the SAR logic circuit according to the comparison signal These three-stage toggle switches. The split-merge-type gradual approximation-to-analog digital converter of claim 1, wherein each of the three-stage switching switches has a merge switch, and the merge switch is coupled to the second terminal of the positive terminal capacitor and the first terminal of the negative terminal capacitor two ends. The split-merge-type gradual approximation analog digital converter of claim 2, wherein each of the three-stage switching switches has a positive terminal switch and a negative terminal switch, and the positive terminal switch is electrically connected to the one of the positive terminal capacitor. A second terminal for selectively connecting the second terminal of the positive terminal capacitor to the reference voltage, the ground terminal, the adjustment voltage or the combined switch, and the negative terminal switching switch is electrically connected to the second terminal of the negative terminal capacitor terminal to selectively connect the second terminal of the negative terminal capacitor to the reference voltage, the ground terminal, the adjustment voltage or the combined switch. The split-merge-type progressive approximation-to-analog digital converter of claim 1, wherein each of the first three-stage switch has a first merge switch, a first positive-side switch and a first negative-side switch, and the third switch has a A positive terminal switch is electrically connected to the first merging switch and the first terminal of the first positive terminal capacitor two terminals to selectively connect the second terminal of the first positive terminal capacitor to the reference voltage, the ground terminal, the first adjustment voltage, the second adjustment voltage, the third adjustment voltage or the first adjustment voltage a merging switch, the first negative end switch is electrically connected to the first merging switch and the second end of the first negative end capacitor to selectively connect the second end of the first negative end capacitor to the The reference voltage, the ground terminal, the first adjustment voltage, the second adjustment voltage, the third adjustment voltage or the first merging switch. The split-merge-type progressive approximation-to-analog digital converter of claim 1, wherein each of the second three-stage switch has a second merge switch, a second positive-side switch and a second negative-side switch, the first Two positive terminal switches are electrically connected to the second combining switch and the second terminal of the second positive terminal capacitor, so as to selectively connect the second terminal of the second positive terminal capacitor to the reference voltage, the ground terminal, the first adjustment voltage, the second adjustment voltage, the third adjustment voltage or the second merging switch, the second negative terminal switch is electrically connected to the second merging switch and the second negative terminal capacitor a second terminal for selectively connecting the second terminal of the second negative terminal capacitor to the reference voltage, the ground terminal, the first adjustment voltage, the second adjustment voltage, the third adjustment voltage or the The second merge switch. As claimed in claim 1, the split-merge type gradually approximating analog-to-digital converter, wherein the comparator has a positive input terminal and a negative input terminal, the positive input terminal is electrically connected to the positive terminal potential line, and the negative input terminal is electrically connected to the negative terminal potential line. As claimed in claim 1, the split-merge progressive approximation analog digital converter comprises a positive-end sampling switch and a negative-end sampling switch, and the positive-end sampling switch is electrically connected to a positive-end voltage input end and the positive-end potential line , the negative terminal sampling switch is electrically connected to a negative terminal voltage input terminal and the negative terminal potential line. The split and merge type of claim 2 is gradually approached to an analog-to-digital converter, wherein the SAR logic circuit outputs a plurality of split and merge control signals according to the comparison signal, and each of the split and merge control signals is used to control each of the merge switches. As claimed in claim 3, the split-merge type gradually approximating the analog-to-digital converter, wherein the SAR logic circuit outputs a plurality of positive-end control signals and a plurality of negative-end control signals according to the comparison signal, and each of the positive-end control signals is used to control each The positive terminal switches and each negative terminal control number is used for each negative terminal switching switch.

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